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1. 发明授权

US08782496B2 Memory controller, semiconductor memory apparatus and decoding method 有权
标题翻译：存储控制器，半导体存储装置及解码方法
公开(公告)号：US08782496B2
公开(公告)日：2014-07-15
申请号：US13235395
申请日：2011-09-18
申请人： Kenji Sakaue , Atsushi Takayama , Yoshihisa Kondo , Tatsuyuki Ishikawa
发明人： Kenji Sakaue , Atsushi Takayama , Yoshihisa Kondo , Tatsuyuki Ishikawa
IPC分类号： G11C29/00 , H03M13/00 , H03M13/11 , H03M13/45 , G06F11/10
CPC分类号： G06F11/1068 , G06F11/1048 , G11C29/00 , H03M13/1105 , H03M13/1111 , H03M13/1137 , H03M13/116 , H03M13/1177 , H03M13/1185 , H03M13/1188 , H03M13/45 , H03M13/6502 , H03M13/6505 , H03M13/6577
摘要： A memory controller including a buffer configured to perform decoding frame-unit data decoded by an LDPC decoder through partial parallel processing based on a check matrix made up of a block of a unit matrix and a plurality of blocks in which each row of the unit matrix is sequentially shifted and store threshold decision information of the data read from a memory section, an LLR conversion section configured to convert the threshold decision information to an LLR, an LMEM configured to store probability information β calculated during iteration processing that repeatedly performs column processing and row processing based on the LLR in an iteration unit equal to or smaller than a size of the block, and a CPU core configured to transfer the probability information β stored in the LMEM to the buffer every time the iteration processing in the iteration unit is completed.
摘要翻译：一种存储器控制器，包括：缓冲器，被配置为基于由单位矩阵的块和多个块组成的校验矩阵，通过部分并行处理来执行由LDPC解码器解码的帧单元数据，其中，每行单位矩阵顺序地移位并存储从存储器部分读取的数据的阈值判定信息，被配置为将阈值判定信息转换为LLR的LLR转换部分，被配置为存储概率信息＆lt; bgr的LMEM; 在迭代处理期间计算的重复执行列处理和基于等于或小于块的大小的迭代单元中的LLR的行处理以及被配置为传送概率信息＆bgr的CPU核心; 每次迭代单元中的迭代处理完成时，将LMEM存储在缓冲区中。

2. 发明申请

US20120297273A1 MEMORY CONTROLLER, SEMICONDUCTOR MEMORY APPARATUS AND DECODING METHOD 有权
标题翻译：存储器控制器，半导体存储器和解码方法
公开(公告)号：US20120297273A1
公开(公告)日：2012-11-22
申请号：US13235395
申请日：2011-09-18
申请人： Kenji SAKAUE , Atsushi Takayama , Yoshihisa Kondo , Tatsuyuki Ishikawa
发明人： Kenji SAKAUE , Atsushi Takayama , Yoshihisa Kondo , Tatsuyuki Ishikawa
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： G06F11/1068 , G06F11/1048 , G11C29/00 , H03M13/1105 , H03M13/1111 , H03M13/1137 , H03M13/116 , H03M13/1177 , H03M13/1185 , H03M13/1188 , H03M13/45 , H03M13/6502 , H03M13/6505 , H03M13/6577
摘要： A memory controller including a buffer configured to perform decoding frame-unit data decoded by an LDPC decoder through partial parallel processing based on a check matrix made up of a block of a unit matrix and a plurality of blocks in which each row of the unit matrix is sequentially shifted and store threshold decision information of the data read from a memory section, an LLR conversion section configured to convert the threshold decision information to an LLR, an LMEM configured to store probability information β calculated during iteration processing that repeatedly performs column processing and row processing based on the LLR in an iteration unit equal to or smaller than a size of the block, and a CPU core configured to transfer the probability information β stored in the LMEM to the buffer every time the iteration processing in the iteration unit is completed.
摘要翻译：一种存储器控制器，包括：缓冲器，被配置为基于由单位矩阵的块和多个块组成的校验矩阵，通过部分并行处理来执行由LDPC解码器解码的帧单元数据，其中，每行单位矩阵顺序地移位并存储从存储器部分读取的数据的阈值判定信息，被配置为将阈值判定信息转换为LLR的LLR转换部分，被配置为存储概率信息＆lt; bgr的LMEM; 在迭代处理期间计算的重复执行列处理和基于等于或小于块的大小的迭代单元中的LLR的行处理以及被配置为传送概率信息＆bgr的CPU核心; 每次迭代单元中的迭代处理完成时，将LMEM存储在缓冲区中。

3. 发明授权

US09312885B2 Nonvolatile semiconductor memory system error correction capability of which is improved 有权
标题翻译：非易失性半导体存储器系统的纠错能力得到提高
公开(公告)号：US09312885B2
公开(公告)日：2016-04-12
申请号：US13671936
申请日：2012-11-08
申请人： Kenji Sakaue , Yoshihisa Kondo , Tarou Iwashiro
发明人： Kenji Sakaue , Yoshihisa Kondo , Tarou Iwashiro
IPC分类号： H03M13/03 , G06F11/16 , H03M13/29 , G06F11/10 , H03M13/11
CPC分类号： H03M13/2909 , G06F11/1044 , H03M13/1102 , H03M13/293 , H03M13/2948
摘要： According to one embodiment, a memory system includes a memory cell array, first error correction part, second error correction part, and third error correction part. The memory cell array includes a first storage area in which 1-bit data is stored in one memory cell, and second storage area in which data of a plurality of bits is stored in one memory cell. When data is written to the first storage area, the first error correction part generates first parity data in the row direction on the basis of the data described above. The second error correction part corrects an error of the data described above on the basis of the first parity data read from the memory cell array. The third error correction part generates second parity data in the column direction on the basis of data of a plurality of pages.
摘要翻译：根据一个实施例，存储器系统包括存储单元阵列，第一纠错部分，第二纠错部分和第三纠错部分。存储单元阵列包括其中1位数据存储在一个存储单元中的第一存储区域和多位数据被存储在一个存储单元中的第二存储区域。当数据被写入第一存储区域时，第一纠错部件基于上述数据在行方向上产生第一奇偶校验数据。第二纠错部分根据从存储单元阵列读出的第一奇偶校验数据校正上述数据的误差。第三纠错部分基于多页的数据在列方向上产生第二奇偶校验数据。

4. 发明申请

US20140053041A1 NONVOLATILE SEMICONDUCTOR MEMORY SYSTEM ERROR CORRECTION CAPABILITY OF WHICH IS IMPROVED 有权
标题翻译：非易失性半导体存储器系统错误校正能力得到改善
公开(公告)号：US20140053041A1
公开(公告)日：2014-02-20
申请号：US13671936
申请日：2012-11-08
申请人： Kenji SAKAUE , Yoshihisa Kondo , Tarou Iwashiro
发明人： Kenji SAKAUE , Yoshihisa Kondo , Tarou Iwashiro
IPC分类号： H03M13/03 , G06F11/16
CPC分类号： H03M13/2909 , G06F11/1044 , H03M13/1102 , H03M13/293 , H03M13/2948
摘要： According to one embodiment, a memory system includes a memory cell array, first error correction part, second error correction part, and third error correction part. The memory cell array includes a first storage area in which 1-bit data is stored in one memory cell, and second storage area in which data of a plurality of bits is stored in one memory cell. When data is written to the first storage area, the first error correction part generates first parity data in the row direction on the basis of the data described above. The second error correction part corrects an error of the data described above on the basis of the first parity data read from the memory cell array. The third error correction part generates second parity data in the column direction on the basis of data of a plurality of pages.
摘要翻译：根据一个实施例，存储器系统包括存储单元阵列，第一纠错部分，第二纠错部分和第三纠错部分。存储单元阵列包括其中1位数据存储在一个存储单元中的第一存储区域和多位数据被存储在一个存储单元中的第二存储区域。当数据被写入第一存储区域时，第一纠错部件基于上述数据在行方向上产生第一奇偶校验数据。第二纠错部分根据从存储单元阵列读出的第一奇偶校验数据校正上述数据的误差。第三纠错部分基于多页的数据在列方向上产生第二奇偶校验数据。

5. 发明授权

US08279670B2 Non-volatile semiconductor storage device 有权
标题翻译：非易失性半导体存储装置
公开(公告)号：US08279670B2
公开(公告)日：2012-10-02
申请号：US12882507
申请日：2010-09-15
申请人： Takuya Futatsuyama , Yoshihisa Kondo , Noboru Shibata
发明人： Takuya Futatsuyama , Yoshihisa Kondo , Noboru Shibata
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , G11C8/00 , G11C11/5621 , G11C16/0483 , G11C2211/5641
摘要： A non-volatile semiconductor storage device according to an embodiment includes: a memory cell array including an array of electrically rewritable memory cells and configured to be able to store N bits of data (where N is a natural number not less than 2) in one memory cell; and a controller operative to control read, write and erase operations of the memory cell array. The memory cell array includes a first region having a first memory cell operative to retain N bits of data, and a second region having a second memory cell operative to retain M bits of data (where M is a natural number less than N). A data structure of address data received by the controller when accessing the first memory cell is the same as a data structure of address data received from the outside when accessing the second memory cell.
摘要翻译：根据实施例的非易失性半导体存储装置包括：包括电可重写存储器单元阵列的存储单元阵列，并且被配置为能够将N位数据（其中N是不小于2的自然数）存储在一个记忆体; 以及控制器，用于控制存储单元阵列的读，写和擦除操作。存储单元阵列包括具有第一存储器单元的第一区域，该第一存储器单元可操作以保留N位数据，以及具有第二存储单元的第二区域，该第二存储单元可操作以保持M位数据（其中M是小于N的自然数）。当访问第一存储器单元时，由控制器接收的地址数据的数据结构与在访问第二存储单元时从外部接收的地址数据的数据结构相同。

6. 发明授权

US5590365A Pipeline information processing circuit for floating point operations 失效
标题翻译：流水线信息处理电路，用于浮点运算
公开(公告)号：US5590365A
公开(公告)日：1996-12-31
申请号：US408125
申请日：1995-03-21
申请人： Nobuhiro Ide , Takeshi Yoshida , Yoshihisa Kondo , Masato Nagamatsu , Junji Mori , Itaru Yamazaki
发明人： Nobuhiro Ide , Takeshi Yoshida , Yoshihisa Kondo , Masato Nagamatsu , Junji Mori , Itaru Yamazaki
IPC分类号： G06F7/57 , G06F9/38 , G06F7/38
CPC分类号： G06F7/483 , G06F9/30014 , G06F9/3826 , G06F2207/3868
摘要： Disclosed is a pipeline information processing circuit which comprises a register control unit for outputting a plurality of data held in registers at a time; an arithmetic operation unit for carrying out a collective arithmetic operation of a plurality of data; and a bypass control unit for comparing an operation result outputted from the arithmetic operation unit and a data outputted from the register control unit, selecting a data to be an object of the next arithmetic operation, and transferring the selected data to the arithmetic operation unit through a suitable bypass.
摘要翻译：公开了一种流水线信息处理电路，其包括：一次输出保存在寄存器中的多个数据的寄存器控制单元; 用于执行多个数据的集合算术运算的算术运算单元; 以及旁路控制单元，用于将从算术运算单元输出的运算结果与从寄存器控制单元输出的数据进行比较，选择下一个算术运算对象的数据，并将选择的数据传送到算术运算单元一个合适的旁路。

7. 发明申请

US20050135183A1 Non-volatile semiconductor memory device and electric device with the same 有权
公开(公告)号：US20050135183A1
公开(公告)日：2005-06-23
申请号：US10829267
申请日：2004-04-22
申请人： Yoshihisa Kondo
发明人： Yoshihisa Kondo
IPC分类号： G11C16/02 , G11C8/00 , G11C16/00 , G11C16/04 , G11C16/06 , G11C16/32
CPC分类号： G11C16/0483 , G11C16/06 , G11C16/32
摘要： A non-volatile semiconductor memory device has a memory core circuit including a cell array in which electrically rewritable and non-volatile memory cells are arranged therein, decoders configured to select the memory cells, and sense amplifiers configured to perform data read and write of the cell array, and a peripheral circuit including a memory controller configured to control data read and write in communication with the memory core circuit, wherein the memory controller has: an oscillator configured to generate an internal clock signal; a timing control circuit configured to timing control timings of data read and write of the cell array as synchronous with the internal clock signal; and a merge clock generation circuit configured to generate based on an external timing signal and the internal clock signal a merge clock signal serving for timing controlling a circuit portion in the peripheral circuit, the merge clock signal being defined as having a first signal period in which the external timing signal serves as a clock source and a second signal period without overlapping the first signal period, in which the internal clock signal serves as a clock source.

8. 发明授权

US6101621A Logic circuit and method for designing the same 失效
标题翻译：逻辑电路及其设计方法
公开(公告)号：US6101621A
公开(公告)日：2000-08-08
申请号：US733074
申请日：1996-10-16
申请人： Yoshihisa Kondo
发明人： Yoshihisa Kondo
IPC分类号： G06F7/48 , G06F7/50 , G06F7/52 , G06F7/535 , G06F9/38 , G06F17/50 , G06F11/00
CPC分类号： G06F7/535 , G06F17/5045 , G06F7/48 , G06F7/5052 , G06F7/507 , G06F9/3867 , G06F2207/3884 , G06F2207/5353
摘要： A logic circuit with a pipelined structure has a plurality stage of combinational circuits and memory circuits such as flip-flops connected among the pipeline combinational circuits. The pipeline combinational circuits constituting a logic circuit is operated at a cycle time shorter than a signal propagation time for the critical path of the pipeline combinational circuit. For the case of activation of the path not covered by this cycle time, another combinational circuit and its peripheral circuits are additionally provided for generating a correction signal. Another combinational circuit has substantially the same logic. The cycle time is determined so as to cover the critical path including another combinational circuit. A comparator circuit compares an output signal of another combinational circuit and an output signal of the combinational circuit. If both the signals are not coincident, a selector is controlled to correct the signal by using the output signal of another combinational circuit.
摘要翻译：具有流水线结构的逻辑电路具有多级的组合电路和诸如连接在管道组合电路之间的触发器的存储电路。构成逻辑电路的管线组合电路在比管道组合电路的关键路径的信号传播时间短的周期时间运行。对于未被该周期时间覆盖的路径的激活的情况，另外提供另外的组合电路及其外围电路以产生校正信号。另一组合电路具有基本上相同的逻辑。确定周期时间以覆盖包括另一组合电路的关键路径。比较器电路将另一组合电路的输出信号与组合电路的输出信号进行比较。如果两个信号不一致，则通过使用另一组合电路的输出信号来控制选择器来校正信号。

9. 发明授权

US5061101A Automatic sheet feed control system for printer 失效
标题翻译：印刷机自动进纸控制系统
公开(公告)号：US5061101A
公开(公告)日：1991-10-29
申请号：US134762
申请日：1987-12-18
申请人： Yoshihisa Kondo , Satoru Tsukihara
发明人： Yoshihisa Kondo , Satoru Tsukihara
IPC分类号： B41J13/00 , G06K15/16
CPC分类号： B41J13/0018 , B41J13/0009
摘要： An automatic sheet feed control system for a printer having an automatic sheet feeder for sequentially feeding a plurality of sheets set on a tray of the feeder to a printing position to print and output the sheets which comprises the steps of discharging the sheet upon detecting of the end of the sheet when receiving a page feed command or a sheet discharge command from an external controller and during the sheet feeding or after feeding the sheet, storing the sheet discharged, and then feeding next sheet to print from a predetermined position when the sheet is discharged at printing time, thereby preventing in advance a sheet from being wound on a platen for a long period by eliminating to allow the sheet wound on the platen to stand for a long period.
摘要翻译：一种用于打印机的自动供纸控制系统，具有自动供纸器，用于将设置在供纸器的托盘上的多个纸张顺序地进给到打印位置以打印和输出纸张，其包括在检测到纸张时排出纸张的步骤当从外部控制器接收到页面馈送命令或片材排出命令时，以及在片材进给期间或在馈送片材之后，存储被排出的片材，然后当片材为预定位置时从预定位置馈送下一张片材在打印时排出，从而通过消除使得卷绕在台板上的片材长时间放置而预防片材长时间卷绕在台板上。

10. 发明申请

US20130336188A1 WIRELESS BASE STATION AND WIRELESS COMMUNICATION SYSTEM USING THE SAME 有权
标题翻译：无线基站和无线通信系统
公开(公告)号：US20130336188A1
公开(公告)日：2013-12-19
申请号：US14000773
申请日：2012-02-16
申请人： Hiroyuki Yomo , Yoshihisa Kondo , Suhua Tang , Sadao Obana , Tetsuya Ito , Akira Matsumoto , Koichi Yoshimura
发明人： Hiroyuki Yomo , Yoshihisa Kondo , Suhua Tang , Sadao Obana , Tetsuya Ito , Akira Matsumoto , Koichi Yoshimura
IPC分类号： H04W52/02
CPC分类号： H04W52/0206 , Y02B70/32 , Y02D70/00 , Y02D70/142 , Y02D70/162
摘要： A wireless base station (1) includes a wakeup device (13) and a main device (14). When the main device (14) is in a sleep mode, the wakeup device (13) is connected to the antenna (11). Then, when the wakeup device (13) receives a wakeup signal for activating the wireless base station (1) from a terminal device assigned to the wireless base station (1) in a communication band used for wireless communication with the terminal device and when the information for identifying a wireless base station to be activated contained in the received wakeup signal is identical with the identification information of the wireless base station (1), the wakeup device (13) outputs a driving signal to the main device (14). The main device (14) transitions from the sleep mode to an operating mode in response to the driving signal from the wakeup device (13).
摘要翻译：无线基站（1）包括唤醒设备（13）和主设备（14）。当主设备（14）处于睡眠模式时，唤醒设备（13）连接到天线（11）。然后，当唤醒装置（13）在与终端装置进行无线通信的通信频带中从分配给无线基站（1）的终端装置接收到激活无线基站（1）的唤醒信号时，用于识别接收到的唤醒信号中包含的要激活的无线基站的信息与无线基站（1）的识别信息相同，所述唤醒设备（13）向主设备（14）输出驱动信号。响应于来自唤醒装置（13）的驱动信号，主装置（14）从睡眠模式转换到操作模式。

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