专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08495278B2 Controller which controls operation of nonvolatile semiconductor memory and semiconductor memory device including nonvolatile semiconductor memory and controller therefore 有权
标题翻译：因此，控制非易失性半导体存储器和包括非易失性半导体存储器和控制器的半导体存储器件的操作
公开(公告)号：US08495278B2
公开(公告)日：2013-07-23
申请号：US12554144
申请日：2009-09-04
申请人： Tarou Iwashiro , Takahide Nishiyama , Seiichi Tomita
发明人： Tarou Iwashiro , Takahide Nishiyama , Seiichi Tomita
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G06F9/3879 , G06F2212/7202 , G06F2212/7206 , Y02D10/13
摘要： A controller includes an instruction table memory, a program counter, a first decoder, and a first executing unit. The instruction table memory stores an instruction code obtained by coding a sequence to access a nonvolatile semiconductor memory. A read address in the instruction table memory is set to the program counter. The first decoder decodes the instruction code read from the instruction table memory to output a first decode signal. The first executing unit executes access to the nonvolatile semiconductor memory on the basis of the first decode signal output from the first decoder.
摘要翻译：控制器包括指令表存储器，程序计数器，第一解码器和第一执行单元。指令表存储器存储通过对序列进行编码而获得的指令代码来访问非易失性半导体存储器。指令表存储器中的读取地址设置为程序计数器。第一解码器解码从指令表存储器读取的指令代码，以输出第一解码信号。第一执行单元基于从第一解码器输出的第一解码信号执行对非易失性半导体存储器的访问。

2. 发明申请

US20110296235A1 MEMORY DEVICE 有权
标题翻译：内存设备
公开(公告)号：US20110296235A1
公开(公告)日：2011-12-01
申请号：US13021243
申请日：2011-02-04
申请人： Masaru OGAWA , Tarou Iwashiro
发明人： Masaru OGAWA , Tarou Iwashiro
IPC分类号： G06F11/16
CPC分类号： G06F11/1048 , G06F12/0246 , G06F2212/7209
摘要： According to one embodiment, a memory device includes a semiconductor memory and a controller that controls the semiconductor memory. The controller includes a first command issuing module, second command issuing module, error correction module and control module. The first command issuing module is configured to issue a read command to the semiconductor memory. The second command issuing module is configured to issue a first command instructing a process that does not involve reading data from the semiconductor memory independently from the first command issuing module to the semiconductor memory. The error correction module is configured to correct an error contained in data supplied from the semiconductor memory. The control module is configured to control the error correction module, first command issuing module and second command issuing module.
摘要翻译：根据一个实施例，存储器件包括半导体存储器和控制半导体存储器的控制器。控制器包括第一命令发布模块，第二命令发布模块，纠错模块和控制模块。第一命令发布模块被配置为向半导体存储器发出读取命令。第二指令发布模块被配置为发出指示不涉及从第一命令发布模块向半导体存储器独立地从半导体存储器读取数据的处理的第一命令。误差校正模块被配置为校正由半导体存储器提供的数据中包含的误差。控制模块被配置为控制纠错模块，第一命令发布模块和第二命令发布模块。

3. 发明申请

US20100241791A1 CONTROLLER WHICH CONTROLS OPERATION OF NONVOLATILE SEMICONDUCTOR MEMORY AND SEMICONDUCTOR MEMORY DEVICE INCLUDING NONVOLATILE SEMICONDUCTOR MEMORY AND CONTROLLER THEREFORE 有权
标题翻译：控制器，其控制非易失性半导体存储器和半导体存储器件的操作，包括非易失性半导体存储器和控制器
公开(公告)号：US20100241791A1
公开(公告)日：2010-09-23
申请号：US12554144
申请日：2009-09-04
申请人： Tarou Iwashiro , Takahide Nishiyama , Seiichi Tomita
发明人： Tarou Iwashiro , Takahide Nishiyama , Seiichi Tomita
IPC分类号： G06F12/00 , G06F12/02 , G06F9/30
CPC分类号： G06F12/0246 , G06F9/3879 , G06F2212/7202 , G06F2212/7206 , Y02D10/13
摘要： A controller includes an instruction table memory, a program counter, a first decoder, and a first executing unit. The instruction table memory stores an instruction code obtained by coding a sequence to access a nonvolatile semiconductor memory. A read address in the instruction table memory is set to the program counter. The first decoder decodes the instruction code read from the instruction table memory to output a first decode signal. The first executing unit executes access to the nonvolatile semiconductor memory on the basis of the first decode signal output from the first decoder.
摘要翻译：控制器包括指令表存储器，程序计数器，第一解码器和第一执行单元。指令表存储器存储通过对序列进行编码而获得的指令代码来访问非易失性半导体存储器。指令表存储器中的读取地址设置为程序计数器。第一解码器解码从指令表存储器读取的指令代码，以输出第一解码信号。第一执行单元基于从第一解码器输出的第一解码信号执行对非易失性半导体存储器的访问。

4. 发明授权

US08886989B2 Memory device 有权
标题翻译：内存设备
公开(公告)号：US08886989B2
公开(公告)日：2014-11-11
申请号：US13021243
申请日：2011-02-04
申请人： Masaru Ogawa , Tarou Iwashiro
发明人： Masaru Ogawa , Tarou Iwashiro
IPC分类号： G06F11/00 , G06F12/02 , G06F11/10
CPC分类号： G06F11/1048 , G06F12/0246 , G06F2212/7209
摘要： According to one embodiment, a memory device includes a semiconductor memory and a controller that controls the semiconductor memory. The controller includes a first command issuing module, second command issuing module, error correction module and control module. The first command issuing module is configured to issue a read command to the semiconductor memory. The second command issuing module is configured to issue a first command instructing a process that does not involve reading data from the semiconductor memory independently from the first command issuing module to the semiconductor memory. The error correction module is configured to correct an error contained in data supplied from the semiconductor memory. The control module is configured to control the error correction module, first command issuing module and second command issuing module.
摘要翻译：根据一个实施例，存储器件包括半导体存储器和控制半导体存储器的控制器。控制器包括第一命令发布模块，第二命令发布模块，纠错模块和控制模块。第一命令发布模块被配置为向半导体存储器发出读取命令。第二指令发布模块被配置为发出指示不涉及从第一命令发布模块向半导体存储器独立地从半导体存储器读取数据的处理的第一命令。误差校正模块被配置为校正由半导体存储器提供的数据中包含的误差。控制模块被配置为控制纠错模块，第一命令发布模块和第二命令发布模块。

5. 发明授权

US09312885B2 Nonvolatile semiconductor memory system error correction capability of which is improved 有权
标题翻译：非易失性半导体存储器系统的纠错能力得到提高
公开(公告)号：US09312885B2
公开(公告)日：2016-04-12
申请号：US13671936
申请日：2012-11-08
申请人： Kenji Sakaue , Yoshihisa Kondo , Tarou Iwashiro
发明人： Kenji Sakaue , Yoshihisa Kondo , Tarou Iwashiro
IPC分类号： H03M13/03 , G06F11/16 , H03M13/29 , G06F11/10 , H03M13/11
CPC分类号： H03M13/2909 , G06F11/1044 , H03M13/1102 , H03M13/293 , H03M13/2948
摘要： According to one embodiment, a memory system includes a memory cell array, first error correction part, second error correction part, and third error correction part. The memory cell array includes a first storage area in which 1-bit data is stored in one memory cell, and second storage area in which data of a plurality of bits is stored in one memory cell. When data is written to the first storage area, the first error correction part generates first parity data in the row direction on the basis of the data described above. The second error correction part corrects an error of the data described above on the basis of the first parity data read from the memory cell array. The third error correction part generates second parity data in the column direction on the basis of data of a plurality of pages.
摘要翻译：根据一个实施例，存储器系统包括存储单元阵列，第一纠错部分，第二纠错部分和第三纠错部分。存储单元阵列包括其中1位数据存储在一个存储单元中的第一存储区域和多位数据被存储在一个存储单元中的第二存储区域。当数据被写入第一存储区域时，第一纠错部件基于上述数据在行方向上产生第一奇偶校验数据。第二纠错部分根据从存储单元阵列读出的第一奇偶校验数据校正上述数据的误差。第三纠错部分基于多页的数据在列方向上产生第二奇偶校验数据。

6. 发明申请

US20140053041A1 NONVOLATILE SEMICONDUCTOR MEMORY SYSTEM ERROR CORRECTION CAPABILITY OF WHICH IS IMPROVED 有权
标题翻译：非易失性半导体存储器系统错误校正能力得到改善
公开(公告)号：US20140053041A1
公开(公告)日：2014-02-20
申请号：US13671936
申请日：2012-11-08
申请人： Kenji SAKAUE , Yoshihisa Kondo , Tarou Iwashiro
发明人： Kenji SAKAUE , Yoshihisa Kondo , Tarou Iwashiro
IPC分类号： H03M13/03 , G06F11/16
CPC分类号： H03M13/2909 , G06F11/1044 , H03M13/1102 , H03M13/293 , H03M13/2948
摘要： According to one embodiment, a memory system includes a memory cell array, first error correction part, second error correction part, and third error correction part. The memory cell array includes a first storage area in which 1-bit data is stored in one memory cell, and second storage area in which data of a plurality of bits is stored in one memory cell. When data is written to the first storage area, the first error correction part generates first parity data in the row direction on the basis of the data described above. The second error correction part corrects an error of the data described above on the basis of the first parity data read from the memory cell array. The third error correction part generates second parity data in the column direction on the basis of data of a plurality of pages.
摘要翻译：根据一个实施例，存储器系统包括存储单元阵列，第一纠错部分，第二纠错部分和第三纠错部分。存储单元阵列包括其中1位数据存储在一个存储单元中的第一存储区域和多位数据被存储在一个存储单元中的第二存储区域。当数据被写入第一存储区域时，第一纠错部件基于上述数据在行方向上产生第一奇偶校验数据。第二纠错部分根据从存储单元阵列读出的第一奇偶校验数据校正上述数据的误差。第三纠错部分基于多页的数据在列方向上产生第二奇偶校验数据。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式