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1. 发明授权

US5590365A Pipeline information processing circuit for floating point operations 失效
标题翻译：流水线信息处理电路，用于浮点运算
公开(公告)号：US5590365A
公开(公告)日：1996-12-31
申请号：US408125
申请日：1995-03-21
申请人： Nobuhiro Ide , Takeshi Yoshida , Yoshihisa Kondo , Masato Nagamatsu , Junji Mori , Itaru Yamazaki
发明人： Nobuhiro Ide , Takeshi Yoshida , Yoshihisa Kondo , Masato Nagamatsu , Junji Mori , Itaru Yamazaki
IPC分类号： G06F7/57 , G06F9/38 , G06F7/38
CPC分类号： G06F7/483 , G06F9/30014 , G06F9/3826 , G06F2207/3868
摘要： Disclosed is a pipeline information processing circuit which comprises a register control unit for outputting a plurality of data held in registers at a time; an arithmetic operation unit for carrying out a collective arithmetic operation of a plurality of data; and a bypass control unit for comparing an operation result outputted from the arithmetic operation unit and a data outputted from the register control unit, selecting a data to be an object of the next arithmetic operation, and transferring the selected data to the arithmetic operation unit through a suitable bypass.
摘要翻译：公开了一种流水线信息处理电路，其包括：一次输出保存在寄存器中的多个数据的寄存器控制单元; 用于执行多个数据的集合算术运算的算术运算单元; 以及旁路控制单元，用于将从算术运算单元输出的运算结果与从寄存器控制单元输出的数据进行比较，选择下一个算术运算对象的数据，并将选择的数据传送到算术运算单元一个合适的旁路。

2. 发明授权

US5206826A Floating-point division cell 失效
标题翻译：浮点分割单元格
公开(公告)号：US5206826A
公开(公告)日：1993-04-27
申请号：US787926
申请日：1991-11-06
申请人： Junji Mori , Masato Nagamatsu , Itaru Yamazaki , Yoshihisa Kondo , Nobuhiro Ide , Takeshi Yoshida
发明人： Junji Mori , Masato Nagamatsu , Itaru Yamazaki , Yoshihisa Kondo , Nobuhiro Ide , Takeshi Yoshida
IPC分类号： G06F7/537 , G06F7/483 , G06F7/506 , G06F7/52 , G06F7/535
CPC分类号： G06F7/535 , G06F2207/382 , G06F2207/5352 , G06F7/4873
摘要： A floating-point division cell consisting of partial remainder data register for storing parallel-partial-remainder data or third partial remainder data, divisor data register for storing parallel-divisor data or third divisor data, low-order divisor data generator for receiving the low-order portion of the divisor data and generating low-order divisor data, low-order partial remainder calculator for obtaining low-order multi-divisor data by multiplying the low-order divisor data and a multiple of 2 together and calculating new low-order partial remainder data by subtracting or adding the low-order multi-divisor data from/to the low-order portion of the partial remainder data, high-order divisor data generator for receiving the high-order portion of the divisor data and generating high-order divisor data, and high-order partial remainder calculator for obtaining high-order multi-divisor data by multiplying the high-order divisor data and a multiple of 2 together and calculating new high-order partial remainder data by subtracting or adding the high-order multi-divisor data from/to the high-order portion of the partial remainder data.
摘要翻译：由部分余数数据寄存器组成的浮点分割单元，用于存储并行余数数据或第三部分余数数据，用于存储并行除数数据或第三除数数据的除数数据寄存器，用于接收低电平的低位除数数据发生器除数数据的低阶部分和低阶除数数据，低阶部分余数计算器，用于通过将低阶除数数据和2的倍数相乘并计算新的低阶数来获得低阶多因子数据通过从部分余数数据的低位部分中减去或添加低阶多因子数据的部分余数数据，高阶除数数据发生器，用于接收除数数据的高阶部分，高阶除数数据和高阶部分余数计算器，用于通过将高阶除数数据和2的倍数相乘在一起来获得高阶多因子数据，并计算新的高除数数据通过从/部分余数数据的高阶部分中减去或添加高阶多因数数据，来获得h阶部分余数数据。

3. 发明授权

US5621910A System for controlling instruction distribution for use in superscalar parallel processor 失效
标题翻译：用于控制超标量并行处理器使用的指令分配系统
公开(公告)号：US5621910A
公开(公告)日：1997-04-15
申请号：US376645
申请日：1995-01-20
申请人： Masato Nagamatsu
发明人： Masato Nagamatsu
IPC分类号： G06F7/00 , G06F9/30 , G06F9/38 , G06F15/16 , G06F15/80 , G06F9/46
CPC分类号： G06F9/3836
摘要： In an instruction distribution control device for parallel execution of instructions for use in a superscalar parallel processor, the control device comprises an instruction distribution starting position pointer register, an instruction distribution enable/disable signal generating circuit, and an updating circuit. The distribution starting position pointer register indicates from which instruction of N (>1) instructions the distribution is to be started. The instruction distribution enable/disable signal generating circuit generates signals for determining whether the instructions may or may not be distributed to instruction executing arithmetic units on the basis of the contents of the instruction distribution starting position pointer register and signals indicating the results of dependence analysis for examining resource conflict. The updating circuit generates information indicating to which instruction of the N instructions the execution has advanced on the basis of the instruction distribution enable/disable signals and signals indicating the results of dependence analysis for examining data conflict and updates the instruction distribution starting position indicated by the instruction distribution starting position pointer register.
摘要翻译：在用于并行执行在超标量并行处理器中使用的指令的指令分配控制装置中，控制装置包括指令分配开始位置指针寄存器，指令分配使能/禁止信号生成电路和更新电路。分配起始位置指针寄存器指示从哪个指令（> 1）指令开始分配。指令分配启用/禁止信号发生电路根据指令分配开始位置指针寄存器的内容生成用于确定指令是否可能分配到指令执行算术单元的信号，以及指示依赖性分析结果的信号审查资源冲突。更新电路基于指示分配使能/禁止信号和指示用于检查数据冲突的依赖关系分析的结果的信号，生成指示执行已经前进的N个指令的哪个指令，并更新指示分配开始位置指令分配起始位置指针寄存器。

4. 发明授权

US5226003A Multi-path multiplier 失效
标题翻译：多径乘法器
公开(公告)号：US5226003A
公开(公告)日：1993-07-06
申请号：US724820
申请日：1991-07-02
申请人： Masato Nagamatsu
发明人： Masato Nagamatsu
IPC分类号： G06F7/533 , G06F7/506 , G06F7/52 , G06F7/523 , G06F7/527
CPC分类号： G06F7/5336
摘要： A low-cost high-speed multiplier comprises a first register for holding a multiplier; a second register for holding a multiplicand; a partial product generator for scanning the multiplier held in the first register to generate three partial products of the multiplicand held in the second register; a 4-input adder for finding the sum of the three partial products and a fourth number; a shift register for holding and shifting the sum; and a unit for returning the shifted sum except a shifted-out portion of the sum to an input of the 4-input adder. This arrangement can process three partial products in one time of addition.
摘要翻译：低成本高速乘法器包括用于保持乘法器的第一寄存器; 持有被乘数的第二个登记册; 用于扫描保持在第一寄存器中的乘法器的部分乘积发生器，以产生保持在第二寄存器中的被乘数的三个部分乘积; 一个用于找到三个部分乘积和第四个数字的和的4输入加法器; 用于持有和转移总和的移位寄存器; 以及用于将除了移除的和除去的部分之外的移位的和返回到4输入加法器的输入的单元。这种安排可以在一次添加中处理三种部分产品。

5. 发明授权

US4733365A Logic arithmetic circuit 失效
标题翻译：逻辑运算电路
公开(公告)号：US4733365A
公开(公告)日：1988-03-22
申请号：US933859
申请日：1986-11-24
申请人： Masato Nagamatsu
发明人： Masato Nagamatsu
IPC分类号： G06F7/501 , G06F7/50 , G06F7/503 , G06F7/508 , H03K19/096 , H03K19/21
CPC分类号： G06F7/503 , H03K19/215
摘要： A logic arithmetic circuit comprising first through sixth transistors, the first through third being P-channel transistors and the fourth through sixth being N-channel transistors. The gates of the first and sixth transistors are supplied by a synchronizing signal; the gates of the second and fifth are supplied by a first operand signal; and the gates of the third and fourth are supplied by a second operand signal. Respective current paths are provided between the first and the sixth transistors through the second and fourth transistors and through the third and fifth transistors with the output signal taken at the connecting point of the fourth and fifth transistors with the sixth transistor.
摘要翻译：包括第一至第六晶体管的逻辑运算电路，第一至第三晶体管为P沟道晶体管，第四至第六晶体管为N沟道晶体管。第一和第六晶体管的栅极由同步信号提供; 第二和第五的栅极由第一操作数信号提供; 并且第三和第四的栅极由第二操作数信号提供。在第一和第六晶体管之间通过第二和第四晶体管以及通过第三和第五晶体管提供各自的电流路径，其中输出信号在第四和第五晶体管与第六晶体管的连接点处获取。

6. 发明授权

US6064246A Logic circuit employing flip-flop circuit 失效
标题翻译：采用触发电路的逻辑电路
公开(公告)号：US6064246A
公开(公告)日：2000-05-16
申请号：US949558
申请日：1997-10-14
申请人： Yukio Endo , Masato Nagamatsu
发明人： Yukio Endo , Masato Nagamatsu
IPC分类号： G11C19/00 , G11C19/28 , H03K3/289
CPC分类号： G11C19/00 , G11C19/28
摘要： A flip-flop circuit consists of a conventional pulse-drive flip-flop plus a clock driver and a local pulse generator that generates a pulse signal according to the output of the clock driver. The flip-flop circuits of this kind are used to form, for example, a shift register in which the clock drivers are connected in series from the last stage toward the first stage. The clock driver in the last stage receives a clock signal, which is successively supplied to the flip-flop circuits from the one in the last stage toward the one in the first stage. This arrangement prevents a data-pass-through problem, assures a sharp waveform of pulse signals, and reduces the size of each clock driver. This type of flip-flop circuits may be used to form logic circuits such as N-bit registers and N-bit shift registers.
摘要翻译：触发器电路由传统的脉冲驱动触发器加上时钟驱动器和本地脉冲发生器组成，该脉冲发生器根据时钟驱动器的输出产生脉冲信号。这种触发器电路用于形成例如其中时钟驱动器从最后阶段到第一阶段串联连接的移位寄存器。最后一级的时钟驱动器接收时钟信号，该时钟信号从最后阶段的触发器电路连续地提供给第一级的时钟信号。这种安排可防止数据通过问题，确保脉冲信号的尖锐波形，并减小每个时钟驱动器的大小。这种类型的触发器电路可以用于形成诸如N位寄存器和N位移位寄存器的逻辑电路。

7. 发明授权

US5171701A Method of manufacturing master-slice semiconductor integrated circuits 失效
标题翻译：制造主切片半导体集成电路的方法
公开(公告)号：US5171701A
公开(公告)日：1992-12-15
申请号：US729128
申请日：1991-07-12
申请人： Masato Nagamatsu
发明人： Masato Nagamatsu
IPC分类号： H01L21/82 , H01L23/525 , H01L23/528 , H01L27/118
CPC分类号： H01L23/528 , H01L23/525 , H01L27/11803 , H01L2924/0002 , Y10S257/909
摘要： A method for forming in a short time master-slice integrated circuits of high reliability, which circuits comprise diffusion layers and polysilicon layers which form transistor elements, and a plurality of metal wiring layers formed for realizing desired circuits, with insulating layers interposed between every adjacent two of the wiring layers. The methods comprises a first wiring process in which a master slice is provided by forming a predetermined number of metal layers in a wafer, and a second wiring process in which further metal wiring layers, to be customized so as to have logical functions required by a user, are formed on the first-mentioned metal wiring layers. The inner-most metal wiring layer of all the metal layers is used as wide power source line which is almost free from electro or stress migration.
摘要翻译：一种用于形成高可靠性的短时间主片集成电路的方法，该电路包括形成晶体管元件的扩散层和多晶硅层，以及形成用于实现期望电路的多个金属布线层，绝缘层插入在每个相邻的两个接线层。该方法包括第一布线工艺，其中通过在晶片中形成预定数量的金属层来提供母片，以及第二布线工艺，其中另外的金属布线层被定制成具有由使用者形成在第一金属布线层上。所有金属层的最内层的金属布线层用作几乎没有电或应力迁移的宽电源线。

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