专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5214759A Multiprocessors including means for communicating with each other through shared memory 失效
标题翻译：包括与每个其他通过共享存储器进行通信的手段的多个处理器
公开(公告)号：US5214759A
公开(公告)日：1993-05-25
申请号：US526718
申请日：1990-05-22
申请人： Akira Yamaoka , Kenichi Wada
发明人： Akira Yamaoka , Kenichi Wada
IPC分类号： G06F15/16 , G06F15/167 , G06F15/177
CPC分类号： G06F15/167
摘要： In a memory device shared among processors, a communication buffer having a size requested by the processing program of the origin of sending is dynamically secured. After the communication buffer has been secured, the send program writes a message to be conveyed to the receive program into the above described communication buffer and asks the send OS to perform sending. The send OS sends a communication ID having "1" set in the bit position corresponding to the receive program. On the basis of the above described bit position, the receive OS specifies a receive program and informs the receive program of that fact. The receive program reads a message from the communication buffer. Communication between the send program and the receive program is thus realized. A send instruction and a receive instruction respectively for exclusive use of sending and reading out a communication ID are prepared beforehand.
摘要翻译：在处理器之间共享的存储器装置中，动态地确保具有处理程序所请求的发送原点的通信缓冲器。在通信缓冲器已被保护之后，发送程序将要传送到接收程序的消息写入上述通信缓冲器，并请求发送OS执行发送。发送OS在与接收程序相对应的比特位置中发送具有“1”的通信ID。基于上述位位置，接收OS指定接收程序并通知接收程序该事实。接收程序从通信缓冲区读取消息。因此实现了发送程序和接收程序之间的通信。预先准备分别发送和读出通信ID的发送指令和接收指令。

2. 发明授权

US4758949A Information processing apparatus 失效
标题翻译：信息处理装置
公开(公告)号：US4758949A
公开(公告)日：1988-07-19
申请号：US928055
申请日：1986-11-07
申请人： Kenichi Wada , Kazunori Kuriyama , Akira Yamaoka
发明人： Kenichi Wada , Kazunori Kuriyama , Akira Yamaoka
IPC分类号： G06F9/38
CPC分类号： G06F9/3873 , G06F9/3802 , G06F9/3836
摘要： An information processing apparatus having a buffer register for pre-fetching a plurality of instructions and executing one instruction after another by reading them from the buffer registers, is provided with a first instruction decode start determination unit for register type instructions and a second instruction decode start determination unit for non-register type instructions, provided separately from the first unit, whereby 0.5 cycle after a register type instruction starts being decoded, or 1 cycle after a non-register type instruction starts being decoded, the next instruction starts to be decoded. By decoding a register type instruction at high speed, it becomes possible to execute a branch instruction at high speed.
摘要翻译：具有用于预取多个指令并且通过从缓冲寄存器读取它们来执行一个指令的缓冲寄存器的信息处理装置设置有用于寄存器类型指令的第一指令解码开始确定单元和第二指令解码开始与第一单元分开设置的非寄存器类型指令的确定单元，其中在寄存器类型指令开始被解码之后的0.5个周期，或者在非寄存器类型指令开始被解码之后的1个周期，下一个指令开始被解码。通过高速解码寄存器类型指令，可以高速执行分支指令。

3. 发明授权

US5201040A Multiprocessor system having subsystems which are loosely coupled through a random access storage and which each include a tightly coupled multiprocessor 失效
标题翻译：具有通过随机存取存储松散耦合的子系统的多处理器系统，每个子系统包括紧密耦合的多处理器
公开(公告)号：US5201040A
公开(公告)日：1993-04-06
申请号：US209073
申请日：1988-06-20
申请人： Kenichi Wada , Akira Yamaoka
发明人： Kenichi Wada , Akira Yamaoka
IPC分类号： G06F15/17
CPC分类号： G06F15/17
摘要： A data processing system which has a plurality of sets of sub-systems, with each set including: a plurality of processors; a main storage; and a controller for controlling the transfer between at least each of the processors and the main storage. A shared storage apparatus is shared between the sub-systems to store exclusive control information, information on the processor-to-processor communications and an instruction to be transferred between the main storages and the shared storage apparatus when the information is accessed by each sub-system. The instruction designates a main storage address, a transfer data length and specified information on accessing the location of the shared storage apparatus and is decoded by the processors to that the main storage address is transferred to the main storage, whereas the specified information such as a data identifier and a relative address is transferred to the shared storage apparatus.
摘要翻译：一种具有多组子系统的数据处理系统，每组包括：多个处理器; 主要存储; 以及用于控制至少每个处理器和主存储器之间的传送的控制器。在每个子系统访问信息时，在子系统之间共享共享存储装置以存储专用控制信息，关于处理器到处理器通信的信息和要在主存储器和共享存储装置之间传送的指令，系统。该指令指定主存储地址，传输数据长度和关于访问共享存储设备的位置的指定信息，并且被处理器解码为主存储地址被传送到主存储器，而指定的信息例如数据标识符和相对地址被传送到共享存储装置。

4. 发明授权

US4954947A Instruction processor for processing branch instruction at high speed 失效
标题翻译：高速处理分支指令的指令处理器
公开(公告)号：US4954947A
公开(公告)日：1990-09-04
申请号：US336741
申请日：1989-03-21
申请人： Kazunori Kuriyama , Kenichi Wada , Akira Yamaoka
发明人： Kazunori Kuriyama , Kenichi Wada , Akira Yamaoka
IPC分类号： G06F9/38
CPC分类号： G06F9/3824
摘要： An instruction processor effecting operations for register operands and for processing branch instructions to perform address calculations for branch destination instructions, comprising general-purpose registers storing data including results of operations of said instruction processor, address adders calculating the address of branch destination instructions by using data read out from the general-purpose register and an ALU performing arithmetical or logical operations on the data read out from the general-purpose register in the decode cycle of the instructions. The result of the arithmetical or logical operation is inputted into the address adder but not from the general-purpose register, in the case where the result of the arithmetical or logical operation is utilized for address calculation in the execution of a succeeding instruction.
摘要翻译：指令处理器对寄存器操作数进行操作并处理分支指令以执行分支目的地指令的地址计算，包括通用寄存器，其存储包括所述指令处理器的操作结果的数据，地址加法器通过使用数据计算分支目的地指令的地址从通用寄存器读出，以及ALU对指令的解码周期中从通用寄存器读出的数据执行算术或逻辑运算。在执行后续指令时，算术运算或逻辑运算的结果被用于地址计算的情况下，将算术或逻辑运算的结果输入到地址加法器而不是通用寄存器。

5. 发明授权

US4924377A Pipelined instruction processor capable of reading dependent operands in parallel 失效
标题翻译：能够并行读取相关操作数的流水线指令处理器
公开(公告)号：US4924377A
公开(公告)日：1990-05-08
申请号：US687161
申请日：1984-12-28
申请人： Kazunori Kuriyama , Kenichi Wada , Akira Yamaoka
发明人： Kazunori Kuriyama , Kenichi Wada , Akira Yamaoka
IPC分类号： G06F9/34 , G06F9/345 , G06F9/355 , G06F9/38
CPC分类号： G06F9/355 , G06F9/345 , G06F9/383
摘要： Address calculation adders and a buffer storages are each independently provided for each operand of an instruction requiring two or more operands. In the translation instruction processing, the address calculations and operand fetch operations on the first and second operands are substantially asynchronously conducted. Consequently, the overhead that takes place one every n second operand fetch operations can be removed by independently and asynchronously performing the address calculations and operand fetch operations by use of a plurality of address adders. Moreover, the circuit for separating and obtaining a byte from the operand buffer can be dispensed with by adopting an operation procedure in which a byte of the first operand is fetched and is stored in temporary store means that supplies the address adder the data stored therein.
摘要翻译：对于需要两个或多个操作数的指令的每个操作数，地址计算加法器和缓冲存储器都是独立提供的。在转换指令处理中，对第一和第二操作数的地址计算和操作数获取操作基本上异步进行。因此，可以通过使用多个地址加法器独立地和异步地执行地址计算和操作数获取操作来移除每n个第二操作数获取操作发生一次的开销。此外，可以通过采用其中获取第一操作数的字节的操作过程来存储用于从操作数缓冲器分离和获得字节的电路，并将其存储在向地址加法器提供其中存储的数据的临时存储装置中。

6. 发明授权

US4739470A Data processing system 失效
标题翻译：数据处理系统
公开(公告)号：US4739470A
公开(公告)日：1988-04-19
申请号：US489349
申请日：1983-04-28
申请人： Kenichi Wada , Yooichi Shintani , Tsuguo Shimizu , Akira Yamaoka
发明人： Kenichi Wada , Yooichi Shintani , Tsuguo Shimizu , Akira Yamaoka
IPC分类号： G06F9/38
CPC分类号： G06F9/3889 , G06F9/383
摘要： A data processing system for executing an instruction in a plurality of stages in a pipeline mode comprises a main operation unit capable of executing all instructions to be executed in the data processing system, a pre-operation unit capable of executing instructions which occurs at a high frequency and can be executed with a small number of circuit components, general purpose registers for storing operation results of the instructions, and a control unit for controlling the writing of the operation results by the main operation unit and the pre-operation unit into the general purpose registers.
摘要翻译：一种用于在流水线模式中执行多级指令的数据处理系统，包括能够执行在数据处理系统中执行的所有指令的主操作单元，能够执行高位指令的预操作单元并且可以用少量的电路部件执行，用于存储指令的操作结果的通用寄存器，以及用于控制主操作单元和预操作单元的操作结果写入一般的控制单元目的寄存器。

7. 发明授权

US4608671A Buffer storage including a swapping circuit 失效
标题翻译：缓冲存储器包括交换电路
公开(公告)号：US4608671A
公开(公告)日：1986-08-26
申请号：US490518
申请日：1983-05-02
申请人： Tsuguo Shimizu , Kenichi Wada , Yooichi Shintani , Akira Yamaoka
发明人： Tsuguo Shimizu , Kenichi Wada , Yooichi Shintani , Akira Yamaoka
IPC分类号： G06F12/08 , G06F12/12 , G11C8/00
CPC分类号： G06F12/128
摘要： In a buffer storage device where swapping of data is employed, plural candidates for replacement of data in a buffer are determined in response to any access to the buffer storage, and, when the replacement is required, one of the candidates is selected so that processing time for replacement can be minimum.
摘要翻译：在采用交换数据的缓冲存储装置中，响应于对缓冲存储器的任何访问来确定用于替换缓冲器中的数据的多个候选，并且当需要更换时，选择候选中的一个，使得处理更换时间可以是最少的。

8. 发明授权

US4532589A Digital data processor with two operation units 失效
标题翻译：具有两个操作单元的数字数据处理器
公开(公告)号：US4532589A
公开(公告)日：1985-07-30
申请号：US446002
申请日：1982-12-01
申请人： Yoichi Shintani , Kenichi Wada , Tsuguo Shimizu , Akira Yamaoka
发明人： Yoichi Shintani , Kenichi Wada , Tsuguo Shimizu , Akira Yamaoka
IPC分类号： G06F9/38 , G06F9/00
CPC分类号： G06F9/3889 , G06F9/3824 , G06F9/3836 , G06F9/3885
摘要： In a data processing apparatus executing a plurality of instructions in a pipeline mode by dividing each of the instructions into a plurality of stages, its operation circuit includes a first execution (E) unit capable of execution of operations required by all of the plural instructions and a second E unit capable of execution of operations required by part of the plural instructions only. A queue of data including decoded information of the instructions required for execution of operation stages are stored in a circuit to be selectively supplied by first and second circuits to the first and second E units, respectively. The first and second circuits sequentially select succeeding data in synchronism with the end of operations in the first and second E units respectively. As a result, when a stage of a succeeding instruction requires the result of operation of a preceding instruction being executed, that stage of the succeeding instruction is executed after the second E unit completes the operation of the preceding instruction, even when the first E unit is executing an instruction further preceding the preceding instruction.
摘要翻译：在通过将每个指令分成多个级来执行流水线模式的多个指令的数据处理装置中，其操作电路包括能够执行所有多个指令所需的操作的第一执行（E）单元，以及能够执行多个指令的一部分所需的操作的第二E单元。包括执行操作阶段所需指令的解码信息的数据队列被存储在电路中，以分别由第一和第二电路选择性地提供给第一和第二E单元。第一和第二电路分别顺序地选择与第一和第二E单元中的操作结束同步的后续数据。结果，当后续指令的阶段需要执行前一指令的操作结果时，即使在第一E单元完成了第二E单元完成前一指令的操作之后，执行后续指令的该阶段正在执行进一步在前面的指令之前的指令。

9. 发明授权

US4541047A Pipelined data processing system 失效
标题翻译：流水线数据处理系统
公开(公告)号：US4541047A
公开(公告)日：1985-09-10
申请号：US490166
申请日：1983-04-29
申请人： Kenichi Wada , Yooichi Shintani , Tsuguo Shimizu , Akira Yamaoka
发明人： Kenichi Wada , Yooichi Shintani , Tsuguo Shimizu , Akira Yamaoka
IPC分类号： G06F9/38 , G06F9/48
CPC分类号： G06F9/3863
摘要： A data processing system for executing an instruction in a plurality of stages in a pipeline mode comprises a main operation unit for operating all instructions to be executed by the data processing unit, a first group of general purpose registers for storing the operation results of the main operation unit, a pre-operation unit for operating a portion of instructions which frequently appear and which can be operated with a small number of circuit components, a second group of general purpose registers for storing the operation results of the pre-operation unit, and control means for storing the operation result of the pre-operation unit into the second general purpose register at least one operation stage earlier than the storing of the operation result of the main operation unit into the first general purpose register and storing the contents of the second general purpose registers into the first general purpose registers when an interruption occurs.
摘要翻译：一种用于在流水线模式中执行多级的指令的数据处理系统包括用于操作由数据处理单元执行的所有指令的主操作单元，用于存储主程序的操作结果的第一组通用寄存器操作单元，用于操作经常出现并且可以用少量电路组件操作的指令的一部分的预操作单元，用于存储预操作单元的操作结果的第二组通用寄存器，以及控制装置，用于将预操作单元的操作结果存储在第二通用寄存器中，比将主操作单元的操作结果存储到第一通用寄存器中的至少一个操作阶段存储第二通用寄存器的内容当发生中断时，通用寄存器进入第一个通用寄存器。

10. 发明授权

US4916606A Pipelined parallel data processing apparatus for directly transferring operand data between preceding and succeeding instructions 失效
标题翻译：用于在先前和后续指令之间直接传送操作数数据的流水线并行数据处理装置
公开(公告)号：US4916606A
公开(公告)日：1990-04-10
申请号：US75528
申请日：1987-07-20
申请人： Akira Yamaoka , Kenichi Wada , Kazunori Kuriyama , Yooichi Shintani
发明人： Akira Yamaoka , Kenichi Wada , Kazunori Kuriyama , Yooichi Shintani
IPC分类号： G06F9/38
CPC分类号： G06F9/3889 , G06F9/3824
摘要： A data processing apparatus of processing first instruction of a type in which the result of operation of the first instruction is stored in at least one storage location designated by operands of the first instruction and second instruction of a type which succeeds to the first instruction and makes use of the result of operation of the first instruction as operand data. The apparatus comprises an OSC control circuit for detecting whether at least a part of the result of operation of the first instruction is to be used or not as the operand data for the second instruction, and an arithmetic unit for allowing the result of operation of the first instruction to be directly used as the operand data for the second instruction when the OSC control circuit detects the given condition is fulfilled.
摘要翻译：一种处理第一指令的第一指令的数据处理装置，其中第一指令的操作结果被存储在由第一指令的操作数指定的至少一个存储位置中，并且第二指令成为第一指令成功的类型使用第一条指令的操作结果作为操作数据。该装置包括用于检测是否要使用第一指令的操作结果的至少一部分作为第二指令的操作数数据的OSC控制电路，以及用于允许第二指令的操作结果的运算单元当OSC控制电路检测到给定条件时，直接用作第二指令的操作数数据的第一指令被满足。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式