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1. 发明授权

US5627490A Amplifier circuit 失效
标题翻译：放大器电路
公开(公告)号：US5627490A
公开(公告)日：1997-05-06
申请号：US597258
申请日：1996-02-06
申请人： Koji Sushihara , Takashi Yamamoto , Ikuo Imanishi , Tsuyoshi Nakamura , Michinori Kishimoto , Kenichi Ishida
发明人： Koji Sushihara , Takashi Yamamoto , Ikuo Imanishi , Tsuyoshi Nakamura , Michinori Kishimoto , Kenichi Ishida
IPC分类号： G05F3/26 , H03F1/48 , H03F3/42 , H03K3/45
CPC分类号： H03F3/42 , G05F3/265 , H03F1/48
摘要： An amplifier circuit for amplifying a change in a resistance value of a magnetic resistance element is formed by connecting a first and a second current mirror circuits having the same structure in cascode, so that a voltage change is amplified without using a capacitive coupling. Hence, a high-pass filter is not created as a parasitic circuit, whereby a gain is maintained high in the low frequency region and a low frequency characteristic is excellent. Further, since control electrodes of transistors which form each current mirror circuit are grounded through the capacitance, a noise is reduced without using a conventional feedback circuit. This eliminates an influence of the feedback circuit over a high frequency characteristic, and therefore, a high frequency characteristic becomes excellent.
摘要翻译：通过将具有相同结构的第一和第二电流镜电路串联连接形成用于放大电阻元件的电阻值变化的放大器电路，从而在不使用电容耦合的情况下放大电压变化。因此，不产生高通滤波器作为寄生电路，从而在低频区域中增益保持较高，并且低频特性优异。此外，由于形成每个电流镜电路的晶体管的控制电极通过电容接地，所以在不使用常规反馈电路的情况下，噪声降低。这消除了反馈电路对高频特性的影响，因此高频特性变得优异。

2. 发明授权

US5751191A Reproducing signal amplifier and central value signal generator 失效
标题翻译：再现信号放大器和中心值信号发生器
公开(公告)号：US5751191A
公开(公告)日：1998-05-12
申请号：US708064
申请日：1996-08-12
申请人： Kenichi Ishida , Michinori Kishimoto , Takashi Yamamoto , Koji Sushihara
发明人： Kenichi Ishida , Michinori Kishimoto , Takashi Yamamoto , Koji Sushihara
IPC分类号： G11B5/02 , H03F3/30 , H03F3/45 , H03F3/68
CPC分类号： H03F3/3066 , G11B5/02 , H03F3/45479
摘要： A magnetic recording device includes a magnetic disk drive for recording desired information as a magnetic signal and a reproducing signal amplifier for amplifying a small electric signal obtained by converting the magnetic signal. The reproducing signal amplifier includes an amplifier for amplifying a small electric signal supplied through an input terminal into an amplified signal having an appropriate amplitude, a central value detection circuit for detecting a central value of the AC component of the amplified signal output by the amplifier and outputting a central value signal consisting of the DC component of the amplified signal, and a subtracter for obtaining a difference between the amplified signal and the central value signal and outputting a reproducing signal.
摘要翻译：磁记录装置包括用于记录作为磁信号的期望信息的磁盘驱动器和用于放大通过转换磁信号而获得的小电信号的再现信号放大器。再现信号放大器包括放大器，用于将通过输入端提供的小电信号放大为具有适当振幅的放大信号;中央值检测电路，用于检测由放大器输出的放大信号的AC分量的中心值;以及输出由放大信号的DC分量组成的中心值信号，以及减法器，用于获得放大信号和中心值信号之间的差，并输出再现信号。

3. 发明授权

US06252440B1 Write-driver circuit 有权
标题翻译：写驱动电路
公开(公告)号：US06252440B1
公开(公告)日：2001-06-26
申请号：US09445392
申请日：2000-03-07
申请人： Koji Sushihara , Takashi Yamamoto , Kenichi Ishida
发明人： Koji Sushihara , Takashi Yamamoto , Kenichi Ishida
IPC分类号： H03K300
CPC分类号： G11B5/022 , G11B5/012 , G11B5/02 , G11B5/09 , G11B5/40
摘要： In a write driver circuit for switching the direction of a write current passing through a magnetic head or the like having an inductance component, an H-shaped bridge circuit is formed by using four NPN transistors in order to switch the write current at a high speed. Four switching means for controlling the base potentials of the four NPN transistors are provided and two switching means for rapidly decreasing the base potential of one of the two NPN transistors on the power source side, which is turned off when the write current passing through the magnetic head is switched are provided, thereby widening a voltage difference occurring between both terminals of the magnetic head.
摘要翻译：在用于切换通过具有电感分量的磁头等的写入电流的写入驱动电路中，通过使用四个NPN晶体管形成H形桥接电路，以便以高速切换写入电流。提供用于控制四个NPN晶体管的基极电位的四个开关装置，以及用于快速降低电源侧的两个NPN晶体管中的一个的基极电位的两个开关装置，当写入电流通过磁提供头部切换，从而扩大在磁头的两个端子之间出现的电压差。

4. 发明授权

US07834794B2 A/D converter 失效
标题翻译： A / D转换器
公开(公告)号：US07834794B2
公开(公告)日：2010-11-16
申请号：US12439444
申请日：2007-08-10
申请人： Masakazu Shigemori , Koji Sushihara , Kenji Murata
发明人： Masakazu Shigemori , Koji Sushihara , Kenji Murata
IPC分类号： H03M1/12
CPC分类号： H03M1/0624 , H03M1/206 , H03M1/365
摘要： The conventional A/D converter has a drawback that the conversion precision is degraded when the operation periods of the constituents of the A/D converter are shortened due to the duty ratio of an external input clock because the operation periods of the constituents of the A/D converter depend on the pulse width of the external input clock. However, a highly-precise A/D conversion operation independent of the duty ratio of the external input clock can be realized by providing a circuit for detecting the operation periods of the constituents of the A/D converter, and adjusting the duty ratio of the operation clock according to the detected operation periods of the constituents of the A/D converter.
摘要翻译：传统的A / D转换器具有这样的缺点，即当A / D转换器的构成要素的操作周期由于外部输入时钟的占空比而缩短时，转换精度降低，因为A / D转换器取决于外部输入时钟的脉冲宽度。然而，与外部输入时钟的占空比无关的高精度A / D转换操作可以通过提供用于检测A / D转换器的构成要素的操作周期的电路来实现，并且调整占空比根据检测到的A / D转换器的构成要素的运行时间来设定运转时钟。

5. 发明申请

US20090179787A1 COMPARATOR AND A/D CONVERTER 有权
标题翻译：比较器和A / D转换器
公开(公告)号：US20090179787A1
公开(公告)日：2009-07-16
申请号：US12093565
申请日：2006-04-18
申请人： Junichi Naka , Koji Sushihara
发明人： Junichi Naka , Koji Sushihara
IPC分类号： H03M1/12 , H03K5/22
CPC分类号： H03M1/0607 , H03K5/2481 , H03M1/204 , H03M1/362
摘要： A comparator used in a parallel-type A/D converter, wherein a comparator 100 includes reset transistors mra and mrb. When the comparator 100 is in the Reset state, the inverted signal /CLK of the clock signal is given to the PMOS reset transistors mra and mrb so as to forcibly reset both of the voltages at two internal nodes Va and Vb being a differential pair to a predetermined reset voltage by the reset transistors mra and mrb. The inverted signal /CLK of the clock signal is produced with a predetermined delay. Thus, when the comparator 100 is in the Reset state, the point in time at which to cancel the reset of the internal nodes Va and Vb is delayed from that at which the comparator performs a comparison operation. Therefore, even if the frequency of the clock signal and the frequency of the analog input signal are high, the voltages at the internal nodes forming a differential pair are well-balanced when the comparator is in the Reset state, thus improving the voltage comparison precision.
摘要翻译：一种用于并行型A / D转换器的比较器，其中比较器100包括复位晶体管mra和mrb。当比较器100处于复位状态时，将时钟信号的反相信号/ CLK提供给PMOS复位晶体管mra和mrb，以便将两个作为差分对的内部节点Va和Vb的两个电压强制复位到复位晶体管mra和mrb的预定复位电压。以预定的延迟产生时钟信号的反相信号/ CLK。因此，当比较器100处于复位状态时，消除内部节点Va和Vb的复位的时间点比比较器执行比较操作的时间延迟。因此，即使时钟信号的频率和模拟输入信号的频率高，形成差分对的内部节点的电压在比较器处于复位状态时也是平衡的，从而提高电压比较精度。

6. 发明授权

US07061419B2 A/D converter and A/D converting system 失效
公开(公告)号：US07061419B2
公开(公告)日：2006-06-13
申请号：US11010423
申请日：2004-12-14
申请人： Koji Sushihara , Takashi Morie
发明人： Koji Sushihara , Takashi Morie
IPC分类号： H03M1/12
CPC分类号： H03M1/0604 , H03M1/0682 , H03M1/365
摘要： In a flash A/D converter including a plurality of differential amplifier circuits and a plurality of voltage comparator circuits, a regulator circuit is provided. The regulator circuit automatically regulates a bias voltage of each of the plurality of differential amplifier circuits in a differential amplifier circuit array to make an output dynamic range for the differential amplifier circuits match an input dynamic range for the plurality of voltage comparator circuits. Therefore, even if the input dynamic range for the voltage comparator circuits is narrowed with reduction in a power supply voltage, the output dynamic range for the differential amplifier circuits and the input dynamic range for the voltage comparator circuits match, thus resulting in a high A/D conversion accuracy.

7. 发明授权

US07898449B2 Differential operational amplifier circuit correcting settling error for use in pipelined A/D converter 有权
标题翻译：差分运算放大器电路校正用于流水线A / D转换器的建立误差
公开(公告)号：US07898449B2
公开(公告)日：2011-03-01
申请号：US12562664
申请日：2009-09-18
申请人： Shoji Kawahito , Kazutaka Honda , Yasuhide Shimizu , Kuniyuki Tani , Akira Kurauchi , Koji Sushihara , Koichiro Mashiko
发明人： Shoji Kawahito , Kazutaka Honda , Yasuhide Shimizu , Kuniyuki Tani , Akira Kurauchi , Koji Sushihara , Koichiro Mashiko
IPC分类号： H03M1/12
CPC分类号： H03F3/45237 , H03F2203/45094 , H03F2203/45356 , H03F2203/45481 , H03F2203/45551
摘要： A telescopic differential operational amplifier circuit for use in a pipelined A/D converter is provided with two auxiliary differential amplifiers connected to two cascode circuits, each including cascode-connected first to fourth transistors. During the sampling phase, first and second switches are turned on to apply a predetermined bias voltage to the gates of first and fourth transistors, and the input terminal of the differential operational amplifier circuit is set to a common mode voltage. During the hold phase, the first and second switches are turned off so that a voltage of each of the gates of the first and fourth transistors change to follow an input signal inputted via the input terminal with coupling capacitors operating as a level shifter of the input signal. Then the differential operational amplifier circuit performs push-pull operation operative only in a transconductance drive region, and is prevented from operating in a slewing region.
摘要翻译：在流水线A / D转换器中使用的伸缩差分运算放大器电路设置有两个连接到两个共源共栅电路的辅助差分放大器，每个包括共源共栅连接的第一至第四晶体管。在采样阶段期间，第一和第二开关导通以对第一和第四晶体管的栅极施加预定的偏置电压，并且差分运算放大器电路的输入端被设置为共模电压。在保持阶段期间，第一和第二开关断开，使得第一和第四晶体管的每个栅极的电压改变为跟随经由输入端输入的输入信号，耦合电容器作为输入的电平转换器信号。然后，差分运算放大器电路仅在跨导驱动区域中执行推挽操作，并且防止在回转区域中操作。

8. 发明授权

US07821303B2 Comparator and A/D converter 有权
标题翻译：比较器和A / D转换器
公开(公告)号：US07821303B2
公开(公告)日：2010-10-26
申请号：US12093565
申请日：2006-04-18
申请人： Junichi Naka , Koji Sushihara
发明人： Junichi Naka , Koji Sushihara
IPC分类号： G01R19/00
CPC分类号： H03M1/0607 , H03K5/2481 , H03M1/204 , H03M1/362
摘要： A comparator used in a parallel-type A/D converter, wherein a comparator 100 includes reset transistors mra and mrb. When the comparator 100 is in the Reset state, the inverted signal /CLK of the clock signal is given to the PMOS reset transistors mra and mrb so as to forcibly reset both of the voltages at two internal nodes Va and Vb being a differential pair to a predetermined reset voltage by the reset transistors mra and mrb. The inverted signal /CLK of the clock signal is produced with a predetermined delay. Thus, when the comparator 100 is in the Reset state, the point in time at which to cancel the reset of the internal nodes Va and Vb is delayed from that at which the comparator performs a comparison operation. Therefore, even if the frequency of the clock signal and the frequency of the analog input signal are high, the voltages at the internal nodes forming a differential pair are well-balanced when the comparator is in the Reset state, thus improving the voltage comparison precision.
摘要翻译：一种用于并行型A / D转换器的比较器，其中比较器100包括复位晶体管mra和mrb。当比较器100处于复位状态时，将时钟信号的反相信号/ CLK提供给PMOS复位晶体管mra和mrb，以便将两个作为差分对的内部节点Va和Vb的两个电压强制复位到复位晶体管mra和mrb的预定复位电压。以预定的延迟产生时钟信号的反相信号/ CLK。因此，当比较器100处于复位状态时，消除内部节点Va和Vb的复位的时间点比比较器执行比较操作的时间延迟。因此，即使时钟信号的频率和模拟输入信号的频率高，形成差分对的内部节点的电压在比较器处于复位状态时也是平衡的，从而提高电压比较精度。

9. 发明申请

US20090146854A1 PIPELINE TYPE A/D CONVERTER APPARATUS PROVIDED WITH PRECHARGE CIRCUIT FOR PRECHARGING SAMPLING CAPACITOR 失效
标题翻译：用于预先采样电容器的预置电路的管路式A / D转换器装置
公开(公告)号：US20090146854A1
公开(公告)日：2009-06-11
申请号：US12139754
申请日：2008-06-16
申请人： Shoji Kawahito , Kazutaka Honda , Yasuhide Shimizu , Kuniyuki Tani , Akira Kurauchi , Koji Sushihara
发明人： Shoji Kawahito , Kazutaka Honda , Yasuhide Shimizu , Kuniyuki Tani , Akira Kurauchi , Koji Sushihara
IPC分类号： H03M1/12
CPC分类号： H03M1/002 , H03M1/0695 , H03M1/164 , H03M1/361 , H03M1/442
摘要： In a pipeline type A/D converter apparatus including A/D converter circuit parts connected in cascade with each other and A/D converting a sample hold signal in a pipeline form, each A/D converter circuit part includes a pre-A/D converter circuit for A/D converting an input signal into a digital signal, and a multiplying D/A converter circuit for D/A converting the digital signal into an analog control signal, and D/A converting the input signal by sampling, holding and amplifying the input signal using a sampling capacitor based on the analog control signal. A precharge circuit precharges a sampling capacitor before sampling so as to attain a predetermined output value in accordance with a digital input to output characteristic substantially adapted to an input to output characteristic of each A/D converter circuit part that presents an output signal corresponding to the input signal to each A/D converter circuit part.
摘要翻译：在A / D转换电路中，A / D变换电路部分包括A / D变换电路部分，并且以流水线形式A / D转换采样保持信号，用于将输入信号转换为数字信号的A / D转换器电路，以及用于将数字信号转换为模拟控制信号进行D / A转换的乘法D / A转换器电路，以及通过采样，保持和/ 使用基于模拟控制信号的采样电容放大输入信号。预充电电路在采样之前对采样电容器进行预充电，以便根据数字输入获得预定的输出值，以输出特性基本上适合于每个A / D转换器电路部分的输入到输出特性，该输出特性呈现对应于输入信号到每个A / D转换器电路部分。

10. 发明授权

US07394417B2 A/D converter 有权
标题翻译： A / D转换器
公开(公告)号：US07394417B2
公开(公告)日：2008-07-01
申请号：US11629402
申请日：2006-04-20
申请人： Junichi Naka , Koji Sushihara
发明人： Junichi Naka , Koji Sushihara
IPC分类号： H03M1/00
CPC分类号： H03M1/0604 , H03M1/204 , H03M1/365
摘要： In an A/D converter, each preamp 102 includes a preamp gain adjusting circuit 109. The preamp gain adjusting circuit 109 suppresses the gain of the preamp 102 and restricts a positive-negative output potential difference of the preamp only when the positive-negative output potential difference of the preamp 102 exceeds a reference potential. Accordingly, in the case where the frequency of an input signal to the A/D converter is high, even when the gain of the preamp is increased due to fabrication process variation, temperature variation or supply voltage variation, output strain of the preamp is minimally caused, and the characteristic degradation of the A/D converter can be suppressed.
摘要翻译：在A / D转换器中，每个前置放大器102包括前置放大器增益调整电路109。前置放大器增益调整电路109抑制前置放大器102的增益，仅在前置放大器102的正负输出电位差超过参考电位时才限制前置放大器的正负输出电位差。因此，在A / D转换器的输入信号的频率高的情况下，即使由于制造工艺变化，温度变化或电源电压变化而增大前置放大器的增益，所以前置放大器的输出应变最小导致，并且可以抑制A / D转换器的特性劣化。

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