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1. 发明授权

US07061419B2 A/D converter and A/D converting system 失效
公开(公告)号：US07061419B2
公开(公告)日：2006-06-13
申请号：US11010423
申请日：2004-12-14
申请人： Koji Sushihara , Takashi Morie
发明人： Koji Sushihara , Takashi Morie
IPC分类号： H03M1/12
CPC分类号： H03M1/0604 , H03M1/0682 , H03M1/365
摘要： In a flash A/D converter including a plurality of differential amplifier circuits and a plurality of voltage comparator circuits, a regulator circuit is provided. The regulator circuit automatically regulates a bias voltage of each of the plurality of differential amplifier circuits in a differential amplifier circuit array to make an output dynamic range for the differential amplifier circuits match an input dynamic range for the plurality of voltage comparator circuits. Therefore, even if the input dynamic range for the voltage comparator circuits is narrowed with reduction in a power supply voltage, the output dynamic range for the differential amplifier circuits and the input dynamic range for the voltage comparator circuits match, thus resulting in a high A/D conversion accuracy.

2. 发明申请

US20060055578A1 A/D converter and A/D converting system 失效
标题翻译： A / D转换器和A / D转换系统
公开(公告)号：US20060055578A1
公开(公告)日：2006-03-16
申请号：US11010423
申请日：2004-12-14
申请人： Koji Sushihara , Takashi Morie
发明人： Koji Sushihara , Takashi Morie
IPC分类号： H03M1/12
CPC分类号： H03M1/0604 , H03M1/0682 , H03M1/365
摘要： In a flash A/D converter including a plurality of differential amplifier circuits and a plurality of voltage comparator circuits, a regulator circuit is provided. The regulator circuit automatically regulates a bias voltage of each of the plurality of differential amplifier circuits in a differential amplifier circuit array to make an output dynamic range for the differential amplifier circuits match an input dynamic range for the plurality of voltage comparator circuits. Therefore, even if the input dynamic range for the voltage comparator circuits is narrowed with reduction in a power supply voltage, the output dynamic range for the differential amplifier circuits and the input dynamic range for the voltage comparator circuits match, thus resulting in a high A/D conversion accuracy.
摘要翻译：在包括多个差分放大器电路和多个电压比较器电路的闪存A / D转换器中，提供了调节器电路。调节器电路自动调节差分放大器电路阵列中的多个差分放大器电路中的每一个的偏置电压，以使得差分放大器电路的输出动态范围与多个电压比较器电路的输入动态范围相匹配。因此，即使电压比较器电路的输入动态范围变窄，电源电压降低，差分放大电路的输出动态范围和电压比较电路的输入动态范围相匹配，导致高A / D转换精度。

3. 发明授权

US07911369B2 Pipelined AD converter 有权
标题翻译：流水线AD转换器
公开(公告)号：US07911369B2
公开(公告)日：2011-03-22
申请号：US12600784
申请日：2008-08-21
申请人： Takashi Morie , Kazuo Matsukawa , Shiro Sakiyama , Shiro Dosho , Yusuke Tokunaga
发明人： Takashi Morie , Kazuo Matsukawa , Shiro Sakiyama , Shiro Dosho , Yusuke Tokunaga
IPC分类号： H03M1/38
CPC分类号： H03M1/0678 , H03M1/0695 , H03M1/44
摘要： A pipelined AD converter (1) includes a plurality of conversion stages (11, 11, . . . ). In each of the conversion stages, an analog-to-digital conversion circuit (101) converts an input voltage (Vin) from the preceding stage to a digital code (Dout). A digital-to-analog conversion circuit (102) converts the digital code obtained by the analog-to-digital conversion circuit to an intermediate voltage (Vda). A charge operation circuit (103) has: a capacitor section (C1, C2) for sampling the input voltage; and an amplifier section (104) for amplifying a mixed voltage of the input voltage sampled by the capacitor section and the intermediate voltage obtained by the digital-to-analog conversion circuit. The amplifier section (104) includes a plurality of op-amps (amp1, amp1, . . . ) having the same configuration and connected in parallel with each other.
摘要翻译：流水线式AD转换器（1）包括多个转换级（11,11 ...）。在每个转换级中，模数转换电路（101）将来自前级的输入电压（Vin）转换为数字代码（Dout）。数模转换电路（102）将由模数转换电路获得的数字代码转换为中间电压（Vda）。充电操作电路（103）具有用于对输入电压进行采样的电容器部（C1，C2）以及用于放大由电容器部分采样的输入电压和由数模转换电路获得的中间电压的混合电压的放大器部分（104）。放大器部分（104）包括具有相同配置并且彼此并联的多个运算放大器（amp1，amp1 ...）。

4. 发明申请

US20100149010A1 PIPELINED AD CONVERTER 有权
标题翻译：管路AD转换器
公开(公告)号：US20100149010A1
公开(公告)日：2010-06-17
申请号：US12600784
申请日：2008-08-21
申请人： Takashi Morie , Kazuo Matsukawa , Shiro Sakiyama , Shiro Dosho , Yusuke Tokunaga
发明人： Takashi Morie , Kazuo Matsukawa , Shiro Sakiyama , Shiro Dosho , Yusuke Tokunaga
IPC分类号： H03M1/38 , H03M1/00
CPC分类号： H03M1/0678 , H03M1/0695 , H03M1/44
摘要： A pipelined AD converter (1) includes a plurality of conversion stages (11, 11, . . . ). In each of the conversion stages, an analog-to-digital conversion circuit (101) converts an input voltage (Vin) from the preceding stage to a digital code (Dout). A digital-to-analog conversion circuit (102) converts the digital code obtained by the analog-to-digital conversion circuit to an intermediate voltage (Vda). A charge operation circuit (103) has: a capacitor section (C1, C2) for sampling the input voltage; and an amplifier section (104) for amplifying a mixed voltage of the input voltage sampled by the capacitor section and the intermediate voltage obtained by the digital-to-analog conversion circuit. The amplifier section (104) includes a plurality of op-amps (amp1, amp1, . . . ) having the same configuration and connected in parallel with each other.
摘要翻译：流水线式AD转换器（1）包括多个转换级（11,11 ...）。在每个转换级中，模数转换电路（101）将来自前级的输入电压（Vin）转换为数字代码（Dout）。数模转换电路（102）将由模数转换电路获得的数字代码转换为中间电压（Vda）。充电操作电路（103）具有用于对输入电压进行采样的电容器部（C1，C2）以及用于放大由电容器部分采样的输入电压和由数模转换电路获得的中间电压的混合电压的放大器部分（104）。放大器部分（104）包括具有相同配置并且彼此并联的多个运算放大器（amp1，amp1 ...）。

5. 发明申请

US20090115502A1 REFERENCE CURRENT CIRCUIT, REFERENCE VOLTAGE CIRCUIT, AND STARTUP CIRCUIT 有权
标题翻译：参考电流电路，参考电压电路和启动电路
公开(公告)号：US20090115502A1
公开(公告)日：2009-05-07
申请号：US12093393
申请日：2007-09-04
申请人： Shiro Sakiyama , Akinori Matsumoto , Takashi Morie , Masayoshi Kinoshita
发明人： Shiro Sakiyama , Akinori Matsumoto , Takashi Morie , Masayoshi Kinoshita
IPC分类号： G05F1/10
CPC分类号： G05F3/262
摘要： A current mirror circuit 10 is formed to have a current ratio (a transistor size ratio) of 1:m. As well, respective pairs of nMOS transistors MN1, MN3 and nMOS transistors MN2, MN4 are formed to have a current ratio of 1:m. Two currents output from the current mirror circuit 10 are each distributed to two. The distributed currents flowing in the nMOS transistors MN2, MN4 are added and are then allowed to flow into one resistor R2. Hence, for the resistor R2, only one resistor in which current of double flows suffices when m=1, for example. This effortlessly reduces the necessary resistance to one fourth.
摘要翻译：电流镜电路10形成为具有1：m的电流比（晶体管尺寸比）。同样，各对nMOS晶体管MN1，MN3和nMOS晶体管MN2，MN4形成为具有1：m的电流比。从电流镜电路10输出的两个电流分别分配给两个。在nMOS晶体管MN2，MN4中流动的分布电流相加，然后被允许流入一个电阻器R2。因此，对于电阻器R2，例如当m = 1时，只有一个双电流的电流就足够了。这轻而易举地减少了四分之一的必要阻力。

6. 发明申请

US20080315933A1 PULSE SYNTHESIS CIRCUIT 有权
标题翻译：脉冲合成电路
公开(公告)号：US20080315933A1
公开(公告)日：2008-12-25
申请号：US12133901
申请日：2008-06-05
申请人： Shiro Sakiyama , Yusuke Tokunaga , Shiro Dosho , Akinori Matsumoto , Takashi Morie , Kazuaki Sogawa , Yukihiro Sasagawa , Masaya Sumita
发明人： Shiro Sakiyama , Yusuke Tokunaga , Shiro Dosho , Akinori Matsumoto , Takashi Morie , Kazuaki Sogawa , Yukihiro Sasagawa , Masaya Sumita
IPC分类号： H03K3/00
CPC分类号： H03K5/00006 , H03K5/13
摘要： A high-level period of each of n first pulse signals partially or wholly overlaps a period during which all of n second pulse signals are at the low level. A high-level period of each of the n second pulse signals partially or wholly overlaps a period during which all of the n first pulse signals are at the low level. Each of n first drive transistors includes a source connected to a ground node, a drain connected to a first node, and a gate receiving a corresponding one of the first pulse signals. Each of n second drive transistors includes a source connected to the ground node, a drain connected to a second node, and a gate receiving a corresponding one of the second pulse signals. A current mirror circuit allows a current corresponding to a current flowing through the second node to flow through the first node.
摘要翻译： n个第一脉冲信号中的每一个的高电平周期部分或全部与在所有n个第二脉冲信号都处于低电平的期间重叠。 n个第二脉冲信号中的每一个的高电平周期部分地或完全地重叠在所有n个第一脉冲信号处于低电平的时段。 n个第一驱动晶体管中的每一个包括连接到接地节点的源极，连接到第一节点的漏极以及接收相应的一个第一脉冲信号的栅极。 n个第二驱动晶体管中的每一个包括连接到接地节点的源极，连接到第二节点的漏极和接收相应的一个第二脉冲信号的栅极。电流镜电路允许对应于流过第二节点的电流的电流流过第一节点。

7. 发明授权

US07327182B2 Switched capacitor filter and feedback system 有权
标题翻译：开关电容滤波器和反馈系统
公开(公告)号：US07327182B2
公开(公告)日：2008-02-05
申请号：US11396464
申请日：2006-04-04
申请人： Shiro Dosho , Yusuke Tokunaga , Takashi Morie
发明人： Shiro Dosho , Yusuke Tokunaga , Takashi Morie
IPC分类号： G06F7/64
CPC分类号： H03H19/004 , H03D13/004 , H03L7/0891 , H03L7/093 , H03L7/18
摘要： A switched capacitor filter comprises three switched capacitor circuits. Each switched capacitor circuit has a capacitance. A first state that the capacitance is connected to an input end of a current signal, a second state that the capacitance is connected to an output end of a voltage signal, and a third state that the capacitance is connected to a side of a filter capacitance, are cycled. These three switched capacitor circuits are operated under an interleave control so that the first to third states do not each overlap between the three switched capacitor circuits.
摘要翻译：开关电容滤波器包括三个开关电容器电路。每个开关电容电路具有电容。电容连接到电流信号的输入端的第一状态，电容连接到电压信号的输出端的第二状态，以及电容连接到滤波电容的一侧的第三状态，循环。这三个开关电容器电路在交错控制下操作，使得第一至第三状态在三个开关电容器电路之间不重叠。

8. 发明申请

US20080007243A1 Reference voltage generation circuit 有权
标题翻译：参考电压发生电路
公开(公告)号：US20080007243A1
公开(公告)日：2008-01-10
申请号：US11783800
申请日：2007-04-12
申请人： Akinori Matsumoto , Shiro Sakiyama , Takashi Morie
发明人： Akinori Matsumoto , Shiro Sakiyama , Takashi Morie
IPC分类号： G05F3/16
CPC分类号： G05F3/30
摘要： A reference voltage generation circuit of the present invention includes: a band gap reference-type current generation circuit for controlling each of currents flowing through a first current path and a second current path, which are extending from a first node to a second node, to be a predetermined reference current, by utilizing a voltage difference occurring between a pair of transistors or diodes; and a resistive load circuit provided between the second node and a third node.
摘要翻译：本发明的参考电压产生电路包括：带隙基准电流产生电路，用于控制从第一节点延伸到第二节点的流过第一电流路径和第二电流路径的每个电流到通过利用在一对晶体管或二极管之间出现的电压差来作为预定的参考电流; 以及设置在第二节点和第三节点之间的电阻性负载电路。

9. 发明授权

US07271648B2 Ladder filter, analog equalizer and signal readout system 有权
标题翻译：梯形滤波器，模拟均衡器和信号读出系统
公开(公告)号：US07271648B2
公开(公告)日：2007-09-18
申请号：US10680129
申请日：2003-10-08
申请人： Shiro Dosho , Takashi Morie
发明人： Shiro Dosho , Takashi Morie
IPC分类号： H03K5/00
CPC分类号： G11B20/10009 , H03H11/04 , H03H11/486 , H03H11/50
摘要： A ladder filter includes multiple inductor sections, each including voltage-controlled current sources and capacitors. A second signal input terminal is provided for the filter separately from an ordinary signal input terminal and a signal, which has been input through the second terminal, is supplied to one of the voltage-controlled current sources by way of a gain calculator. By adjusting the gain obtained by the gain calculator to an appropriate value, the ladder filter can make the numerator of its transfer function freely definable.
摘要翻译：梯形滤波器包括多个电感器部分，每个电路部分包括压控电流源和电容器。与普通信号输入端分开设置用于滤波器的第二信号输入端子，并且已经通过第二端子输入的信号通过增益计算器提供给一个压控电流源。通过将增益计算器获得的增益调整到适当的值，梯形滤波器可以使其传递函数的分子自由定义。

10. 发明申请

US20070162828A1 Coding method and apparatus, and computer program and computer-readable storage medium 失效
标题翻译：编码方法和装置，以及计算机程序和计算机可读存储介质
公开(公告)号：US20070162828A1
公开(公告)日：2007-07-12
申请号：US10580327
申请日：2005-01-24
申请人： Yusuke Mitarai , Masakazu Matsugu , Katsuhiko Mori , Takashi Morie
发明人： Yusuke Mitarai , Masakazu Matsugu , Katsuhiko Mori , Takashi Morie
IPC分类号： H03M13/00
CPC分类号： H04N19/192 , H04N19/119 , H04N19/136 , H04N19/172 , H04N19/50 , H04N19/60
摘要： Data in multidimensional space such as a two-dimensional image is encoded with high efficiency. Further, as two-dimensional data can be decomposed to one-dimensional bases, the problem of wiring for two-dimensional parallelizing in a convolution arithmetic unit can be solved. For this purpose, two-dimensional image data f(x,y) to be encoded is inputted, and one-dimensional adaptive bases X(x),Y(y) representing the two-dimensional image are obtained. Next, a reconstructed image is generated based on the one-dimensional adaptive bases, and the one-dimensional adaptive bases are corrected based on an error E between the reconstructed image and the input image. The correction is repeated until the error E is reduced.
摘要翻译：多维空间中的数据（如二维图像）以高效率进行编码。此外，由于二维数据可以分解为一维的基础，因此可以解决卷积运算单元中二维并行化的布线问题。为此，输入要编码的二维图像数据f（x，y），并且获得表示二维图像的一维自适应基准X（x），Y（y）。接下来，基于一维自适应基础生成重建图像，并且基于重构图像和输入图像之间的误差E来校正一维自适应基准。重复校正直到误差E减小。

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