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1. 发明授权

US5937020A Digital information signal reproducing circuit and digital information system 失效
标题翻译：数字信息信号再现电路和数字信息系统
公开(公告)号：US5937020A
公开(公告)日：1999-08-10
申请号：US719875
申请日：1996-09-25
申请人： Kenichi Hase , Ryutaro Horita , Tsuguyoshi Hirooka , Haruto Katsu , Takashi Nara , Shoichi Miyazawa, deceased , Shintaro Suzumura
发明人： Kenichi Hase , Ryutaro Horita , Tsuguyoshi Hirooka , Haruto Katsu , Takashi Nara , Shoichi Miyazawa, deceased , Shintaro Suzumura
IPC分类号： G11B20/10 , G11B20/14 , G11B20/18 , H03L7/087 , H03L7/22 , H03M1/36 , H04L7/033 , H04L7/04 , H04L7/10 , H03D3/24 , H03D3/02 , H03L7/00
CPC分类号： G11B20/10055 , G11B20/10009 , G11B20/1403 , H03L7/087 , H03M1/365 , H04L7/033 , H04L7/046 , H04L7/10
摘要： Digital information including a sync data field and a user data field subsequent thereto is read from a storage media as a digital information signal in an analog signal format. The obtained signal is sampled according to a clock signal and is thereby transformed into a digital information signal in a digital format. In the sync data field, the clock signal is synchronized with the digital information signal by an analog PLL circuit. Thereafter, in the user data field, the clock signal is synchronized with the digital information signal by a digital PLL circuit.
摘要翻译：从存储介质读取包括同步数据字段和随后的用户数据字段的数字信息作为模拟信号格式的数字信息信号。所获得的信号根据时钟信号被采样，从而被转换为数字格式的数字信息信号。在同步数据字段中，时钟信号通过模拟PLL电路与数字信息信号同步。此后，在用户数据字段中，时钟信号通过数字PLL电路与数字信息信号同步。

2. 发明授权

US5636254A Signal processing delay circuit 失效
标题翻译：信号处理延迟电路
公开(公告)号：US5636254A
公开(公告)日：1997-06-03
申请号：US430534
申请日：1995-04-25
申请人： Kenichi Hase , Ryutaro Horita , Kunio Watanabe , Yoshiteru Ishida , Takashi Nara , Hiroshi Kimura
发明人： Kenichi Hase , Ryutaro Horita , Kunio Watanabe , Yoshiteru Ishida , Takashi Nara , Hiroshi Kimura
IPC分类号： G11B5/09 , G11B20/10 , G11B20/14 , H03H11/26 , H03H11/54 , H03K5/13 , H03K5/135 , H03L7/081 , H03L7/089 , H03L7/099 , H04L7/00 , H04L7/02
CPC分类号： H03L7/0805 , G11B20/10 , G11B20/1403 , H03K5/13 , H03L7/0812 , H03L7/0896 , H03L7/0995 , H04L7/02 , H04L7/0008 , H04L7/0041
摘要： A signal processing delay circuit is fabricated as a semiconductor integration circuit to cope with increase in the data transfer speed and data recording and reproducing density on a recording medium. In the delay circuit, the amount of delay of a reference delay circuit of a delay PLL is controlled to take a fixed value independent of deviation in quality of the semiconductor circuit, change in power, and alteration in temperature. A control signal supervising the delay amount of the reference delay circuit is employed to control amounts of delay of input signals supplied to a window adjustment delay circuit of a window adjustment circuit and a T/2 generation delay circuit generating a synchronizing signal. Each of these delay circuits includes an analog variable delay circuit having the same configuration. The window adjustment delay circuit is supervised by a signal obtained by weighting the control signal by a D/A converter. A data acquisition circuit and a data write circuit each include an analog variable delay circuit.
摘要翻译：制造信号处理延迟电路作为半导体积分电路，以应对数据传送速度的增加和记录介质上的数据记录和再现密度。在延迟电路中，延迟PLL的参考延迟电路的延迟量被控制为独立于半导体电路的质量偏差，功率变化和温度变化的固定值。采用监视参考延迟电路的延迟量的控制信号来控制提供给窗口调整电路的窗口调整延迟电路的输入信号的延迟量和产生同步信号的T / 2产生延迟电路。这些延迟电路中的每一个包括具有相同配置的模拟可变延迟电路。窗口调整延迟电路由通过D / A转换器对控制信号进行加权而获得的信号进行监视。数据采集电路和数据写入电路各自包括模拟可变延迟电路。

3. 发明授权

US5572163A Active filter control apparatus 失效
标题翻译：有源滤波器控制装置
公开(公告)号：US5572163A
公开(公告)日：1996-11-05
申请号：US362874
申请日：1994-12-23
申请人： Hiroshi Kimura , Ryutaro Horita , Kenichi Hase , Kunio Watanabe , Takashi Nara
发明人： Hiroshi Kimura , Ryutaro Horita , Kenichi Hase , Kunio Watanabe , Takashi Nara
IPC分类号： H03H11/04 , H03B5/00
CPC分类号： H03H11/0472 , H03H11/0433 , H03H2210/023
摘要： An active filter control apparatus for controlling or tuning an active filter having a variable cut-off frequency. The active filter control apparatus includes a control circuit for controlling or tuning the cut-off frequency of the active filter and a characteristic correction generator for generating a correction signal to correct a group delay characteristic of the active filter in accordance with a set cut-off frequency. The characteristic correction includes a correction signal generator for generating the correction signal in accordance with a set correction amount. The cut-off frequency controller controls tunes the characteristic of the active filter in accordance with the correction signal. Preferably, the apparatus is formed of a one-chip LSI integrated on one chip. The control apparatus can be utilized to control the speed in a recording/reproducing apparatus such as a optical disk drive or a magnetic tape drive apparatus.
摘要翻译：一种用于控制或调谐具有可变截止频率的有源滤波器的有源滤波器控制装置。有源滤波器控制装置包括用于控制或调谐有源滤波器的截止频率的控制电路和用于根据设定的截止产生校正信号校正有源滤波器的组延迟特性的特性校正发生器频率。特征校正包括用于根据设定的校正量产生校正信号的校正信号发生器。截止频率控制器根据校正信号控制有源滤波器的特性。优选地，该装置由集成在一个芯片上的单芯片LSI形成。控制装置可以用于控制诸如光盘驱动器或磁带驱动装置的记录/再现装置中的速度。

4. 发明授权

US5878097A Signal processing delay circuit 失效
标题翻译：信号处理延迟电路
公开(公告)号：US5878097A
公开(公告)日：1999-03-02
申请号：US865704
申请日：1997-05-30
申请人： Kenichi Hase , Ryutaro Horita , Kunio Watanabe , Yoshiteru Ishida , Takashi Nara , Hiroshi Kimura
发明人： Kenichi Hase , Ryutaro Horita , Kunio Watanabe , Yoshiteru Ishida , Takashi Nara , Hiroshi Kimura
IPC分类号： G11B5/09 , G11B20/10 , G11B20/14 , H03H11/26 , H03H11/54 , H03K5/13 , H03K5/135 , H03L7/081 , H03L7/089 , H03L7/099 , H04L7/00 , H04L7/02 , H04L25/36 , H04L25/40
CPC分类号： H03L7/0805 , G11B20/10 , G11B20/1403 , H03K5/13 , H03L7/0812 , H03L7/0896 , H03L7/0995 , H04L7/02 , H04L7/0008 , H04L7/0041
摘要： A signal processing delay circuit is fabricated as a semiconductor integration circuit to cope with increase in the data transfer speed and data recording and reproducing density on a recording medium. In the delay circuit, the amount of delay of a reference delay circuit of a delay PLL is controlled to take a fixed value independent of deviation in quality of the semiconductor circuit, change in power, and alteration in temperature. A control signal supervising the delay amount of the reference delay circuit is employed to control amounts of delay of input signals supplied to a window adjustment delay circuit of a window adjustment circuit and a T/2 generation delay circuit generating a synchronizing signal. Each of these delay circuits includes an analog variable delay circuit having the same configuration. The window adjustment delay circuit is supervised by a signal obtained by weighting the control signal by a D/A converter. A data acquisition circuit and a data write circuit each include an analog variable delay circuit.
摘要翻译：制造信号处理延迟电路作为半导体积分电路，以应对数据传送速度的增加和记录介质上的数据记录和再现密度。在延迟电路中，延迟PLL的参考延迟电路的延迟量被控制为独立于半导体电路的质量偏差，功率变化和温度变化的固定值。采用监视参考延迟电路的延迟量的控制信号来控制提供给窗口调整电路的窗口调整延迟电路的输入信号的延迟量和产生同步信号的T / 2产生延迟电路。这些延迟电路中的每一个包括具有相同配置的模拟可变延迟电路。窗口调整延迟电路由通过D / A转换器对控制信号进行加权而获得的信号进行监视。数据采集电路和数据写入电路各自包括模拟可变延迟电路。

5. 发明授权

US5222002A Semiconductor integrated circuit which performs phase synchronization 失效
标题翻译：执行相位同步的半导体集成电路
公开(公告)号：US5222002A
公开(公告)日：1993-06-22
申请号：US687638
申请日：1991-04-19
申请人： Kenichi Hase , Shoichi Miyazawa , Ryutaro Horita , Shinichi Kojima
发明人： Kenichi Hase , Shoichi Miyazawa , Ryutaro Horita , Shinichi Kojima
IPC分类号： G11B20/14 , G11B5/012 , G11B20/10 , H03L7/06 , H04L25/02 , H04L25/45
CPC分类号： H04L25/0286 , G11B20/10009 , H04L25/45 , G11B5/012 , H04L25/0292
摘要： Pulse detector and a data separator are integrated on a single chip semiconductor integrated circuit. In the pulse detector, an input stage of a gain variable amplifier, which amplifies an input signal applied thereto so as to have a constant peak, includes a bipolar transistor, and a pulse generator for generating a pulse shape signal according to a differential value of an output from the gain variable amplifier includes a Bi-CMOS gate or a CMOS gate. In the data separator, a voltage controlled oscillator for generating a clock signal includes a bipolar transistor. A frequency phase comparator for comparing the pulse shape signal in phases with the clock signal generated by the voltage controlled oscillator to obtain a phase difference, includes a Bi-CMOS gate and a CMOS gate.
摘要翻译：脉冲检测器和数据分离器集成在单芯片半导体集成电路上。在脉冲检测器中，增益可变放大器的输入级放大施加到其上的具有恒定峰值的输入信号，包括双极型晶体管和脉冲发生器，用于根据微分值产生脉冲形状信号来自增益可变放大器的输出包括Bi-CMOS栅极或CMOS栅极。在数据分离器中，用于产生时钟信号的压控振荡器包括双极晶体管。用于将脉冲形状信号与由压控振荡器产生的时钟信号进行比较以获得相位差的频率相位比较器包括Bi-CMOS栅极和CMOS栅极。

6. 发明授权

US5559645A Disk recording apparatus with adaptive window adjusting 失效
标题翻译：具有自适应窗口调节的磁盘记录装置
公开(公告)号：US5559645A
公开(公告)日：1996-09-24
申请号：US216606
申请日：1994-03-23
申请人： Shyoichi Miyazawa , Ryutaro Horita , Kenichi Hase , Satoshi Kawamura , Shinichi Kojima , Toshiyuki Iseki
发明人： Shyoichi Miyazawa , Ryutaro Horita , Kenichi Hase , Satoshi Kawamura , Shinichi Kojima , Toshiyuki Iseki
IPC分类号： G11B5/012 , G11B7/0045 , G11B20/10 , G11B20/14 , G11B5/09
CPC分类号： G11B20/10212 , G11B20/1403 , G11B5/012 , G11B7/0045
摘要： In a signal processing unit for writing/reading data on/from a disk-shaped recording medium of a disk apparatus, all of a data separator, a code decoder circuit, a code encoder and a write compensation circuit are constructed on a one-chip integrated circuit. The data separator separates a synchronization clock from a code data reproduced from the disk. The code decoder circuit produces decoded data from the synchronization clock as the output from the data separator, and synchronized code data. The code encoder encodes data supplied from a host computer or a disk controller into code data. The write compensation circuit compensates for a peak shift with respect to write code data. This integrated circuit is fabricated by a Bipolar-CMOS process by which a bipolar transistor and a CMOS transistor are mixed with each other thereon.
摘要翻译：在用于在盘装置的盘形记录介质上写入/读取数据的信号处理单元中，数据分离器，代码解码器电路，代码编码器和写补偿电路全部构成在单片机集成电路。数据分离器将同步时钟与从盘再现的代码数据分离。码解码器电路从数据分离器产生来自同步时钟的解码数据，并产生同步的代码数据。代码编码器将从主计算机或磁盘控制器提供的数据编码为代码数据。写补偿电路相对于写代码数据补偿峰移。该集成电路由双极CMOS工艺制造，双极晶体管和CMOS晶体管彼此混合。

7. 发明授权

US5062011A Address mark generating method and its circuit in a data memory 失效
标题翻译：地址标记生成方法及其在数据存储器中的电路
公开(公告)号：US5062011A
公开(公告)日：1991-10-29
申请号：US327757
申请日：1989-03-23
申请人： Kenichi Hase , Shyoichi Miyazawa , Ryutaro Horita , Shinichi Kojima , Akira Uragami , Takashi Watanabe , Yoshinori Yoshino
发明人： Kenichi Hase , Shyoichi Miyazawa , Ryutaro Horita , Shinichi Kojima , Akira Uragami , Takashi Watanabe , Yoshinori Yoshino
IPC分类号： G11B20/10 , G11B20/14 , G11B27/30
CPC分类号： G11B27/3027 , G11B20/1419 , G11B20/1426
摘要： When data are memorized in a 2-7 RLL code on a disc shaped memorizing medium using a sector format, as an address mark in each sector a 2-7 illegal pattern is used; a 1-byte data "8B" in an NRZ signal is converted into a 2-7 RLL code, and further it is modified into the 2-7 illegal pattern.A disc controller in a disc memory inserts the 1-byte data "8B" into a specified position in an NRZ signal and transmits it to an encoder/decoder. In the encoder, the 1-byte data "8B" in an NRZ signal is detected, and a 2-7 illegal pattern is formed by reversing a specified bit of a 2-7 RLL code formed by converting the 1-byte data "8B", and the illegal pattern is sent to the read/write amplifier.
摘要翻译：当使用扇区格式将数据存储在盘形存储介质上的2-7 RLL代码中时，作为每个扇区中的地址标记，使用2-7非法模式; NRZ信号中的1字节数据“8B”被转换为2-7 RLL码，并进一步修改为2-7非法码型。盘存储器中的盘控制器将1字节数据“8B”插入NRZ信号中的指定位置并将其发送到编码器/解码器。在编码器中，检测到NRZ信号中的1字节数据“8B”，并且通过将通过转换1字节数据“8B”形成的2-7 RLL码的指定位反转来形成2-7非法模式 “，并且非法模式被发送到读/写放大器。

8. 发明授权

US5633766A Magnetic disk storage apparatus with phase sync circuit having controllable response characteristics 失效
标题翻译：具有相位同步电路的磁盘存储装置具有可控的响应特性
公开(公告)号：US5633766A
公开(公告)日：1997-05-27
申请号：US360426
申请日：1994-12-21
申请人： Kenichi Hase , Syoichi Miyazawa , Ryutaro Horita , Shinichi Kojima , Akihiko Hirano , Akira Uragami
发明人： Kenichi Hase , Syoichi Miyazawa , Ryutaro Horita , Shinichi Kojima , Akihiko Hirano , Akira Uragami
IPC分类号： G11B5/012 , G11B20/14 , H03K3/282 , H03L7/089 , H03L7/093 , H03L7/095 , H03L7/099 , H03L7/107 , H04L7/033 , G11B5/09 , G11B15/04
CPC分类号： H03L7/093 , G11B20/1403 , G11B5/012 , H03K3/2821 , H03L7/089 , H03L7/0895 , H03L7/0898 , H03L7/095 , H03L7/099 , H03L7/107 , G11B2020/10916 , H03L2207/06 , H04L7/033
摘要： A magnetic disk storage apparatus provides with a phase locked loop or a phase sync circuit including a phase comparator, a charge pump, a filter and a voltage-controlled oscillator. The phase sync circuit includes a register which is connected to an information processing system and adapted to store therein the response characteristics of the phase comparator, the charge pump, the filter and the voltage-controlled oscillator as instructed from the information processing system. In this way, in accordance with the information on the response characteristics from the information processing system, the phase sync circuit is controlled thereby to assure a stable operation even in the case of the data transfer speed varying between inner and outer track such as occurs in a magnetic disk.
摘要翻译：磁盘存储装置提供锁相环或包括相位比较器，电荷泵，滤波器和压控振荡器的相位同步电路。相位同步电路包括连接到信息处理系统并适合于从信息处理系统指示的其中存储相位比较器，电荷泵，滤波器和压控振荡器的响应特性的寄存器。以这种方式，根据关于来自信息处理系统的响应特性的信息，控制相位同步电路，从而即使在内外轨道之间变化的数据传输速度的情况下也可以确保稳定的操作，例如发生在磁盘。

9. 发明授权

US5999353A Magnetic disk storage apparatus with phase sync circuit having controllable response characteristic 失效
公开(公告)号：US5999353A
公开(公告)日：1999-12-07
申请号：US826972
申请日：1997-04-09
申请人： Kenichi Hase , Syoichi Miyazawa , Ryutaro Horita , Shinichi Kojima , Akihiko Hirano , Akira Uragami
发明人： Kenichi Hase , Syoichi Miyazawa , Ryutaro Horita , Shinichi Kojima , Akihiko Hirano , Akira Uragami
IPC分类号： G11B5/012 , G11B20/14 , H03K3/282 , H03L7/089 , H03L7/093 , H03L7/095 , H03L7/099 , H03L7/107 , H04L7/033 , G11B5/09 , G11B15/04
CPC分类号： H03L7/093 , G11B20/1403 , G11B5/012 , H03K3/2821 , H03L7/089 , H03L7/0895 , H03L7/0898 , H03L7/095 , H03L7/099 , H03L7/107 , G11B2020/10916 , H03L2207/06 , H04L7/033
摘要： A magnetic disk storage apparatus provides with a phase locked loop or a phase sync circuit including a phase comparator, a charge pump, a filter and a voltage-controlled oscillator. The phase sync circuit includes a register which is connected to an information processing system and adapted to store therein the response characteristics of the phase comparator, the charge pump, the filter and the voltage-controlled oscillator as instructed from the information processing system. In this way, in accordance with the information on the response characteristics from the information processing system, the phase sync circuit is controlled thereby to assure a stable operation even in the case of the data transfer speed varying between inner and outer track such as occurs in a magnetic disk.

10. 发明授权

US5475715A Sync data introduction method and system 失效
标题翻译：同步数据介绍方法和系统
公开(公告)号：US5475715A
公开(公告)日：1995-12-12
申请号：US886860
申请日：1992-05-22
申请人： Kenichi Hase , Syoichi Miyazawa , Ryutaro Horita , Akihiko Hirano , Hiroshi Kimura , Akira Uragami
发明人： Kenichi Hase , Syoichi Miyazawa , Ryutaro Horita , Akihiko Hirano , Hiroshi Kimura , Akira Uragami
IPC分类号： G11B20/10 , G11B20/14 , H04L1/00 , H04L7/00 , H04L7/033 , H04L7/08
CPC分类号： G11B20/1403 , H04L7/08 , H04L7/033
摘要： A data device for introducing the data read from a recording medium includes first creation device for receiving a read code signal corresponding to the data stored on a data recording medium to create first two phase signals which repeat inversion with a substantially equal period to each other on the basis of a change in the waveform of the read code; second creation device for receiving the first two phase signals to create second two phase signals with their one phase occupying most of their period having an overlapping portion with each other, the period being twice as long as that of the first two phase signals; and third creation device for receiving the read code signal and said second two phase signals to create a second code signal corresponding to the read code signal which shifts during the one phase period of said second two phase signals. The second two phase signals serve to extend sufficiently the window for introducing the read code to provide stabilized read for the data including jitter due to rotation fluctuation of the recording medium.
摘要翻译：用于引入从记录介质读取的数据的数据设备包括：第一创建设备，用于接收与存储在数据记录介质上的数据相对应的读取代码信号，以产生以两个相同周期重复反相的第一两个相位信号读取代码的波形变化的基础; 第二创建装置，用于接收前两个相位信号以产生第二两相信号，其相位占据其大部分周期具有彼此重叠的部分，该周期是前两个相位信号的两倍; 以及第三创建装置，用于接收读取代码信号和所述第二两个相位信号，以产生对应于在所述第二两个相位信号的一个相位周期期间移位的读取代码信号的第二代码信号。第二个两个相位信号充分地延伸用于引入读取代码的窗口，以提供包括由记录介质的旋转波动引起的抖动的数据的稳定读数。

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