专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5999353A Magnetic disk storage apparatus with phase sync circuit having controllable response characteristic 失效
公开(公告)号：US5999353A
公开(公告)日：1999-12-07
申请号：US826972
申请日：1997-04-09
申请人： Kenichi Hase , Syoichi Miyazawa , Ryutaro Horita , Shinichi Kojima , Akihiko Hirano , Akira Uragami
发明人： Kenichi Hase , Syoichi Miyazawa , Ryutaro Horita , Shinichi Kojima , Akihiko Hirano , Akira Uragami
IPC分类号： G11B5/012 , G11B20/14 , H03K3/282 , H03L7/089 , H03L7/093 , H03L7/095 , H03L7/099 , H03L7/107 , H04L7/033 , G11B5/09 , G11B15/04
CPC分类号： H03L7/093 , G11B20/1403 , G11B5/012 , H03K3/2821 , H03L7/089 , H03L7/0895 , H03L7/0898 , H03L7/095 , H03L7/099 , H03L7/107 , G11B2020/10916 , H03L2207/06 , H04L7/033
摘要： A magnetic disk storage apparatus provides with a phase locked loop or a phase sync circuit including a phase comparator, a charge pump, a filter and a voltage-controlled oscillator. The phase sync circuit includes a register which is connected to an information processing system and adapted to store therein the response characteristics of the phase comparator, the charge pump, the filter and the voltage-controlled oscillator as instructed from the information processing system. In this way, in accordance with the information on the response characteristics from the information processing system, the phase sync circuit is controlled thereby to assure a stable operation even in the case of the data transfer speed varying between inner and outer track such as occurs in a magnetic disk.

2. 发明授权

US5633766A Magnetic disk storage apparatus with phase sync circuit having controllable response characteristics 失效
标题翻译：具有相位同步电路的磁盘存储装置具有可控的响应特性
公开(公告)号：US5633766A
公开(公告)日：1997-05-27
申请号：US360426
申请日：1994-12-21
申请人： Kenichi Hase , Syoichi Miyazawa , Ryutaro Horita , Shinichi Kojima , Akihiko Hirano , Akira Uragami
发明人： Kenichi Hase , Syoichi Miyazawa , Ryutaro Horita , Shinichi Kojima , Akihiko Hirano , Akira Uragami
IPC分类号： G11B5/012 , G11B20/14 , H03K3/282 , H03L7/089 , H03L7/093 , H03L7/095 , H03L7/099 , H03L7/107 , H04L7/033 , G11B5/09 , G11B15/04
CPC分类号： H03L7/093 , G11B20/1403 , G11B5/012 , H03K3/2821 , H03L7/089 , H03L7/0895 , H03L7/0898 , H03L7/095 , H03L7/099 , H03L7/107 , G11B2020/10916 , H03L2207/06 , H04L7/033
摘要： A magnetic disk storage apparatus provides with a phase locked loop or a phase sync circuit including a phase comparator, a charge pump, a filter and a voltage-controlled oscillator. The phase sync circuit includes a register which is connected to an information processing system and adapted to store therein the response characteristics of the phase comparator, the charge pump, the filter and the voltage-controlled oscillator as instructed from the information processing system. In this way, in accordance with the information on the response characteristics from the information processing system, the phase sync circuit is controlled thereby to assure a stable operation even in the case of the data transfer speed varying between inner and outer track such as occurs in a magnetic disk.
摘要翻译：磁盘存储装置提供锁相环或包括相位比较器，电荷泵，滤波器和压控振荡器的相位同步电路。相位同步电路包括连接到信息处理系统并适合于从信息处理系统指示的其中存储相位比较器，电荷泵，滤波器和压控振荡器的响应特性的寄存器。以这种方式，根据关于来自信息处理系统的响应特性的信息，控制相位同步电路，从而即使在内外轨道之间变化的数据传输速度的情况下也可以确保稳定的操作，例如发生在磁盘。

3. 发明授权

US06266200B1 Magnetic disk storage apparatus 失效
标题翻译：磁盘存储装置
公开(公告)号：US06266200B1
公开(公告)日：2001-07-24
申请号：US09438510
申请日：1999-11-12
申请人： Kenichi Hase , Syoichi Miyazawa , Ryutaro Horita , Shinichi Kojima , Akihiko Hirano , Akira Uragami
发明人： Kenichi Hase , Syoichi Miyazawa , Ryutaro Horita , Shinichi Kojima , Akihiko Hirano , Akira Uragami
IPC分类号： G11B509
CPC分类号： H03L7/093 , G11B5/012 , G11B20/1403 , G11B2020/10916 , H03K3/2821 , H03L7/089 , H03L7/0895 , H03L7/0898 , H03L7/095 , H03L7/099 , H03L7/107 , H03L2207/06 , H04L7/033
摘要： A magnetic disk storage apparatus having a magnetic disk-type storage medium; a head for reading data recorded on the magnetic disk-type storage medium, a processor, a phase synchronizing circuit having a controllable response characteristic and for outputting a clock signal to handle the data read from the magnetic disk-type storage medium, and a memory for storing information to control the response characteristic of the phase synchronizing circuit previously set in accordance with an access position on the magnetic disk-type storage medium. The processor generates the access position on the magnetic disk-type storage medium and data for commanding the control of the response characteristic of the phase synchronizing circuit in accordance with the information stored in the memory, and commands the control of the response characteristic by the data for the command, at a time consistent with a time of a seek operation of the head for the access position on the magnetic disk-type storage medium or a time before the seek operation of the head. Further, the response characteristic is controlled by the command.
摘要翻译：一种具有磁盘式存储介质的磁盘存储装置; 用于读取记录在磁盘式存储介质上的数据的磁头，处理器，具有可控响应特性的相位同步电路，以及用于输出时钟信号以处理从磁盘式存储介质读取的数据的存储器用于存储用于控制根据磁盘式存储介质上的存取位置预先设定的相位同步电路的响应特性的信息。处理器根据存储在存储器中的信息产生磁盘式存储介质上的访问位置和用于指示相位同步电路的响应特性的控制的数据，并且通过数据命令对响应特性的控制在与磁盘式存储介质上的访问位置的头部的寻道操作的时间或头部的搜索操作之前的时间相一致的时间。此外，响应特性由命令控制。

4. 发明授权

US5404250A Magnetic disk storage apparatus with phase sync circuit having controllable response characteristic 失效
标题翻译：具有可控响应特性的相位同步电路的磁盘存储装置
公开(公告)号：US5404250A
公开(公告)日：1995-04-04
申请号：US177694
申请日：1994-01-04
申请人： Kenichi Hase , Syoichi Miyazawa , Ryutaro Horita , Shinichi Kojima , Akihiko Hirano , Akira Uragami
发明人： Kenichi Hase , Syoichi Miyazawa , Ryutaro Horita , Shinichi Kojima , Akihiko Hirano , Akira Uragami
IPC分类号： G11B5/012 , G11B20/14 , H03K3/282 , H03L7/089 , H03L7/093 , H03L7/095 , H03L7/099 , H03L7/107 , H04L7/033 , G11B5/09 , H03K5/00 , H03L7/00
CPC分类号： H03L7/093 , G11B20/1403 , G11B5/012 , H03K3/2821 , H03L7/089 , H03L7/0895 , H03L7/0898 , H03L7/095 , H03L7/099 , H03L7/107 , G11B2020/10916 , H03L2207/06 , H04L7/033
摘要： A magnetic disk storage apparatus provides with a phase locked loop or a phase sync circuit including a phase comparator, a charge pump, a filter and a voltage-controlled oscillator. The phase sync circuit includes a register which is connected to an information processing system and adapted to store therein the response characteristics of the phase comparator, the charge pump, the filter and the voltage-controlled oscillator as instructed from the information processing system. In this way, in accordance with the information on the response characteristics from the information processing system, the phase sync circuit is controlled thereby to assure a stable operation even in the case of the data transfer speed varying between inner and outer track such as occurs in a magnetic disk.
摘要翻译：磁盘存储装置提供锁相环或包括相位比较器，电荷泵，滤波器和压控振荡器的相位同步电路。相位同步电路包括连接到信息处理系统并适合于从信息处理系统指示的其中存储相位比较器，电荷泵，滤波器和压控振荡器的响应特性的寄存器。以这种方式，根据关于来自信息处理系统的响应特性的信息，控制相位同步电路，从而即使在内外轨道之间变化的数据传输速度的情况下也可以确保稳定的操作，例如发生在磁盘。

5. 发明授权

US5062011A Address mark generating method and its circuit in a data memory 失效
标题翻译：地址标记生成方法及其在数据存储器中的电路
公开(公告)号：US5062011A
公开(公告)日：1991-10-29
申请号：US327757
申请日：1989-03-23
申请人： Kenichi Hase , Shyoichi Miyazawa , Ryutaro Horita , Shinichi Kojima , Akira Uragami , Takashi Watanabe , Yoshinori Yoshino
发明人： Kenichi Hase , Shyoichi Miyazawa , Ryutaro Horita , Shinichi Kojima , Akira Uragami , Takashi Watanabe , Yoshinori Yoshino
IPC分类号： G11B20/10 , G11B20/14 , G11B27/30
CPC分类号： G11B27/3027 , G11B20/1419 , G11B20/1426
摘要： When data are memorized in a 2-7 RLL code on a disc shaped memorizing medium using a sector format, as an address mark in each sector a 2-7 illegal pattern is used; a 1-byte data "8B" in an NRZ signal is converted into a 2-7 RLL code, and further it is modified into the 2-7 illegal pattern.A disc controller in a disc memory inserts the 1-byte data "8B" into a specified position in an NRZ signal and transmits it to an encoder/decoder. In the encoder, the 1-byte data "8B" in an NRZ signal is detected, and a 2-7 illegal pattern is formed by reversing a specified bit of a 2-7 RLL code formed by converting the 1-byte data "8B", and the illegal pattern is sent to the read/write amplifier.
摘要翻译：当使用扇区格式将数据存储在盘形存储介质上的2-7 RLL代码中时，作为每个扇区中的地址标记，使用2-7非法模式; NRZ信号中的1字节数据“8B”被转换为2-7 RLL码，并进一步修改为2-7非法码型。盘存储器中的盘控制器将1字节数据“8B”插入NRZ信号中的指定位置并将其发送到编码器/解码器。在编码器中，检测到NRZ信号中的1字节数据“8B”，并且通过将通过转换1字节数据“8B”形成的2-7 RLL码的指定位反转来形成2-7非法模式 “，并且非法模式被发送到读/写放大器。

6. 发明授权

US5559645A Disk recording apparatus with adaptive window adjusting 失效
标题翻译：具有自适应窗口调节的磁盘记录装置
公开(公告)号：US5559645A
公开(公告)日：1996-09-24
申请号：US216606
申请日：1994-03-23
申请人： Shyoichi Miyazawa , Ryutaro Horita , Kenichi Hase , Satoshi Kawamura , Shinichi Kojima , Toshiyuki Iseki
发明人： Shyoichi Miyazawa , Ryutaro Horita , Kenichi Hase , Satoshi Kawamura , Shinichi Kojima , Toshiyuki Iseki
IPC分类号： G11B5/012 , G11B7/0045 , G11B20/10 , G11B20/14 , G11B5/09
CPC分类号： G11B20/10212 , G11B20/1403 , G11B5/012 , G11B7/0045
摘要： In a signal processing unit for writing/reading data on/from a disk-shaped recording medium of a disk apparatus, all of a data separator, a code decoder circuit, a code encoder and a write compensation circuit are constructed on a one-chip integrated circuit. The data separator separates a synchronization clock from a code data reproduced from the disk. The code decoder circuit produces decoded data from the synchronization clock as the output from the data separator, and synchronized code data. The code encoder encodes data supplied from a host computer or a disk controller into code data. The write compensation circuit compensates for a peak shift with respect to write code data. This integrated circuit is fabricated by a Bipolar-CMOS process by which a bipolar transistor and a CMOS transistor are mixed with each other thereon.
摘要翻译：在用于在盘装置的盘形记录介质上写入/读取数据的信号处理单元中，数据分离器，代码解码器电路，代码编码器和写补偿电路全部构成在单片机集成电路。数据分离器将同步时钟与从盘再现的代码数据分离。码解码器电路从数据分离器产生来自同步时钟的解码数据，并产生同步的代码数据。代码编码器将从主计算机或磁盘控制器提供的数据编码为代码数据。写补偿电路相对于写代码数据补偿峰移。该集成电路由双极CMOS工艺制造，双极晶体管和CMOS晶体管彼此混合。

7. 发明授权

US5402274A Data separator and signal processing circuit with an adjustable window 失效
标题翻译：数据分离器和信号处理电路具有可调窗口
公开(公告)号：US5402274A
公开(公告)日：1995-03-28
申请号：US964294
申请日：1992-10-21
申请人： Shyoichi Miyazawa , Ryutaro Horita , Kenichi Hase , Satoshi Kawamura , Shinichi Kojima , Toshiyuki Iseki
发明人： Shyoichi Miyazawa , Ryutaro Horita , Kenichi Hase , Satoshi Kawamura , Shinichi Kojima , Toshiyuki Iseki
IPC分类号： G11B5/012 , G11B7/0045 , G11B20/10 , G11B20/14 , G11B27/10 , G11B5/09
CPC分类号： G11B20/10212 , G11B20/1403 , G11B5/012 , G11B7/0045
摘要： In a signal processing unit for writing/reading data on/from a disk-shaped recording medium of a disk apparatus, all of a data separator, a code decoder circuit, a code encoder and a write compensation circuit are constructed on a one-chip integrated circuit. The data separator separates a synchronization clock from a code data reproduced from the disk. The code decoder circuit produces decoded data from the synchronization clock as the output from the data separator, and synchronized code data. The code encoder encodes data supplied from a host computer or a disk controller into code data. The write compensation circuit compensates for a peak shift with respect to write code data. This integrated circuit is fabricated by a Bipolar-CMOS process by which a bipolar transistor and a CMOS transistor are mixed with each other thereon.
摘要翻译：在用于在盘装置的盘形记录介质上写入/读取数据的信号处理单元中，数据分离器，代码解码器电路，代码编码器和写补偿电路全部构成在单片机集成电路。数据分离器将同步时钟与从盘再现的代码数据分离。码解码器电路从数据分离器产生来自同步时钟的解码数据，并产生同步的代码数据。代码编码器将从主计算机或磁盘控制器提供的数据编码为代码数据。写补偿电路相对于写代码数据补偿峰移。该集成电路由双极CMOS工艺制造，双极晶体管和CMOS晶体管彼此混合。

8. 发明授权

US5187615A Data separator and signal processing circuit 失效
标题翻译：数据分离器和信号处理电路
公开(公告)号：US5187615A
公开(公告)日：1993-02-16
申请号：US734073
申请日：1991-07-22
申请人： Shyoichi Miyazawa , Ryutaro Horita , Kenichi Hase , Satoshi Kawamura , Shinichi Kojima , Toshiyuki Iseki
发明人： Shyoichi Miyazawa , Ryutaro Horita , Kenichi Hase , Satoshi Kawamura , Shinichi Kojima , Toshiyuki Iseki
IPC分类号： G11B5/012 , G11B7/0045 , G11B20/10 , G11B20/14
CPC分类号： G11B20/10212 , G11B20/1403 , G11B5/012 , G11B7/0045
摘要： In a signal processing unit for writing/reading data on/from a disk-shaped recording medium of a disk apparatus, all of a data separator, a code decoder circuit, a code encoder and a write compensation circuit are constructed on a one-chip integrated circuit. The data separator separates a synchronization clock from a code data reproduced from the disk. The code decoder circuit produces decoded data from the synchronization clock as the output from the data separator, and synchronized code data. The code encoder encodes data supplied from a host computer or a disk controller into code data. The write compensation circuit compensates for a peak shift with respect to write code data. This integrated circuit is fabricated by a Bipolar-CMOS process by which a bipolar transistor and a CMOS transistor are mixed with each other thereon.
摘要翻译：在用于在盘装置的盘形记录介质上写入/读取数据的信号处理单元中，数据分离器，代码解码器电路，代码编码器和写补偿电路全部构成在单片机集成电路。数据分离器将同步时钟与从盘再现的代码数据分离。码解码器电路从数据分离器产生来自同步时钟的解码数据，并产生同步的代码数据。代码编码器将从主计算机或磁盘控制器提供的数据编码为代码数据。写补偿电路相对于写代码数据补偿峰移。该集成电路由双极CMOS工艺制造，双极晶体管和CMOS晶体管彼此混合。

9. 发明授权

US5222002A Semiconductor integrated circuit which performs phase synchronization 失效
标题翻译：执行相位同步的半导体集成电路
公开(公告)号：US5222002A
公开(公告)日：1993-06-22
申请号：US687638
申请日：1991-04-19
申请人： Kenichi Hase , Shoichi Miyazawa , Ryutaro Horita , Shinichi Kojima
发明人： Kenichi Hase , Shoichi Miyazawa , Ryutaro Horita , Shinichi Kojima
IPC分类号： G11B20/14 , G11B5/012 , G11B20/10 , H03L7/06 , H04L25/02 , H04L25/45
CPC分类号： H04L25/0286 , G11B20/10009 , H04L25/45 , G11B5/012 , H04L25/0292
摘要： Pulse detector and a data separator are integrated on a single chip semiconductor integrated circuit. In the pulse detector, an input stage of a gain variable amplifier, which amplifies an input signal applied thereto so as to have a constant peak, includes a bipolar transistor, and a pulse generator for generating a pulse shape signal according to a differential value of an output from the gain variable amplifier includes a Bi-CMOS gate or a CMOS gate. In the data separator, a voltage controlled oscillator for generating a clock signal includes a bipolar transistor. A frequency phase comparator for comparing the pulse shape signal in phases with the clock signal generated by the voltage controlled oscillator to obtain a phase difference, includes a Bi-CMOS gate and a CMOS gate.
摘要翻译：脉冲检测器和数据分离器集成在单芯片半导体集成电路上。在脉冲检测器中，增益可变放大器的输入级放大施加到其上的具有恒定峰值的输入信号，包括双极型晶体管和脉冲发生器，用于根据微分值产生脉冲形状信号来自增益可变放大器的输出包括Bi-CMOS栅极或CMOS栅极。在数据分离器中，用于产生时钟信号的压控振荡器包括双极晶体管。用于将脉冲形状信号与由压控振荡器产生的时钟信号进行比较以获得相位差的频率相位比较器包括Bi-CMOS栅极和CMOS栅极。

10. 发明授权

US5515068A One-chip semiconductor integrated circuit device capable of outputting analog color signal or digital color signal 失效
标题翻译：能够输出模拟彩色信号或数字彩色信号的单芯片半导体集成电路器件
公开(公告)号：US5515068A
公开(公告)日：1996-05-07
申请号：US300065
申请日：1994-09-02
申请人： Akira Uragami , Shinichi Kojima
发明人： Akira Uragami , Shinichi Kojima
IPC分类号： G09G5/04 , G06F1/32 , G06F3/14 , G09G3/36 , G09G5/00 , G09G5/06 , G09G5/36
CPC分类号： G09G5/06 , G09G5/366 , G06F3/1431
摘要： A semiconductor device (CPLT) of the invention comprises a first terminal (R) to which analog data is to be supplied, a digital/analog converter (DAC1) with its output coupled to the first terminal, a second terminal (R'0) to which digital data is to be supplied, a digital output circuit (DOB) with its output coupled to the second terminal, and a preparation means (PLM, SEL) which is coupled to respective inputs of the digital/analog converter and the digital output circuit, and prepares digital data to be processed (RR) for any one of input of the digital/analog converter and input of the digital output circuit.
摘要翻译：本发明的半导体器件（CPLT）包括：要向其提供模拟数据的第一端子（R），其输出耦合到第一端子的数模转换器（DAC1），第二端子（R'0）要向其提供数字数据的数字输出电路（DOB），其输出耦合到第二终端;以及准备装置（PLM，SEL），其耦合到数字/模拟转换器的相应输入端和数字输出端电路，并为数字/模拟转换器的输入和数字输出电路的输入中的任何一个准备待处理的数字数据（RR）。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式