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    • 5. 发明授权
    • Memory device having virtual ground line
    • 具有虚拟接地线的存储器件
    • US5650959A
    • 1997-07-22
    • US540473
    • 1995-10-10
    • Tetsuya HayashiAkira TakataKazuhiro Watanabe
    • Tetsuya HayashiAkira TakataKazuhiro Watanabe
    • G11C17/00G11C7/02G11C16/04G11C17/12G11C17/18G11C11/34
    • G11C17/126
    • This memory device includes a plurality of word lines, a plurality of bit lines, a plurality of virtual ground lines, memory cells arranged at the intersections between the word and bit lines, a potential setting unit for setting the potential of the virtual ground lines to a ground or bias level, and a sense amplifier for detecting storage information of a target memory cell through the bit line when the virtual ground line connected to the target memory cell is set to the ground level by the potential setting unit. To read out information from a memory cell Mij, a virtual ground line GLi connected to the electrode of this memory cell is set to the ground level, and the remaining virtual ground lines are connected to a common bias potential line set to the bias level.
    • 这种存储装置包括多个字线,多个位线,多个虚拟接地线,布置在字和位线之间的交叉处的存储器单元,用于将虚拟接地线的电位设置为 接地或偏置电平;以及读出放大器,用于当通过电位设定单元将连接到目标存储单元的虚拟地线设置为地电平时,通过位线检测目标存储单元的存储信息。 为了从存储单元Mij读取信息,将连接到该存储单元的电极的虚拟接地线GLi设置为接地电平,并且剩余的虚拟接地线连接到设置为偏置电平的公共偏置电位线。
    • 6. 发明授权
    • Programmable logic device having plural programmable function cells
    • 具有多个可编程功能单元的可编程逻辑器件
    • US4763020A
    • 1988-08-09
    • US903781
    • 1986-09-04
    • Akira TakataKoichi Fujii
    • Akira TakataKoichi Fujii
    • A23G9/04A23G9/20A47J43/046F25C5/12G01R31/3185H03K19/177
    • A23G9/045A23G9/20F25C5/12G01R31/318516H03K19/17712
    • A programmable logic device includes an AND plane and an OR plane associated with the AND plane. At least one of the AND and OR planes includes an array of programmable memory elements which can be selectively programmed to define a desired logic function. In one form, a function cell designed for providing one of a predetermined functions, such as a counter or shift register function, selectively is provided. In another form, a driver circuit connected to a pair of input lines has a first state in which one of the paired input lines serves as an inverting input line and the other as a non-inverting input line and a second state in which both of the paired input lines are set at low level. In a further form, two pairs of input lines of the AND plane are connected to an input or input/output terminal of the device. In a still further form, the AND plane further includes a plurality of test input lines each associated with the corresponding one of the product term lines of the AND plane, and an three-state output buffer is connected between the OR plane and a device output terminal, whereby the output buffer is enabled by a logical sum between a selected product term from the AND plane and an internally supplied test mode signal.
    • 可编程逻辑器件包括AND平面和与AND平面相关联的OR平面。 AND和OR平面中的至少一个包括可编程存储器元件的阵列,其可以被选择性地编程以定义期望的逻辑功能。 在一种形式中,提供了用于选择性地提供诸如计数器或移位寄存器功能之类的预定功能之一的功能单元。 在另一种形式中,连接到一对输入线的驱动器电路具有第一状态,其中一对输入线中的一个用作反相输入线,而另一个用作非反相输入线,而第二状态 成对的输入线设置为低电平。 在另一种形式中,AND平面的两对输入线连接到设备的输入或输入/输出端子。 在另一种形式中,AND平面还包括多个测试输入线,每条测试输入线与AND平面的相应一个乘积项相关联,三态输出缓冲器连接在OR平面和器件输出 终端,由此通过来自AND平面的所选择的产品项和内部提供的测试模式信号之间的逻辑和启用输出缓冲器。