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1. 发明授权

US08404133B2 Manufacturing method of planar optical waveguide device with grating structure 有权
标题翻译：具有光栅结构的平面光波导器件的制造方法
公开(公告)号：US08404133B2
公开(公告)日：2013-03-26
申请号：US12547115
申请日：2009-08-25
申请人： Ken Sakuma , Kensuke Ogawa , Kazuhiro Goi , Yong Tsong Tan , Ning Guan , Mingbin Yu , Hwee Gee Teo , Guo-Qiang Lo
发明人： Ken Sakuma , Kensuke Ogawa , Kazuhiro Goi , Yong Tsong Tan , Ning Guan , Mingbin Yu , Hwee Gee Teo , Guo-Qiang Lo
IPC分类号： C03C15/00
CPC分类号： G02B6/124
摘要： A method for manufacturing a planar optical waveguide device of which a core includes a plurality of alternatively arranged fin portions and valley portions to form a grating structure, in which the core widths of the valley portions vary along the longitudinal direction, the method including: a high refractive index material layer forming step of forming a high refractive index material layer; a photoresist layer forming step of forming a photoresist layer on the high refractive index material layer; a first exposure step of forming shaded portions on the photoresist layer using a phase-shifting photomask; a second exposure step of forming shaded portions on the photoresist layer using a binary photomask; a development step of developing the photoresist layer; and an etching step of etching the high refractive index material layer using the photoresist pattern resulted from the development step.
摘要翻译：一种平面光波导装置的制造方法，其特征在于，芯体具有多个交替设置的翅片部和谷部，以形成其中谷部的芯宽沿纵向变化的格栅结构，该方法包括：形成高折射率材料层的高折射率材料层形成步骤; 在高折射率材料层上形成光致抗蚀剂层的光致抗蚀剂层形成步骤; 使用相移光掩模在光致抗蚀剂层上形成阴影部分的第一曝光步骤; 第二曝光步骤，使用二元光掩模在所述光致抗蚀剂层上形成阴影部分; 显影光致抗蚀剂层的显影步骤; 以及使用由显影步骤产生的光致抗蚀剂图案来蚀刻高折射率材料层的蚀刻步骤。

2. 发明申请

US20110049735A1 MANUFACTURING METHOD OF PLANAR OPTICAL WAVEGUIDE DEVICE WITH GRATING STRUCTURE 有权
标题翻译：具有光栅结构的平面光波导器件的制造方法
公开(公告)号：US20110049735A1
公开(公告)日：2011-03-03
申请号：US12547115
申请日：2009-08-25
申请人： Ken Sakuma , Kensuke Ogawa , Kazuhiro Goi , Yong Tsong Tan , Ning Guan , Mingbin Yu , Hwee Gee Teo , Guo-Qiang Lo
发明人： Ken Sakuma , Kensuke Ogawa , Kazuhiro Goi , Yong Tsong Tan , Ning Guan , Mingbin Yu , Hwee Gee Teo , Guo-Qiang Lo
IPC分类号： G02B6/10
CPC分类号： G02B6/124
摘要： A method for manufacturing a planar optical waveguide device of which a core includes a plurality of alternatively arranged fin portions and valley portions to form a grating structure, in which the core widths of the valley portions vary along the longitudinal direction, the method including: a high refractive index material layer forming step of forming a high refractive index material layer; a photoresist layer forming step of forming a photoresist layer on the high refractive index material layer; a first exposure step of forming shaded portions on the photoresist layer using a phase-shifting photomask; a second exposure step of forming shaded portions on the photoresist layer using a binary photomask; a development step of developing the photoresist layer; and an etching step of etching the high refractive index material layer using the photoresist pattern resulted from the development step.
摘要翻译：一种平面光波导装置的制造方法，其特征在于，芯体具有多个交替设置的翅片部和谷部，以形成其中谷部的芯宽沿纵向变化的格栅结构，该方法包括：形成高折射率材料层的高折射率材料层形成步骤; 在高折射率材料层上形成光致抗蚀剂层的光致抗蚀剂层形成步骤; 使用相移光掩模在光致抗蚀剂层上形成阴影部分的第一曝光步骤; 第二曝光步骤，使用二元光掩模在所述光致抗蚀剂层上形成阴影部分; 显影光致抗蚀剂层的显影步骤; 以及使用由显影步骤产生的光致抗蚀剂图案来蚀刻高折射率材料层的蚀刻步骤。

3. 发明授权

US08227178B2 Manufacturing method of planar optical waveguide device with grating structure 有权
标题翻译：具有光栅结构的平面光波导器件的制造方法
公开(公告)号：US08227178B2
公开(公告)日：2012-07-24
申请号：US12547146
申请日：2009-08-25
申请人： Ken Sakuma , Kensuke Ogawa , Kazuhiro Goi , Yong Tsong Tan , Ning Guan , Mingbin Yu , Hwee Gee Teo , Guo-Qiang Lo
发明人： Ken Sakuma , Kensuke Ogawa , Kazuhiro Goi , Yong Tsong Tan , Ning Guan , Mingbin Yu , Hwee Gee Teo , Guo-Qiang Lo
IPC分类号： G03F7/20
CPC分类号： G02B6/124 , G02B6/132 , G02B6/136
摘要： A method for manufacturing a planar optical waveguide device including a core of which a top face is provided with a groove section filled with a groove section filler made of a low refractive index material having a refractive index lower than that of the core, the method including; a first high refractive index material layer forming step of forming a high refractive index material layer; a low refractive index material layer forming step of forming a low refractive index material layer made of the low refractive index material on the high refractive index material layer; a groove section filler forming step of forming the groove section filler by trimming both lateral portions of the low refractive index material layer; and a second high refractive index material layer forming step of forming a high refractive index material layer so as to fill the both sides of the lateral portions of the groove section filler.
摘要翻译：一种平面光波导器件的制造方法，其特征在于，具有芯部，其上表面设置有填充有折射率低于芯的低折射率材料的槽部填充物的槽部，该方法包括 ; 形成高折射率材料层的第一高折射率材料层形成步骤; 低折射率材料层形成步骤，在所述高折射率材料层上形成由所述低折射率材料制成的低折射率材料层; 槽部填料形成工序，通过对所述低折射率材料层的两个侧面进行修整而形成所述槽部填料; 以及形成高折射率材料层的第二高折射率材料层形成步骤，以便填充槽部填料的侧部的两侧。

4. 发明申请

US20100052064A1 METHOD FOR STRAINING A SEMICONDUCTOR WAFER AND A WAFER SUBSTRATE UNIT USED THEREIN 审中-公开
标题翻译：用于应变半导体波长的方法和使用它的波导衬底单元
公开(公告)号：US20100052064A1
公开(公告)日：2010-03-04
申请号：US12373881
申请日：2006-07-20
申请人： Guo-Qiang Lo , Lakshmi Kanta Bera , Li-Hui Guo , Wei-Yip Loh , Ebin Liao , Xiaowu Zhang
发明人： Guo-Qiang Lo , Lakshmi Kanta Bera , Li-Hui Guo , Wei-Yip Loh , Ebin Liao , Xiaowu Zhang
IPC分类号： H01L27/092 , H01L21/50
CPC分类号： H01L21/324 , H01L21/823807 , H01L29/6659 , H01L29/7842
摘要： The present invention provides a method for straining a semiconductor wafer, the method comprising: providing a semiconductor wafer, the semiconductor wafer having a first wafer surface and a second wafer surface arranged substantially opposite the first wafer surface; providing a substrate, the substrate having a substrate surface; adhering the first wafer surface to the substrate surface, thereby connecting the semiconductor wafer to the substrate and forming a wafer substrate unit; heating the semiconductor wafer and the substrate to a first temperature; and cooling the wafer substrate unit to a second temperature lower than the first temperature; thereby straining and bending the semiconductor wafer. The present invention further provides a wafer substrate unit.
摘要翻译：本发明提供了一种使半导体晶片变形的方法，所述方法包括：提供半导体晶片，所述半导体晶片具有第一晶片表面和与所述第一晶片表面基本相对的第二晶片表面; 提供衬底，所述衬底具有衬底表面; 将第一晶片表面粘合到基板表面，从而将半导体晶片连接到基板并形成晶片基板单元; 将半导体晶片和衬底加热到第一温度; 以及将所述晶片衬底单元冷却到低于所述第一温度的第二温度; 从而使半导体晶片变形和弯曲。本发明还提供了一种晶片衬底单元。

5. 发明授权

US07176104B1 Method for forming shallow trench isolation structure with deep oxide region 有权
标题翻译：用于形成具有深氧化物区域的浅沟槽隔离结构的方法
公开(公告)号：US07176104B1
公开(公告)日：2007-02-13
申请号：US10863540
申请日：2004-06-08
申请人： Chih-Hsiang Chen , Guo-Qiang Lo
发明人： Chih-Hsiang Chen , Guo-Qiang Lo
IPC分类号： H01L21/76 , H01L21/336
CPC分类号： H01L21/76235 , H01L21/26506 , H01L21/76205
摘要： The present invention relates to a shallow trench isolation structure and a method for forming a shallow trench isolation structure on a semiconductor substrate. A masking structure that includes a hard mask is formed over the semiconductor substrate and an etch is performed so as to form trenches within the semiconductor substrate. A shallow trench isolation structure and a method for forming a shallow trench isolation structure are disclosed. Oxidation enhancing species are then implanted into the bottom surface of the trenches and an oxidation process is performed. The oxidation enhancing species will form a deep oxidation region below the bottom surface of each trench and will form thinner oxidation regions within side surfaces of trenches. A layer of dielectric material is then deposited to fill the trenches. A chemical mechanical polishing process is performed to remove those portions of the dielectric film that overlie the hard mask. The hard mask is then removed, producing a void-free shallow trench isolation structure.
摘要翻译：本发明涉及浅沟槽隔离结构和在半导体衬底上形成浅沟槽隔离结构的方法。在半导体衬底上形成包括硬掩模的掩模结构，并进行蚀刻以在半导体衬底内形成沟槽。公开了浅沟槽隔离结构和形成浅沟槽隔离结构的方法。然后将氧化增强物质注入到沟槽的底表面中，并进行氧化过程。氧化增强物质将在每个沟槽的底表面下方形成深氧化区域，并且在沟槽的侧表面内形成更薄的氧化区域。然后沉积介电材料层以填充沟槽。执行化学机械抛光工艺以去除覆盖在硬掩模上的介电膜的那些部分。然后去除硬掩模，产生无空隙的浅沟槽隔离结构。

6. 发明授权

US07214990B1 Memory cell with reduced soft error rate 有权
标题翻译：具有降低的软错误率的存储单元
公开(公告)号：US07214990B1
公开(公告)日：2007-05-08
申请号：US11063704
申请日：2005-02-22
申请人： Shih-Ked Lee , Chuen-Der Lien , Louis Huang , Gaolong Jin , Wanqing Cao , Guo-Qiang Lo
发明人： Shih-Ked Lee , Chuen-Der Lien , Louis Huang , Gaolong Jin , Wanqing Cao , Guo-Qiang Lo
IPC分类号： H01L27/11
CPC分类号： H01L28/24 , H01L27/016 , H01L27/0802 , H01L29/78
摘要： The present invention includes SRAM memory cells and methods for forming SRAM cells having reduced soft error rate. The SRAM cell includes a first NMOS transistor and a first PMOS transistor having a common gate, and a second NMOS transistor and a second PMOS transistor having a common gate. A first resistor is electrically coupled on one end to the drains of the first PMOS transistor and the first NMOS transistor; and is electrically coupled on the other end to the common gate of the second NMOS and second PMOS transistors. A second resistor is electrically coupled on one end to the drains of the second PMOS transistor and the second NMOS transistor; and is electrically coupled on the other end to the common gate of the first NMOS transistor and the first PMOS transistor. The added resistor can be embedded in a contact opening such that it does not take up valuable surface area on the semiconductor substrate. Thereby, data loss from soft errors can be avoided while preserving small memory cell size.
摘要翻译：本发明包括SRAM存储单元和用于形成具有降低的软错误率的SRAM单元的方法。 SRAM单元包括第一NMOS晶体管和具有公共栅极的第一PMOS晶体管，以及具有公共栅极的第二NMOS晶体管和第二PMOS晶体管。第一电阻器的一端电耦合到第一PMOS晶体管和第一NMOS晶体管的漏极; 并且在另一端电耦合到第二NMOS和第二PMOS晶体管的公共栅极。第二电阻器的一端电耦合到第二PMOS晶体管和第二NMOS晶体管的漏极; 并且在另一端电耦合到第一NMOS晶体管和第一PMOS晶体管的公共栅极。添加的电阻器可以嵌入在接触开口中，使得其不占据半导体衬底上的有价值的表面积。因此，可以避免从软错误的数据丢失，同时保持小的存储单元尺寸。

7. 发明授权

US07375392B1 Gate structures having sidewall spacers formed using selective deposition 有权
标题翻译：具有使用选择性沉积形成的侧壁间隔物的栅极结
公开(公告)号：US07375392B1
公开(公告)日：2008-05-20
申请号：US11395818
申请日：2006-03-30
申请人： Chih-Hsiang Chen , Guo-Qiang Lo , Shih-Ked Lee
发明人： Chih-Hsiang Chen , Guo-Qiang Lo , Shih-Ked Lee
IPC分类号： H01L29/76
CPC分类号： H01L21/76897 , H01L29/6656 , H01L29/78 , Y10S257/90
摘要： Sidewall spacers are disclosed that extend on opposing sidewalls of gate stacks. The sidewall spacers have improved profiles to suppress or eliminate void formation between the gate stacks during gap-filling A gate dielectric layer is formed on a semiconductor substrate. Then, a gate stack 24 having a sidewall is formed over the gate dielectric layer. The gate stack 24 comprises a conductive layer 28 and a hard mask 30 overlying the conductive layer 28. A liner 32 is selectively deposited over the gate stack 24 such that the liner 32 is deposited on the hard mask 30 at a rate lower than the rate of deposition on the conductive layer 28. Thus, the liner 32 is substantially thinner on the hard mask 30 than on the conductive layer 28. A nitride spacer is formed over 34 the liner 32. A PMD layer is formed over the resultant structure, filling the gaps between adjacent gate stacks.
摘要翻译：公开了在门堆叠的相对侧壁上延伸的侧壁间隔物。在间隙填充期间，侧壁间隔物具有改进的轮廓以抑制或消除栅极堆叠之间的空隙形成在半导体衬底上形成栅极介电层。然后，在栅介质层上形成具有侧壁的栅极叠层24。栅极堆叠24包括导电层28和覆盖导电层28的硬掩模30。衬套32选择性地沉积在栅极堆叠24上，使得衬垫32以低于导电层28上的沉积速率的速率沉积在硬掩模30上。因此，衬垫32在硬掩模30上比在导电层28上显着更薄。在衬垫32上形成氮化物衬垫34。在所得结构上形成PMD层，填充相邻栅极堆叠之间的间隙。

8. 发明授权

US07129149B1 Method for forming shallow trench isolation structure with anti-reflective liner 失效
标题翻译：用抗反射衬垫形成浅沟槽隔离结构的方法
公开(公告)号：US07129149B1
公开(公告)日：2006-10-31
申请号：US10862520
申请日：2004-06-07
申请人： Chih-Hsiang Chen , Yiming Gu , Guo-Qiang Lo
发明人： Chih-Hsiang Chen , Yiming Gu , Guo-Qiang Lo
IPC分类号： H01L21/76 , H01L21/336
CPC分类号： H01L21/76224
摘要： The present invention relates to a shallow trench isolation structure and a method for forming a shallow trench isolation structure on a semiconductor substrate. A masking structure that includes a hard mask is formed over the semiconductor substrate, and an etch is performed so as to form trenches within the semiconductor substrate. An anti-reflective film is deposited such that it extends within the trench. A dielectric film is deposited over the anti-reflective film such that it fills the trench. A heating process step is then performed to anneal the substrate, rounding the corners of the trench. A chemical mechanical polishing process is performed to remove those portions of the anti-reflective film and the dielectric film that overlie the hard mask. The hard mask is then removed, producing a shallow trench isolation structure that prevents lifting and notching in subsequent fabrication steps.
摘要翻译：本发明涉及浅沟槽隔离结构和在半导体衬底上形成浅沟槽隔离结构的方法。在半导体衬底上形成包括硬掩模的掩模结构，并且进行蚀刻以在半导体衬底内形成沟槽。沉积防反射膜使得其在沟槽内延伸。电介质膜沉积在抗反射膜上，使得其填充沟槽。然后进行加热工艺步骤以使衬底退火，使沟槽的角落四舍五入。执行化学机械抛光工艺以去除覆盖在硬掩模上的抗反射膜和电介质膜的那些部分。然后去除硬掩模，产生浅沟槽隔离结构，其在随后的制造步骤中防止提起和开槽。

9. 发明授权

US07125783B2 Dielectric anti-reflective coating surface treatment to prevent defect generation in associated wet clean 有权
公开(公告)号：US07125783B2
公开(公告)日：2006-10-24
申请号：US09838084
申请日：2001-04-18
申请人： Guo-Qiang Lo , Ohm-Guo Pan , Zhenjiang Yu , Yu-Lung Mao , Tsengyou Syau , Shih-Ked Lee
发明人： Guo-Qiang Lo , Ohm-Guo Pan , Zhenjiang Yu , Yu-Lung Mao , Tsengyou Syau , Shih-Ked Lee
IPC分类号： H01L21/762
CPC分类号： H01L21/0276 , H01L21/02052 , H01L21/31111 , H01L21/3143 , H01L21/76235 , H01L21/76814 , H01L21/76829 , Y10S438/906 , Y10S438/952
摘要： A method for preventing the formation of watermark defects includes the steps of forming a pad oxide, a silicon nitride layer and a silicon oxynitride layer over a semiconductor substrate. A photoresist mask is formed over the resulting structure, with the silicon oxynitride layer being used as an anti-reflective coating during exposure of the photoresist material. An etch is performed through the photoresist mask, thereby forming a trench in the substrate. The photoresist mask is stripped, and the silicon oxynitride layer is conditioned. For example, the silicon oxynitride layer may be conditioned by a rapid thermal anneal in the presence of oxygen or nitrogen. A wet clean step is subsequently performed to remove a native oxide layer in the trench. The conditioned silicon oxynitride layer prevents the formation of watermarks during the wet clean process.

10. 发明授权

US06281102B1 Cobalt silicide structure for improving gate oxide integrity and method for fabricating same 失效
标题翻译：用于提高栅极氧化物完整性的硅化钴结构及其制造方法
公开(公告)号：US06281102B1
公开(公告)日：2001-08-28
申请号：US09484580
申请日：2000-01-13
申请人： Wanqing Cao , Sang-Yun Lee , Guo-Qiang Lo , Shih-Ked Lee
发明人： Wanqing Cao , Sang-Yun Lee , Guo-Qiang Lo , Shih-Ked Lee
IPC分类号： H01L213205
CPC分类号： H01L29/665 , H01L21/28518
摘要： An improved method is provided for fabricating a cobalt silicide structure that includes the steps of: (1) forming a silicon structure, wherein a native oxide is located over a first surface of the silicon structure, (2) loading the silicon structure into a chamber, (3) introducing a vacuum to the chamber, (4) depositing a titanium layer over the first surface of the silicon structure, wherein the thickness of the titanium layer is selected to remove substantially all of the native oxide, (5) depositing a cobalt layer over the titanium layer, (6) depositing an oxygen impervious cap layer over the cobalt layer; and then (7) breaking the vacuum in the chamber, and (8) subjecting the silicon structure, the titanium layer, the cobalt layer and the cap layer to an anneal, thereby forming the cobalt silicide structure. The cap layer can be, for example, titanium or titanium nitride. The resulting cobalt silicide structure is substantially free from oxygen (i.e., oxide). Consequently, an underlying gate oxide or substrate is advantageously protected from the effects of cobalt silicide spiking.
摘要翻译：提供了一种用于制造钴硅化物结构的改进方法，其包括以下步骤：（1）形成硅结构，其中自然氧化物位于硅结构的第一表面上，（2）将硅结构加载到室中（3）向腔室引入真空，（4）在硅结构的第一表面上沉积钛层，其中选择钛层的厚度以去除基本上所有的天然氧化物，（5）沉积钴层，（6）在钴层上沉积不透氧的盖层; 然后（7）破坏腔室中的真空，（8）对硅结构，钛层，钴层和盖层进行退火，从而形成钴硅化物结构。盖层可以是例如钛或氮化钛。所得的钴硅化物结构基本上不含氧（即氧化物）。因此，有利地保护下面的栅极氧化物或衬底免受硅化钴尖峰的影响。

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