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1. 发明授权

US07129149B1 Method for forming shallow trench isolation structure with anti-reflective liner 失效
标题翻译：用抗反射衬垫形成浅沟槽隔离结构的方法
公开(公告)号：US07129149B1
公开(公告)日：2006-10-31
申请号：US10862520
申请日：2004-06-07
申请人： Chih-Hsiang Chen , Yiming Gu , Guo-Qiang Lo
发明人： Chih-Hsiang Chen , Yiming Gu , Guo-Qiang Lo
IPC分类号： H01L21/76 , H01L21/336
CPC分类号： H01L21/76224
摘要： The present invention relates to a shallow trench isolation structure and a method for forming a shallow trench isolation structure on a semiconductor substrate. A masking structure that includes a hard mask is formed over the semiconductor substrate, and an etch is performed so as to form trenches within the semiconductor substrate. An anti-reflective film is deposited such that it extends within the trench. A dielectric film is deposited over the anti-reflective film such that it fills the trench. A heating process step is then performed to anneal the substrate, rounding the corners of the trench. A chemical mechanical polishing process is performed to remove those portions of the anti-reflective film and the dielectric film that overlie the hard mask. The hard mask is then removed, producing a shallow trench isolation structure that prevents lifting and notching in subsequent fabrication steps.
摘要翻译：本发明涉及浅沟槽隔离结构和在半导体衬底上形成浅沟槽隔离结构的方法。在半导体衬底上形成包括硬掩模的掩模结构，并且进行蚀刻以在半导体衬底内形成沟槽。沉积防反射膜使得其在沟槽内延伸。电介质膜沉积在抗反射膜上，使得其填充沟槽。然后进行加热工艺步骤以使衬底退火，使沟槽的角落四舍五入。执行化学机械抛光工艺以去除覆盖在硬掩模上的抗反射膜和电介质膜的那些部分。然后去除硬掩模，产生浅沟槽隔离结构，其在随后的制造步骤中防止提起和开槽。

2. 发明授权

US09421567B2 Recycle photochemical to reduce cost of material and environmental impact 有权
标题翻译：回收光化学物质，降低材料成本和环境影响
公开(公告)号：US09421567B2
公开(公告)日：2016-08-23
申请号：US14480080
申请日：2014-09-08
申请人： Winston Wu , Yiming Gu
发明人： Winston Wu , Yiming Gu
IPC分类号： B05B15/04 , H01L21/02 , H01L21/027
CPC分类号： B05B14/00 , B05B13/0242 , H01L21/02079 , H01L21/02087 , H01L21/02118 , H01L21/0271 , H01L21/6715 , Y02P70/36
摘要： This invention discloses an apparatus for coating a semiconductor wafer in a coating chamber comprising a platform for placing the semiconductor wafer thereon. The apparatus further includes a catch and recycle (C&R) apparatus comprises a rim/ring controllable to move below and surround the platform for receiving and catching a coating material spurned off in coating the semiconductor wafer.
摘要翻译：本发明公开了一种用于在涂覆室中涂覆半导体晶片的装置，包括用于将半导体晶片放置在其上的平台。该装置还包括捕获和再循环（C＆R）装置，其包括可控制以在平台下方并围绕平台的边缘/环，用于接收和捕获在涂覆半导体晶片时被抛弃的涂层材料。

3. 发明授权

US08982314B2 Photolithographic apparatus 有权
标题翻译：光刻设备
公开(公告)号：US08982314B2
公开(公告)日：2015-03-17
申请号：US13405238
申请日：2012-02-25
申请人： Qiang Wu , Yiming Gu
发明人： Qiang Wu , Yiming Gu
IPC分类号： G03B27/32 , G03F7/20
CPC分类号： G03F7/70575 , G03F7/203 , G03F7/70466
摘要： A photolithographic apparatus for use with a photo-resist comprises a first component that generates a first chemical substance and produces a chemical amplification action and a second component that generates a second chemical substance. The photolithographic apparatus comprises a first exposure subsystem for selectively illuminating a surface of the photo-resist using a light of a first wavelength band such that the first component generates the first chemical substance and a second exposure subsystem for uniformly illuminating the surface using a light of a second wavelength band such that the second component generates the second chemical substance. The second chemical substance reacts with the first chemical substance to reduce the mass concentration of the first chemical substance in the photo-resist and improves the contrast of a latent image of the first chemical substance formed in the photo-resist.
摘要翻译：用于光刻胶的光刻设备包括产生第一化学物质并产生化学放大作用的第一组分和产生第二化学物质的第二组分。光刻设备包括：第一曝光子系统，用于使用第一波长带的光选择性地照射光刻胶的表面，使得第一成分产生第一化学物质;以及第二曝光子系统，用于使用第二波长带，使得第二组分产生第二化学物质。第二化学物质与第一化学物质反应以降低光致抗蚀剂中的第一化学物质的质量浓度并且改善形成在光致抗蚀剂中的第一化学物质的潜像的对比度。

4. 发明授权

US08304317B2 Gate line edge roughness reduction by using 2P/2E process together with high temperature bake 有权
标题翻译：通过使用2P / 2E工艺与高温烘烤进行栅极边缘粗糙度降低
公开(公告)号：US08304317B2
公开(公告)日：2012-11-06
申请号：US12648802
申请日：2009-12-29
申请人： Yiming Gu , James Walter Blatchford
发明人： Yiming Gu , James Walter Blatchford
IPC分类号： H01L21/8324
CPC分类号： H01L21/28123 , H01L21/32139
摘要： A method of patterning a plurality of polysilicon structures includes forming a polysilicon layer over a semiconductor body, and patterning the polysilicon layer to form a first polysilicon structure using a first patterning process that reduces line-edge roughness (LER). The method further includes patterning the polysilicon layer to form a second polysilicon structure using a second patterning process that is different from the first patterning process after performing the first patterning process.
摘要翻译：图案化多个多晶硅结构的方法包括在半导体本体上形成多晶硅层，并使用减少线边缘粗糙度（LER）的第一图案化工艺来图案化多晶硅层以形成第一多晶硅结构。该方法还包括使用在执行第一图案化工艺之后与第一图案化工艺不同的第二图案化工艺来图案化多晶硅层以形成第二多晶硅结构。

5. 发明申请

US20160067729A1 RECYCLE PHOTOCHEMICAL TO REDUCE COST OF MATERIAL AND ENVIRONMENTAL IMPACT 审中-公开
标题翻译：循环光化学降低材料成本和环境影响
公开(公告)号：US20160067729A1
公开(公告)日：2016-03-10
申请号：US14480080
申请日：2014-09-08
申请人： Winston Wu , Yiming Gu
发明人： Winston Wu , Yiming Gu
IPC分类号： B05B15/04 , H01L21/027 , H01L21/02
CPC分类号： B05B14/00 , B05B13/0242 , H01L21/02079 , H01L21/02087 , H01L21/02118 , H01L21/0271 , H01L21/6715 , Y02P70/36
摘要： This invention discloses an apparatus for coating a semiconductor wafer in a coating chamber comprising a platform for placing the semiconductor wafer thereon. The apparatus further includes a catch and recycle (C&R) apparatus comprises a rim/ring controllable to move below and surround the platform for receiving and catching a coating material spurned off in coating the semiconductor wafer.
摘要翻译：本发明公开了一种用于在涂覆室中涂覆半导体晶片的装置，包括用于将半导体晶片放置在其上的平台。该装置还包括捕获和再循环（C＆R）装置，其包括可控制以在平台下方并围绕平台的边缘/环，用于接收和捕获在涂覆半导体晶片时被抛弃的涂层材料。

6. 发明授权

US07235336B1 Method for determining photoresist thickness and structure formed using determined photoresist thickness 有权
标题翻译：确定光致抗蚀剂厚度和使用确定的光致抗蚀剂厚度形成的结构的方法
公开(公告)号：US07235336B1
公开(公告)日：2007-06-26
申请号：US10808806
申请日：2004-03-25
申请人： Yiming Gu
发明人： Yiming Gu
IPC分类号： G03C5/00
CPC分类号： G03F7/168 , G03F7/30 , G03F7/3028
摘要： A method for determining photoresist thickness is disclosed that can be used in a semiconductor fabrication process. A layer of material is formed that has one or more common characteristic relative to the material in the layer that is to be patterned in the semiconductor fabrication process. A layer of photoresist is then formed that has varying thickness. The thickness of the layer of photoresist is determined at a plurality of different points. The layer of photoresist is exposed, developed and etched. The remaining structures are then analyzed to determine photoresist thickness to be used in the semiconductor fabrication process. The determined photoresist thickness is then used in the semiconductor fabrication process to form structures on a semiconductor wafer.
摘要翻译：公开了一种用于确定光致抗蚀剂厚度的方法，可用于半导体制造工艺。形成一层材料，其相对于在半导体制造工艺中待图案化的层中的材料具有一个或多个共同特性。然后形成具有变化的厚度的光致抗蚀剂层。在多个不同点确定光致抗蚀剂层的厚度。光致抗蚀剂层被曝光，显影和蚀刻。然后分析剩余的结构以确定在半导体制造工艺中使用的光致抗蚀剂厚度。然后将所确定的光致抗蚀剂厚度用于半导体制造工艺中以在半导体晶片上形成结构。

7. 发明授权

US06733936B1 Method for generating a swing curve and photoresist feature formed using swing curve 有权
标题翻译：使用摆动曲线形成摆动曲线和光刻胶特征的方法
公开(公告)号：US06733936B1
公开(公告)日：2004-05-11
申请号：US10247877
申请日：2002-09-19
申请人： Yiming Gu , John L. Sturtevant
发明人： Yiming Gu , John L. Sturtevant
IPC分类号： G03C500
CPC分类号： G03F7/168 , G03F7/30 , G03F7/3028
摘要： A method for generating a swing curve and a photoresist feature formed using the swing curve. A layer of photoresist is formed that has varying thickness. The thickness of the layer of photoresist is determined at a plurality of points. The semiconductor wafer is then exposed and developed to form a photoresist structure that includes features. For each of the points at which thickness was determined, the size of a corresponding feature is determined. A curve is then determined that correlates the thickness measurements and the size measurements. The resulting swing curve is then used to determine a thickness for photoresist deposition and a photoresist layer is deposited, exposed, and developed to obtain a photoresist feature having the desired size.
摘要翻译：使用摆动曲线形成摆动曲线和光致抗蚀剂特征的方法。形成具有不同厚度的光致抗蚀剂层。在多个点处确定光致抗蚀剂层的厚度。然后将半导体晶片曝光和显影以形成包括特征的光致抗蚀剂结构。对于确定厚度的每个点，确定相应特征的尺寸。然后确定将厚度测量和尺寸测量相关联的曲线。然后将所得的摆动曲线用于确定光致抗蚀剂沉积的厚度，并且沉积，曝光和显影光致抗蚀剂层以获得具有所需尺寸的光致抗蚀剂特征。

8. 发明申请

US20100167484A1 Gate line edge roughness reduction by using 2P/2E process together with high temperature bake 有权
标题翻译：通过使用2P / 2E工艺与高温烘烤进行栅极边缘粗糙度降低
公开(公告)号：US20100167484A1
公开(公告)日：2010-07-01
申请号：US12648802
申请日：2009-12-29
申请人： Yiming Gu , James Walter Blatchford
发明人： Yiming Gu , James Walter Blatchford
IPC分类号： H01L21/8234 , H01L21/28 , H01L21/3205 , G03F7/20
CPC分类号： H01L21/28123 , H01L21/32139
摘要： A method of patterning a plurality of polysilicon structures includes forming a polysilicon layer over a semiconductor body, and patterning the polysilicon layer to form a first polysilicon structure using a first patterning process that reduces line-edge roughness (LER). The method further includes patterning the polysilicon layer to form a second polysilicon structure using a second patterning process that is different from the first patterning process after performing the first patterning process.
摘要翻译：图案化多个多晶硅结构的方法包括在半导体本体上形成多晶硅层，并使用减少线边缘粗糙度（LER）的第一图案化工艺来图案化多晶硅层以形成第一多晶硅结构。该方法还包括使用在执行第一图案化工艺之后与第一图案化工艺不同的第二图案化工艺来图案化多晶硅层以形成第二多晶硅结构。

9. 发明申请

US20100167472A1 IMPLANTATION SHADOWING EFFECT REDUCTION USING THERMAL BAKE PROCESS 审中-公开
标题翻译：使用热烘烤工艺减少影响的植入
公开(公告)号：US20100167472A1
公开(公告)日：2010-07-01
申请号：US12646479
申请日：2009-12-23
申请人： Yiming Gu , Shaofeng Yu , James Blatchford
发明人： Yiming Gu , Shaofeng Yu , James Blatchford
IPC分类号： H01L21/335 , G03F7/20
CPC分类号： H01L21/26586 , G03F7/40 , H01L29/6659
摘要： A method of forming a resist feature includes forming a resist layer over a semiconductor body, and selectively exposing the resist layer. The method further includes performing a first bake of the selectively exposed resist layer, and developing the selectively exposed resist layer to form a resist feature having a corner edge associated therewith, thereby exposing a portion of the semiconductor body. A second bake of the developed selectively exposed resist layer is then performed, thereby rounding the corner edge of the resist feature.
摘要翻译：形成抗蚀剂特征的方法包括在半导体本体上形成抗蚀剂层，并且选择性地暴露抗蚀剂层。该方法还包括执行选择性曝光的抗蚀剂层的第一烘烤，以及使选择性曝光的抗蚀剂层显影以形成具有与其相关联的角边缘的抗蚀剂特征，从而暴露半导体本体的一部分。然后进行显影的选择性曝光的抗蚀剂层的第二次烘烤，从而使抗蚀剂特征的拐角边缘四舍五入。

10. 发明申请

US20080248640A1 Method for reducing polysilicon gate defects in semiconductor devices 审中-公开
标题翻译：减少半导体器件中多晶硅栅极缺陷的方法
公开(公告)号：US20080248640A1
公开(公告)日：2008-10-09
申请号：US11732969
申请日：2007-04-05
申请人： Yiming Gu , Gary Zhang , Craig Hall
发明人： Yiming Gu , Gary Zhang , Craig Hall
IPC分类号： H01L21/3205
CPC分类号： H01L21/28123 , H01L21/28035 , H01L21/32139
摘要： Semiconductor devices and fabrication methods are provided, in which gate defects associated with photoresist stress after plasma trim/etch are substantially reduced. The method comprises forming a gate dielectric layer above a semiconductor body substrate; coating the gate dielectric layer with a photoresist coating; exposing and developing the photoresist coating; performing a resist annealing; and trimming and etching the photoresist coating.
摘要翻译：提供了半导体器件和制造方法，其中与等离子体修整/蚀刻之后的光致抗蚀剂应力相关的栅极缺陷显着降低。该方法包括在半导体本体基板上形成栅极电介质层; 用光致抗蚀剂涂层涂覆栅介质层; 曝光和显影光刻胶涂层; 进行抗蚀剂退火; 并修整和蚀刻光刻胶涂层。

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