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1. 发明授权

US5140684A Access privilege-checking apparatus and method 失效
标题翻译：访问权限检查装置和方法
公开(公告)号：US5140684A
公开(公告)日：1992-08-18
申请号：US663282
申请日：1991-02-28
申请人： Ken Sakamura , Toyohiko Yoshida
发明人： Ken Sakamura , Toyohiko Yoshida
IPC分类号： G06F12/14
CPC分类号： G06F12/1491
摘要： The data processor related to the invention accesses memory with an address value which is expressed by signed binary notation expressed by twos compliment, is so constructed that the negative address value having maximum absolute value and the positive address value having the same are not wrapped around each other, is provided with hardware which signed extends the address values expressed by relatively small bit number, and is so constructed that the user area and the supervisor area are separated from each other in accordance with the positiveness and the negativeness of address value, so that the positive and negative address space are allowed to optionally be extended in the direction of the greater absolute value without being split, and extending process of address value is easy, furthermore, the user area and the supervisor area can be judged merely by means of the signed bit denoting either the positiveness or the negativeness, to thereby violation of the access right in the supervisor area under the user mode being able to easily be detected.
摘要翻译：与本发明相关的数据处理器以由二进制表示的有符号二进制符号表示的地址值访问存储器被构造成使得具有最大绝对值的负地址值和具有相同值的正地址值不被包围在每个另一方面，具有签名的硬件扩展了由相对小的比特数表示的地址值，并且被构造成使得用户区域和主管区域根据地址值的积极性和否定性而彼此分离，使得允许正，负地址空间在绝对值较大的方向上被扩展，而不会被拆分，并且地址值的扩展处理容易，此外，用户区域和主管区域只能通过签署的位表示积极性或否定性，从而违反了访问权限用户模式下的主管区域能够容易地被检测。

2. 发明授权

US5132898A System for processing data having different formats 失效
标题翻译：用于处理具有不同格式的数据的系统
公开(公告)号：US5132898A
公开(公告)日：1992-07-21
申请号：US631197
申请日：1990-12-20
申请人： Ken Sakamura , Toyohiko Yoshida
发明人： Ken Sakamura , Toyohiko Yoshida
IPC分类号： G06F5/00 , G06F7/76 , G06F13/40
CPC分类号： G06F7/768 , G06F13/4013 , G06F5/00
摘要： A data processor that executes arithmetic operations between first and second binary numbers, stored in different registers, of different lengths, with the first number having a byte-length smaller than the register, and the second number having a byte-length equal to the register, by storing the first number so that its lower order bit is justified with the lower order bit of the second number. Additionally, data having different bit and byte polarities are processed by reversing the bit and byte order of the data as required.
摘要翻译：一种数据处理器，其执行存储在不同长度的不同寄存器中的第一和第二二进制数之间的算术运算，第一个数字的字节长度小于寄存器，第二个数字具有等于寄存器的字节长度，通过存储第一个数字，使得它的低阶位与第二个数字的低位位对齐。另外，通过根据需要反转数据的位和字节顺序来处理具有不同位和字节极性的数据。

3. 发明授权

US5434988A Data processor implementing a two's complement addressing technique 失效
标题翻译：数据处理器实现二进制补码寻址技术
公开(公告)号：US5434988A
公开(公告)日：1995-07-18
申请号：US181692
申请日：1994-01-14
申请人： Ken Sakamura , Toyohiko Yoshida
发明人： Ken Sakamura , Toyohiko Yoshida
IPC分类号： G06F12/14 , G06F12/00
CPC分类号： G06F12/1491
摘要： The data processor accesses memory with an address value which is expressed by signed binary notation expressed by twos compliment, is so constructed that the negative address value having maximum absolute value and the positive address value having the same are not wrapped around each other, is provided with hardware which signed extends the address values expressed by relatively small bit number, and is so constructed that the user area and the supervisor area are separated from each other in accordance with the positiveness and the negativeness of address value, so that the positive and negative address space are allowed to optionally be extended in the direction of the greater absolute value without being split, and extending process of address value is easy, furthermore, the user area and the supervisor area can be judged merely by means of the signed bit denoting either the positiveness or the negativeness, to thereby violation of the access right in the supervisor area under the user mode being able to easily be detected.
摘要翻译：提供数据处理器以由二进制表示的有符号二进制符号表示的地址值访问存储器，被构造为具有最大绝对值的负地址值和具有相同的正地址值不彼此缠绕符号的硬件扩展了由相对较小的位数表示的地址值，并且被构造为使得用户区域和主管区域根据地址值的积极性和否定性而彼此分离，使得正和负允许地址空间在绝对值较大的方向上可选地扩展，而不会被拆分，并且地址值的扩展处理容易，此外，用户区域和主管区域只能通过签名位来判断，积极性或消极性，从而违反了监督区内的访问权限用户模式能够容易地被检测。

4. 发明授权

US5327542A Data processor implementing a two's complement addressing technique 失效
标题翻译：数据处理器实现二进制补码寻址技术
公开(公告)号：US5327542A
公开(公告)日：1994-07-05
申请号：US89383
申请日：1993-07-08
申请人： Ken Sakamura , Toyohiko Yoshida
发明人： Ken Sakamura , Toyohiko Yoshida
IPC分类号： G06F12/14 , G06F9/34 , G06F12/00
CPC分类号： G06F12/1491
摘要： The data processor related to the invention accesses memory with an address value which is expressed by signed binary notation expressed by twos compliment, is so constructed that the negative address value having maximum absolute value and the positive address value having the same are not wrapped around each other, is provided with hardware which signed extends the address values expressed by relatively small bit number, and is so constructed that the user area and the supervisor area are separated from each other in accordance with the positiveness and the negativeness of address value, so that the positive and negative address space are allowed to optionally be extended in the direction of the greater absolute value without being split, and extending process of address value is easy, furthermore, the user area and the supervisor area can be judged merely by means of the signed bit denoting either the positiveness or the negativeness, to thereby violation of the access right in the supervisor area under the user mode being able to easily be detected.
摘要翻译：与本发明相关的数据处理器以由二进制表示的有符号二进制符号表示的地址值访问存储器被构造成使得具有最大绝对值的负地址值和具有相同值的正地址值不被包围在每个另一方面，具有签名的硬件扩展了由相对小的比特数表示的地址值，并且被构造成使得用户区域和主管区域根据地址值的积极性和否定性而彼此分离，使得允许正，负地址空间在绝对值较大的方向上被扩展，而不会被拆分，并且地址值的扩展处理容易，此外，用户区域和主管区域只能通过签署的位表示积极性或否定性，从而违反了访问权限用户模式下的主管区域能够容易地被检测。

5. 发明授权

US07346760B2 Data processing apparatus of high speed process using memory of low speed and low power consumption 有权
标题翻译：数据处理装置采用低速，低功耗的存储器
公开(公告)号：US07346760B2
公开(公告)日：2008-03-18
申请号：US09855594
申请日：2001-05-16
申请人： Toyohiko Yoshida , Akira Yamada , Hisakazu Sato
发明人： Toyohiko Yoshida , Akira Yamada , Hisakazu Sato
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/3814 , G06F7/5443 , G06F9/3802 , G06F9/381 , G06F9/3822 , G06F9/3875
摘要： When fetching an instruction from a plurality of memory banks, a first pipeline cycle corresponding to selection of a memory bank and a second pipeline cycle corresponding to instruction readout are generated to carry out a pipeline process. Only the selected memory bank can be precharged to allow reduction of power consumption. Since the first and second pipeline cycles are effected in parallel, the throughput of the instruction memory can be improved.
摘要翻译：当从多个存储体获取指令时，生成对应于存储器组的选择的第一流水线循环和对应于指令读出的第二流水线循环，以执行流水线处理。只有选定的存储体可以被预先充电，以减少功耗。由于第一和第二流水线周期是并行实现的，因此可以提高指令存储器的吞吐量。

6. 发明授权

US06408385B1 Data processor 失效
标题翻译：数据处理器
公开(公告)号：US06408385B1
公开(公告)日：2002-06-18
申请号：US09602830
申请日：2000-06-23
申请人： Masahito Matsuo , Toyohiko Yoshida
发明人： Masahito Matsuo , Toyohiko Yoshida
IPC分类号： G06F940
CPC分类号： G06F9/3806 , G06F9/30054 , G06F9/321 , G06F9/3842 , G06F9/3867
摘要： A data processor in accordance with the present invention makes it possible to perform pre-branch processing with respect to a return address in the initial stage of pipeline processing also on a subroutine return instruction, and therefore by providing a stack memory (PC stack) dedicated to a program counter (PC) for storing only return addresses of the subroutine return instruction, in executing a subroutine call instruction in an execution stage of a pipeline processing mechanism, the return address from the subroutine is pushed to the PC stack, and the pre-branch processing is performed to the address popped from the PC stack in decoding the subroutine return instruction in an instruction decoding stage.
摘要翻译：根据本发明的数据处理器使得可以在流水线处理的初始阶段对子程序返回指令执行关于返回地址的预分支处理，因此通过提供专用的堆栈存储器（PC堆栈）到用于仅存储子程序返回指令的返回地址的程序计数器（PC），在执行流水线处理机构的执行阶段中的子程序调用指令时，将子程序的返回地址推送到PC堆栈，在指令解码阶段对子例程返回指令进行解码时，对从PC堆栈弹出的地址进行分支处理。

7. 发明授权

US06333571B1 MOS integrated circuit device operating with low power consumption 有权
标题翻译： MOS集成电路器件以低功耗运行
公开(公告)号：US06333571B1
公开(公告)日：2001-12-25
申请号：US09577969
申请日：2000-05-25
申请人： Eiichi Teraoka , Toyohiko Yoshida
发明人： Eiichi Teraoka , Toyohiko Yoshida
IPC分类号： H01H4700
CPC分类号： H03K19/0013 , H01L27/092 , Y10T307/76 , Y10T307/826
摘要： In accordance with selection signals corresponding to an operation mode from a mode detection circuit, the voltage levels of back gate voltages applied to the back gates of MOS transistors included in internal circuitry are selected, by the selection signals, among the voltages from voltage generation circuits for generating a plurality of voltages having different voltage levels. The threshold voltage and the drive current of the MOS transistor are adjusted in accordance with the operation mode, and the semiconductor integrated circuit device which operates at high speed with low current consumption can be achieved.
摘要翻译：根据与来自模式检测电路的操作模式对应的选择信号，通过选择信号选择施加到内部电路中的MOS晶体管的背栅极的背栅电压的电压电平，来自电压产生电路用于产生具有不同电压电平的多个电压。根据操作模式调整MOS晶体管的阈值电压和驱动电流，并且可以实现以低电流消耗高速运行的半导体集成电路器件。

8. 发明授权

US6115806A Data processor having an instruction decoder and a plurality of executing units for performing a plurality of operations in parallel 失效
标题翻译：数据处理器具有指令解码器和用于并行执行多个操作的多个执行单元
公开(公告)号：US6115806A
公开(公告)日：2000-09-05
申请号：US56650
申请日：1998-04-08
申请人： Toyohiko Yoshida
发明人： Toyohiko Yoshida
IPC分类号： G06F9/30 , G06F9/32 , G06F9/38 , G06F3/30
CPC分类号： G06F9/30167 , G06F9/30145 , G06F9/3842 , G06F9/3853 , G06F9/3885
摘要： In a data processor, using a format field which specifies the number of operation fields of an instruction code and an order of execution of operations, the number of operations and the order of operation executions are flexibly controlled and the necessity of a null operation is reduced, and decoders operate in parallel each decoding only one operation having a specific function which has a dependency on an operation execution mechanism, so that the operation fields of the instruction code are decoded in parallel by a number of decoders. While the data processor is basically a VLIW type data processor, more types of operations can be specified by the operation fields, and coding efficiency of instructions is improved since the number of operation fields and the order of operation executions are flexibly controlled and the necessity of a null operation is reduced by means of the format field which specifies the number of the operation and the order of the operation executions.
摘要翻译：在数据处理器中，使用指定指令代码的操作字段的数量的格式字段和操作的执行顺序，灵活地控制操作次数和操作执行顺序，并且减少空操作的必要性并且解码器并行操作，每个仅解码具有与操作执行机构相关的特定功能的一个操作，使得指令代码的操作字段由多个解码器并行解码。虽然数据处理器基本上是一个VLIW型数据处理器，但操作领域可以指定更多类型的操作，并且由于操作字段的数量和操作执行的顺序被灵活地控制，并且必须通过指定操作次数和操作执行顺序的格式字段来减少空操作。

9. 发明授权

US5522053A Branch target and next instruction address calculation in a pipeline processor 失效
标题翻译：流水线处理器中的分支目标和下一条指令地址计算
公开(公告)号：US5522053A
公开(公告)日：1996-05-28
申请号：US291963
申请日：1994-08-17
申请人： Toyohiko Yoshida , Masahito Matuo
发明人： Toyohiko Yoshida , Masahito Matuo
IPC分类号： G06F9/32 , G06F9/38
CPC分类号： G06F9/32 , G06F9/38
摘要： An instruction decoding device for a data processor which is capable of predicting a branch address is disclosed. A program counter value calculation device can be used to calculate the branch target address. An address calculation device can be used to calculate an operand address. The address calculation device can calculate the operand address by adding the instruction length of the branch instruction and the program counter value of the branch instruction. In this way the apparatus performs branching processing for the unconditional branch instructions, conditional branch instructions, subroutine branch instructions and loop control instructions at the instruction decoding stage to suppress disturbances in the pipeline processing.
摘要翻译：公开了一种能够预测分支地址的数据处理器的指令解码装置。可以使用程序计数器值计算装置来计算分支目标地址。地址计算装置可用于计算操作数地址。地址计算装置可以通过添加分支指令的指令长度和分支指令的程序计数器值来计算操作数地址。以这种方式，设备在指令解码阶段对无条件转移指令，条件转移指令，子程序转移指令和循环控制指令执行分支处理，以抑制流水线处理中的干扰。

10. 发明授权

US5485587A Data processor calculating branch target address of a branch instruction in parallel with decoding of the instruction 失效
标题翻译：数据处理器与指令的解码并行地计算分支指令的分支目标地址
公开(公告)号：US5485587A
公开(公告)日：1996-01-16
申请号：US10085
申请日：1993-01-27
申请人： Masahito Matsuo , Toyohiko Yoshida
发明人： Masahito Matsuo , Toyohiko Yoshida
IPC分类号： G06F9/32 , G06F9/38 , G06F9/28
CPC分类号： G06F9/3804 , G06F9/322 , G06F9/3842
摘要： A data processor, comprising: an instruction fetch unit 111 which fetches instructions from a memory which stores instructions; an instruction decoding unit 112 which decodes the instructions fetched from the instruction fetch unit 111; an instruction execution unit which executes the instructions on the basis of the decoding result by the instruction decoding unit 112; a program counter (DPC) 29 which holds an address of the instruction being decoded in the instruction decoding unit 112; and a branch target address calculation unit 1 which is connected to the instruction fetch unit 111 and the program counter (DPC) 29, adds a value of a branch displacement field transferred from the instruction fetch unit 111 and the instruction address transferred from the program counter (DPC) 29, and transfers the addition result to the instruction fetch unit 111, so that jump instruction can be processed efficiently by pipeline processing.
摘要翻译：一种数据处理器，包括：指令提取单元111，其从存储指令的存储器中取出指令; 指令解码单元112，对从指令获取单元111取出的指令进行解码; 指令执行单元，其基于指令解码单元112的解码结果执行指令; 程序计数器（DPC）29，其保持在指令解码单元112中解码的指令的地址; 和连接到指令提取单元111和程序计数器（DPC）29的分支目标地址计算单元1相加从指令提取单元111传送的分支位移字段的值和从程序计数器传送的指令地址（DPC）29，并将相加结果传送到指令提取单元111，使得可以通过流水线处理有效地处理跳转指令。

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