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1. 发明授权

US06333571B1 MOS integrated circuit device operating with low power consumption 有权
标题翻译： MOS集成电路器件以低功耗运行
公开(公告)号：US06333571B1
公开(公告)日：2001-12-25
申请号：US09577969
申请日：2000-05-25
申请人： Eiichi Teraoka , Toyohiko Yoshida
发明人： Eiichi Teraoka , Toyohiko Yoshida
IPC分类号： H01H4700
CPC分类号： H03K19/0013 , H01L27/092 , Y10T307/76 , Y10T307/826
摘要： In accordance with selection signals corresponding to an operation mode from a mode detection circuit, the voltage levels of back gate voltages applied to the back gates of MOS transistors included in internal circuitry are selected, by the selection signals, among the voltages from voltage generation circuits for generating a plurality of voltages having different voltage levels. The threshold voltage and the drive current of the MOS transistor are adjusted in accordance with the operation mode, and the semiconductor integrated circuit device which operates at high speed with low current consumption can be achieved.
摘要翻译：根据与来自模式检测电路的操作模式对应的选择信号，通过选择信号选择施加到内部电路中的MOS晶体管的背栅极的背栅电压的电压电平，来自电压产生电路用于产生具有不同电压电平的多个电压。根据操作模式调整MOS晶体管的阈值电压和驱动电流，并且可以实现以低电流消耗高速运行的半导体集成电路器件。

2. 发明授权

US6097113A MOS integrated circuit device operating with low power consumption 失效
标题翻译： MOS集成电路器件以低功耗运行
公开(公告)号：US6097113A
公开(公告)日：2000-08-01
申请号：US84949
申请日：1998-05-28
申请人： Eiichi Teraoka , Toyohiko Yoshida
发明人： Eiichi Teraoka , Toyohiko Yoshida
IPC分类号： H01L29/78 , G11C11/408 , H01L21/8238 , H01L27/092 , H03F1/02 , H03K19/00 , H03K19/094 , H01H47/00
CPC分类号： H03K19/0013 , H01L27/092 , Y10T307/76 , Y10T307/826
摘要： In accordance with selection signals corresponding to an operation mode from a mode detection circuit, the voltage levels of back gate voltages applied to the back gates of MOS transistors included in internal circuitry are selected, by the selection signals, among the voltages from voltage generation circuits for generating a plurality of voltages having different voltage levels. The threshold voltage and the drive current of the MOS transistor are adjusted in accordance with the operation mode, and the semiconductor integrated circuit device which operates at high speed with low current consumption can be achieved.
摘要翻译：根据与来自模式检测电路的操作模式对应的选择信号，通过选择信号选择施加到内部电路中的MOS晶体管的背栅极的背栅电压的电压电平，来自电压产生电路用于产生具有不同电压电平的多个电压。根据操作模式调整MOS晶体管的阈值电压和驱动电流，并且可以实现以低电流消耗高速运行的半导体集成电路器件。

3. 发明授权

US5191547A Decimating digital finite impulse response filter 失效
标题翻译：抽取数字有限脉冲响应滤波器
公开(公告)号：US5191547A
公开(公告)日：1993-03-02
申请号：US564808
申请日：1990-08-08
申请人： Koji Kawamoto , Toru Kengaku , Eiichi Teraoka , Tetsuaki Oga , Hiroichi Ishida
发明人： Koji Kawamoto , Toru Kengaku , Eiichi Teraoka , Tetsuaki Oga , Hiroichi Ishida
IPC分类号： H03H17/00 , G06F17/10 , H03H17/06
CPC分类号： H03H17/0664 , G06F17/10 , H03H2218/10
摘要： A decimation type digital filter which utilizes the thinned-out signal of a finite impulse response (FIR) filter having N taps for processing the signal by the product sum operation of filter coefficients and the input signals inputted at every first period, in which, on the basis of the ratio K between a first period which is the input signal period and an output signal period and the number of taps N, M (a value obtained by raising below the decimal point of N/K) registers are provided and M successive output signals are processed by the product sum operation in parallel by respective registers, whereby the input signal is not necessarily to be held, a capacity of the register may be minimized and processing may be effected once for each register during the first period or by M number of times of product sum operation in total, thus the operating speed can be reduced to 1/K and the capacity and the operating speed can be optimized.
摘要翻译：一种抽取式数字滤波器，其利用具有N个抽头的有限脉冲响应（FIR）滤波器的稀疏信号通过滤波器系数的乘积和运算和每个第一周期输入的输入信号来处理该信号，其中，提供作为输入信号周期的第一周期与输出信号周期之间的比率K与抽头数N，M（通过升高到小于N / K的小数点而获得的值）之间的比率K的基础，M连续输出信号由相应的寄存器并行处理，由此输入信号不一定被保持，寄存器的容量可以最小化，并且可以在第一周期期间对每个寄存器执行一次处理，或者通过M 产品总计运算次数，可以将运行速度降低到1 / K，可以优化运行速度和运行速度。

4. 发明授权

US4856106A Synchronous static random access memory having precharge system and operating method thereof 失效
标题翻译：具有预充电系统的同步静态随机存取存储器及其操作方法
公开(公告)号：US4856106A
公开(公告)日：1989-08-08
申请号：US230343
申请日：1988-08-09
申请人： Eiichi Teraoka
发明人： Eiichi Teraoka
IPC分类号： G11C11/41 , G11C7/10 , G11C7/12 , G11C11/409
CPC分类号： G11C7/12 , G11C7/1048
摘要： A plurality sets of bit line pairs are connected to one set of common data line pair respectively through bit line selecting transistors. The common data line pair is coupled to the supply potential through precharging transistors. In the precharging period, a set of bit line pair is selected by a Y decoder to be connected to the common data line pair. On this occasion, the precharging transistor turns on in response to a precharge signal and the selected bit line pair is precharged through the common data line pair. The bit line pair which is not selected is not precharged.
摘要翻译：多组位线对分别通过位线选择晶体管连接到一组公共数据线对。公共数据线对通过预充电晶体管耦合到电源电位。在预充电期间，由Y解码器选择一组位线对以连接到公共数据线对。在这种情况下，预充电晶体管响应于预充电信号而导通，并且所选位线对通过公共数据线对被预充电。未选择的位线对未预充电。

5. 发明授权

US5276889A Microprocessor having built-in synchronous memory with power-saving feature 失效
标题翻译：具有内置同步存储器的微处理器具有省电功能
公开(公告)号：US5276889A
公开(公告)日：1994-01-04
申请号：US543273
申请日：1990-06-25
申请人： Taketora Shiraishi , Eiichi Teraoka , Toru Kengaku
发明人： Taketora Shiraishi , Eiichi Teraoka , Toru Kengaku
IPC分类号： G06F1/04 , G06F1/32 , G06F9/38 , G06F15/78
CPC分类号： G06F1/3215 , G06F1/3275 , G06F9/3836 , Y02B60/1225 , Y02B60/1228 , Y02B60/32
摘要： A microprocessor, including a synchronous type memory having several parts, includes a power saving feature that places at least some parts of the memory in a non-operating state when instructions not requiring access to the memory are executed. An enable signal is generated when access is not required and a signal supplying circuit supplies a synchronous signal when the enable signal is not generated and supplies a signal in a predetermined state to place at least some parts or all parts of the memory in the non-operating state to reduce power consumption.
摘要翻译：包括具有若干部分的同步型存储器的微处理器包括省电功能，其中当执行不需要访问存储器的指令时，将存储器的至少一些部分置于非操作状态。当不需要访问时产生使能信号，并且当不产生使能信号时信号供给电路提供同步信号，并且提供处于预定状态的信号以将存储器的至少一部分或全部部分放置在非易失性存储器中，运行状态降低功耗。

6. 发明授权

US4777623A Semiconductor memory device having initialization transistor 失效
标题翻译：具有初始晶体管的半导体存储器
公开(公告)号：US4777623A
公开(公告)日：1988-10-11
申请号：US869653
申请日：1986-06-02
申请人： Yukihiko Shimazu , Eiichi Teraoka
发明人： Yukihiko Shimazu , Eiichi Teraoka
IPC分类号： G11C7/00 , G06F1/24 , G11C11/401 , G11C11/41 , H03K3/037 , H03K3/356 , G11C11/40
CPC分类号： H03K3/356095 , H03K3/35606
摘要： A memory circuit 14 comprises a MOS transistor 15 having its threshold voltage selected to be higher than the output voltage on the occasion of the ordinary operation. Consequently, the MOS transistor 15 is off on the occasion of the ordinary operation, and a ratio latch 4 performs the ordinary storing operation. Meanwhile, if the output voltage of the power source 12 is raised, the MOS transistor 15 turns on to pull down the potential of a data input line 6a to the ratio latch. Accordingly, the ratio latch 4 is forced to be set.
摘要翻译：存储电路14包括在正常操作时选择其阈值电压高于输出电压的MOS晶体管15。因此，在正常工作的情况下，MOS晶体管15截止，比例锁存器4进行普通存储操作。同时，如果电源12的输出电压升高，则MOS晶体管15导通，将数据输入线6a的电位下拉到比率锁存器。因此，比例闩锁4被强制设定。

7. 发明授权

US5317529A Digital filter using intermediate holding registers and common accumulators and multipliers 失效
标题翻译：数字滤波器使用中间保持寄存器和公共累加器和乘法器
公开(公告)号：US5317529A
公开(公告)日：1994-05-31
申请号：US859208
申请日：1992-03-27
申请人： Eiichi Teraoka , Toru Kengaku , Hiroichi Ishida
发明人： Eiichi Teraoka , Toru Kengaku , Hiroichi Ishida
IPC分类号： H03M1/00 , H03H17/00 , H03H17/02 , H03H17/06 , H03M3/00 , G06F15/31
CPC分类号： H03H17/0657 , H03H17/0664 , H03H17/0685 , H03H2218/08 , H03H2218/085
摘要： An A/D-D/A converting apparatus, in which a multiplier is omitted by storing the multiplied result of a filter coefficient and a digital signal in advance and reading it out responsive to the inputted digital signal, in view of the point that filter characteristics of digital filters of an A/D converting unit and a D/A converting unit are equal one another, memories which are coefficient generating devices are used in common, and further, in view of the point :hat processing contents of respective digital filters are equal, a multiplier and an accumulator constituting the digital filter are used in common to reduce a circuit configuration considerably.
摘要翻译： A / DD / A转换装置，其中通过根据输入的数字信号预先存储滤波器系数和数字信号的相乘结果而省略乘法器，考虑到滤波器特性 A / D转换单元和D / A转换单元的数字滤波器彼此相等，作为系数产生装置的存储器是共同使用的，此外，考虑到各个数字滤波器的帽子处理内容相等，共同地使用构成数字滤波器的乘法器和累加器来显着地减少电路配置。

8. 发明授权

US5162667A Semiconductor integrated circuit with master and slave latches 失效
标题翻译：半导体集成电路与主从锁存器
公开(公告)号：US5162667A
公开(公告)日：1992-11-10
申请号：US610179
申请日：1990-11-07
申请人： Ikuo Yasui , Toru Kengaku , Eiichi Teraoka
发明人： Ikuo Yasui , Toru Kengaku , Eiichi Teraoka
IPC分类号： H03K3/289 , G06F1/32 , H03K3/037
CPC分类号： G06F1/32 , H03K3/0372
摘要： A semiconductor integrated circuit of master and slave latches and the like that reduces power consumption by supplying a second clock which is a synchronous with a first clock to a slave latch only when the first clock that determines the latch period is supplied to a master latch, discontinuing the supply of the second clock after the master latch completes its latch action in the case that the supply of the first clock to the master latch is discontinued, and discontinuing the supply of clocks when latch action is not required, to reduce loads connected to them.
摘要翻译：主锁存器和从锁存器等的半导体集成电路，只有当确定锁存周期的第一时钟被提供给主锁存器时，通过将与第一时钟同步的第二时钟提供给从锁存器来降低功耗，在主锁存器提供第一时钟到主锁存器被停止的情况下，在主锁存器完成其锁存动作之后停止提供第二时钟，并且当不需要锁存动作时停止提供时钟，以减少连接到他们。

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