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1. 发明授权

US06333571B1 MOS integrated circuit device operating with low power consumption 有权
标题翻译： MOS集成电路器件以低功耗运行
公开(公告)号：US06333571B1
公开(公告)日：2001-12-25
申请号：US09577969
申请日：2000-05-25
申请人： Eiichi Teraoka , Toyohiko Yoshida
发明人： Eiichi Teraoka , Toyohiko Yoshida
IPC分类号： H01H4700
CPC分类号： H03K19/0013 , H01L27/092 , Y10T307/76 , Y10T307/826
摘要： In accordance with selection signals corresponding to an operation mode from a mode detection circuit, the voltage levels of back gate voltages applied to the back gates of MOS transistors included in internal circuitry are selected, by the selection signals, among the voltages from voltage generation circuits for generating a plurality of voltages having different voltage levels. The threshold voltage and the drive current of the MOS transistor are adjusted in accordance with the operation mode, and the semiconductor integrated circuit device which operates at high speed with low current consumption can be achieved.
摘要翻译：根据与来自模式检测电路的操作模式对应的选择信号，通过选择信号选择施加到内部电路中的MOS晶体管的背栅极的背栅电压的电压电平，来自电压产生电路用于产生具有不同电压电平的多个电压。根据操作模式调整MOS晶体管的阈值电压和驱动电流，并且可以实现以低电流消耗高速运行的半导体集成电路器件。

2. 发明授权

US6097113A MOS integrated circuit device operating with low power consumption 失效
标题翻译： MOS集成电路器件以低功耗运行
公开(公告)号：US6097113A
公开(公告)日：2000-08-01
申请号：US84949
申请日：1998-05-28
申请人： Eiichi Teraoka , Toyohiko Yoshida
发明人： Eiichi Teraoka , Toyohiko Yoshida
IPC分类号： H01L29/78 , G11C11/408 , H01L21/8238 , H01L27/092 , H03F1/02 , H03K19/00 , H03K19/094 , H01H47/00
CPC分类号： H03K19/0013 , H01L27/092 , Y10T307/76 , Y10T307/826
摘要： In accordance with selection signals corresponding to an operation mode from a mode detection circuit, the voltage levels of back gate voltages applied to the back gates of MOS transistors included in internal circuitry are selected, by the selection signals, among the voltages from voltage generation circuits for generating a plurality of voltages having different voltage levels. The threshold voltage and the drive current of the MOS transistor are adjusted in accordance with the operation mode, and the semiconductor integrated circuit device which operates at high speed with low current consumption can be achieved.
摘要翻译：根据与来自模式检测电路的操作模式对应的选择信号，通过选择信号选择施加到内部电路中的MOS晶体管的背栅极的背栅电压的电压电平，来自电压产生电路用于产生具有不同电压电平的多个电压。根据操作模式调整MOS晶体管的阈值电压和驱动电流，并且可以实现以低电流消耗高速运行的半导体集成电路器件。

3. 发明授权

US07346760B2 Data processing apparatus of high speed process using memory of low speed and low power consumption 有权
标题翻译：数据处理装置采用低速，低功耗的存储器
公开(公告)号：US07346760B2
公开(公告)日：2008-03-18
申请号：US09855594
申请日：2001-05-16
申请人： Toyohiko Yoshida , Akira Yamada , Hisakazu Sato
发明人： Toyohiko Yoshida , Akira Yamada , Hisakazu Sato
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/3814 , G06F7/5443 , G06F9/3802 , G06F9/381 , G06F9/3822 , G06F9/3875
摘要： When fetching an instruction from a plurality of memory banks, a first pipeline cycle corresponding to selection of a memory bank and a second pipeline cycle corresponding to instruction readout are generated to carry out a pipeline process. Only the selected memory bank can be precharged to allow reduction of power consumption. Since the first and second pipeline cycles are effected in parallel, the throughput of the instruction memory can be improved.
摘要翻译：当从多个存储体获取指令时，生成对应于存储器组的选择的第一流水线循环和对应于指令读出的第二流水线循环，以执行流水线处理。只有选定的存储体可以被预先充电，以减少功耗。由于第一和第二流水线周期是并行实现的，因此可以提高指令存储器的吞吐量。

4. 发明授权

US06408385B1 Data processor 失效
标题翻译：数据处理器
公开(公告)号：US06408385B1
公开(公告)日：2002-06-18
申请号：US09602830
申请日：2000-06-23
申请人： Masahito Matsuo , Toyohiko Yoshida
发明人： Masahito Matsuo , Toyohiko Yoshida
IPC分类号： G06F940
CPC分类号： G06F9/3806 , G06F9/30054 , G06F9/321 , G06F9/3842 , G06F9/3867
摘要： A data processor in accordance with the present invention makes it possible to perform pre-branch processing with respect to a return address in the initial stage of pipeline processing also on a subroutine return instruction, and therefore by providing a stack memory (PC stack) dedicated to a program counter (PC) for storing only return addresses of the subroutine return instruction, in executing a subroutine call instruction in an execution stage of a pipeline processing mechanism, the return address from the subroutine is pushed to the PC stack, and the pre-branch processing is performed to the address popped from the PC stack in decoding the subroutine return instruction in an instruction decoding stage.
摘要翻译：根据本发明的数据处理器使得可以在流水线处理的初始阶段对子程序返回指令执行关于返回地址的预分支处理，因此通过提供专用的堆栈存储器（PC堆栈）到用于仅存储子程序返回指令的返回地址的程序计数器（PC），在执行流水线处理机构的执行阶段中的子程序调用指令时，将子程序的返回地址推送到PC堆栈，在指令解码阶段对子例程返回指令进行解码时，对从PC堆栈弹出的地址进行分支处理。

5. 发明授权

US6115806A Data processor having an instruction decoder and a plurality of executing units for performing a plurality of operations in parallel 失效
标题翻译：数据处理器具有指令解码器和用于并行执行多个操作的多个执行单元
公开(公告)号：US6115806A
公开(公告)日：2000-09-05
申请号：US56650
申请日：1998-04-08
申请人： Toyohiko Yoshida
发明人： Toyohiko Yoshida
IPC分类号： G06F9/30 , G06F9/32 , G06F9/38 , G06F3/30
CPC分类号： G06F9/30167 , G06F9/30145 , G06F9/3842 , G06F9/3853 , G06F9/3885
摘要： In a data processor, using a format field which specifies the number of operation fields of an instruction code and an order of execution of operations, the number of operations and the order of operation executions are flexibly controlled and the necessity of a null operation is reduced, and decoders operate in parallel each decoding only one operation having a specific function which has a dependency on an operation execution mechanism, so that the operation fields of the instruction code are decoded in parallel by a number of decoders. While the data processor is basically a VLIW type data processor, more types of operations can be specified by the operation fields, and coding efficiency of instructions is improved since the number of operation fields and the order of operation executions are flexibly controlled and the necessity of a null operation is reduced by means of the format field which specifies the number of the operation and the order of the operation executions.
摘要翻译：在数据处理器中，使用指定指令代码的操作字段的数量的格式字段和操作的执行顺序，灵活地控制操作次数和操作执行顺序，并且减少空操作的必要性并且解码器并行操作，每个仅解码具有与操作执行机构相关的特定功能的一个操作，使得指令代码的操作字段由多个解码器并行解码。虽然数据处理器基本上是一个VLIW型数据处理器，但操作领域可以指定更多类型的操作，并且由于操作字段的数量和操作执行的顺序被灵活地控制，并且必须通过指定操作次数和操作执行顺序的格式字段来减少空操作。

6. 发明授权

US5522053A Branch target and next instruction address calculation in a pipeline processor 失效
标题翻译：流水线处理器中的分支目标和下一条指令地址计算
公开(公告)号：US5522053A
公开(公告)日：1996-05-28
申请号：US291963
申请日：1994-08-17
申请人： Toyohiko Yoshida , Masahito Matuo
发明人： Toyohiko Yoshida , Masahito Matuo
IPC分类号： G06F9/32 , G06F9/38
CPC分类号： G06F9/32 , G06F9/38
摘要： An instruction decoding device for a data processor which is capable of predicting a branch address is disclosed. A program counter value calculation device can be used to calculate the branch target address. An address calculation device can be used to calculate an operand address. The address calculation device can calculate the operand address by adding the instruction length of the branch instruction and the program counter value of the branch instruction. In this way the apparatus performs branching processing for the unconditional branch instructions, conditional branch instructions, subroutine branch instructions and loop control instructions at the instruction decoding stage to suppress disturbances in the pipeline processing.
摘要翻译：公开了一种能够预测分支地址的数据处理器的指令解码装置。可以使用程序计数器值计算装置来计算分支目标地址。地址计算装置可用于计算操作数地址。地址计算装置可以通过添加分支指令的指令长度和分支指令的程序计数器值来计算操作数地址。以这种方式，设备在指令解码阶段对无条件转移指令，条件转移指令，子程序转移指令和循环控制指令执行分支处理，以抑制流水线处理中的干扰。

7. 发明授权

US5485587A Data processor calculating branch target address of a branch instruction in parallel with decoding of the instruction 失效
标题翻译：数据处理器与指令的解码并行地计算分支指令的分支目标地址
公开(公告)号：US5485587A
公开(公告)日：1996-01-16
申请号：US10085
申请日：1993-01-27
申请人： Masahito Matsuo , Toyohiko Yoshida
发明人： Masahito Matsuo , Toyohiko Yoshida
IPC分类号： G06F9/32 , G06F9/38 , G06F9/28
CPC分类号： G06F9/3804 , G06F9/322 , G06F9/3842
摘要： A data processor, comprising: an instruction fetch unit 111 which fetches instructions from a memory which stores instructions; an instruction decoding unit 112 which decodes the instructions fetched from the instruction fetch unit 111; an instruction execution unit which executes the instructions on the basis of the decoding result by the instruction decoding unit 112; a program counter (DPC) 29 which holds an address of the instruction being decoded in the instruction decoding unit 112; and a branch target address calculation unit 1 which is connected to the instruction fetch unit 111 and the program counter (DPC) 29, adds a value of a branch displacement field transferred from the instruction fetch unit 111 and the instruction address transferred from the program counter (DPC) 29, and transfers the addition result to the instruction fetch unit 111, so that jump instruction can be processed efficiently by pipeline processing.
摘要翻译：一种数据处理器，包括：指令提取单元111，其从存储指令的存储器中取出指令; 指令解码单元112，对从指令获取单元111取出的指令进行解码; 指令执行单元，其基于指令解码单元112的解码结果执行指令; 程序计数器（DPC）29，其保持在指令解码单元112中解码的指令的地址; 和连接到指令提取单元111和程序计数器（DPC）29的分支目标地址计算单元1相加从指令提取单元111传送的分支位移字段的值和从程序计数器传送的指令地址（DPC）29，并将相加结果传送到指令提取单元111，使得可以通过流水线处理有效地处理跳转指令。

8. 发明授权

US5465376A Microprocessor, coprocessor and data processing system using them 失效
标题翻译：微处理器，协处理器和数据处理系统使用它们
公开(公告)号：US5465376A
公开(公告)日：1995-11-07
申请号：US59943
申请日：1993-05-05
申请人： Toyohiko Yoshida
发明人： Toyohiko Yoshida
IPC分类号： G06F9/30 , G06F9/34 , G06F9/38 , G06F9/46
CPC分类号： G06F9/3802 , G06F9/3016 , G06F9/30167 , G06F9/34 , G06F9/382 , G06F9/3863 , G06F9/3877
摘要： In a data processing system, the program counter (PC) values of coprocessor (CP) instructions are stored in a queue of a CP, and the stored PC value is not erased until the CP has completed executing the instruction. The need for a queue is caused by the pipeline in the CP. Three instructions may be executing concurrently and an exception may occur for any one of them. Accordingly, for example, at least 3 PC values must be stored in the queue. Early overwriting is prevented by making the queue 4 words deep. Also, the CP must assert a CPST signal before accepting a new command from the micro processor (MC). Thus, if the pipeline is full the CPST signal will not be asserted and the MP must wait before storing the new PC value in the queue. Instead of the entire PC, only an entry point is transferred to the CP. When only four PC values are saved, the entry point is only two bits and may be transferred along with the command information in a single bus cycle. If there are more than one CP, a program status word (PSW) includes a CPID for identifying which CP is to execute a received CP instruction. The queue and PCID system is only used for the first CP. In the event that an exception occurs, the entry point is transferred back to the MP and the PC of the instruction that took the exception is provided.
摘要翻译：在数据处理系统中，协处理器（CP）指令的程序计数器（PC）值被存储在CP的队列中，并且存储的PC值不被擦除，直到CP完成执行指令。队列的需要是由CP中的管道引起的。三个指令可能同时执行，并且任何一个可能发生异常。因此，例如，必须在队列中存储至少3个PC值。通过使队列4字深入，可以防止早期重写。此外，CP必须在接收来自微处理器（MC）的新命令之前先断言CPST信号。因此，如果流水线已满，则将不会断言CPST信号，并且在将新的PC值存储在队列中之前，MP必须等待。而不是整个PC，只有一个入口点被传送到CP。当仅保存四个PC值时，入口点只有两个位，并且可以在单个总线周期内与命令信息一起传输。如果存在多于一个CP，则程序状态字（PSW）包括用于识别哪个CP执行接收到的CP指令的CPID。队列和PCID系统仅用于第一个CP。在发生异常的情况下，将入口点传回MP，提供异常指令的PC。

9. 发明授权

US5390307A Apparatus for a multi-data store or load instruction for transferring multiple contiguous storage locations in one transfer operation 失效
标题翻译：用于在一个传送操作中传送多个连续存储位置的多数据存储或加载指令的装置
公开(公告)号：US5390307A
公开(公告)日：1995-02-14
申请号：US245846
申请日：1994-05-19
申请人： Toyohiko Yoshida
发明人： Toyohiko Yoshida
IPC分类号： G06F9/30 , G06F9/312 , G06F9/34 , G06F12/06
CPC分类号： G06F9/30043
摘要： A data processor wherein, in the case where an instruction decoder has decoded a multi-data transfer (storing or loading) instruction, bits in a register list outputted from the instruction decoder are searched by first and second priority encoders to encode respectively a position of "1" (or "0") and a position where "1" (or "0") is continued in two bits as binary digits, and when the encoded results do not coincide only one register corresponding to a bit position of the single "1" (or "0") is accessed, when the encoded results coincide the registers corresponding to the bit positions of the two continuous "1" (or "0") are accessed at the same time to process the multi-data transfer instruction effectively.
摘要翻译：一种数据处理器，其中在指令解码器已经对多数据传送（存储或加载）指令进行解码的情况下，由第一和第二优先级编码器搜索从指令解码器输出的寄存器列表中的比特，分别编码 “1”（或“0”）和“2”（或“0”）作为二进制数位继续的位置，并且当编码结果不与仅对应于单个位的一个位的一个寄存器重合时访问“1”（或“0”），当编码结果重合时，同时访问与两个连续“1”（或“0”）的位位置相对应的寄存器，以处理多数据传输指令有效。

10. 发明授权

US5386580A Data processor 失效
标题翻译：数据处理器
公开(公告)号：US5386580A
公开(公告)日：1995-01-31
申请号：US819545
申请日：1992-01-10
申请人： Toyohiko Yoshida , Masahito Matsuo
发明人： Toyohiko Yoshida , Masahito Matsuo
IPC分类号： G06F9/22 , G06F9/28 , G06F9/30 , G06F9/34 , G06F9/345 , G06F9/35 , G06F9/38
CPC分类号： G06F9/345 , G06F9/34
摘要： A data processor which comprises: an instruction decoding unit for decoding the instruction; an operand address calculating unit having an adder and an output latch holding the added result and calculating addresses of plural memory operands, in accordance with address calculation control code outputted from the instruction decoding unit; and an instruction executing unit for executing the instruction, in accordance with the operand address outputted from the operand address calculating unit and an operation control code outputted from the instruction decoding unit; and is capable of executing the plural data operating instruction for processing plural data at high efficiency, by performing address calculation of the plural operands by the operand address calculating unit before executing the instruction by the instruction executing unit.
摘要翻译：一种数据处理器，包括：指令解码单元，用于解码指令; 操作数地址计算单元，具有根据从指令解码单元输出的地址计算控制码，具有加法器和保存相加结果的输出锁存器以及计算多个存储器操作数的地址; 以及指令执行单元，用于根据从操作数地址计算单元输出的操作数地址和从指令解码单元输出的操作控制代码执行指令; 并且能够通过由指令执行单元执行指令之前通过操作数地址计算单元执行多个操作数的地址计算，来执行用于高效率处理多个数据的多个数据操作指令。

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