专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06475356B1 Method and apparatus for improving sidewall coverage during sputtering in a chamber having an inductively coupled plasma 失效
标题翻译：用于在具有电感耦合等离子体的腔室中改善溅射期间的侧壁覆盖度的方法和装置
公开(公告)号：US06475356B1
公开(公告)日：2002-11-05
申请号：US09493700
申请日：2000-01-28
申请人： Ken Ngan , Simon Hui , Seshadri Ramaswami
发明人： Ken Ngan , Simon Hui , Seshadri Ramaswami
IPC分类号： C23C1434
CPC分类号： C23C14/345 , C23C14/046 , C23C14/34 , C23C14/358 , H01J37/321 , H01J37/34 , H01J2237/3327 , H01L21/2855 , H01L21/76843 , H01L21/76877
摘要： Increased sidewall coverage by a sputtered material is achieved by generating an ionizing plasma in a relatively low pressure sputtering gas. By reducing the pressure of the sputtering gas, it is believed that the ionization rate of the deposition material passing through the plasma is correspondingly reduced which in turn is believed to increase the sidewall coverage by the underlayer. Although the ionization rate is decreased, sufficient bottom coverage of the by the material is maintained. In an alternative embodiment, increased sidewall coverage by the material may be achieved even in a high density plasma chamber by generating the high density plasma only during an initial portion of the material deposition. Once good bottom coverage has been achieved, the RF power to the coil generating the high density plasma may be turned off entirely and the remainder of the deposition conducted without the high density plasma. Consequently, it has been found that good sidewall coverage is achieved in the latter part of the deposition.
摘要翻译：通过在相对低压的溅射气体中产生电离等离子体，可以通过溅射材料增加侧壁覆盖。通过降低溅射气体的压力，相信通过等离子体的沉积材料的电离率相应地降低，这又被认为增加了底层的侧壁覆盖。虽然电离速率降低，但材料的底部覆盖范围仍然足够。在替代实施例中，即使在高密度等离子体室中，仅通过在材料沉积的初始部分期间产生高密度等离子体，可以实现材料增加的侧壁覆盖。一旦已经实现了良好的底部覆盖，则产生高密度等离子体的线圈的RF功率可以被完全截止，并且剩余的沉积在没有高密度等离子体的情况下进行。因此，已经发现在沉积的后半部分中实现良好的侧壁覆盖。

2. 发明授权

US08940619B2 Method of diced wafer transportation 有权
标题翻译：切片晶片运输方法
公开(公告)号：US08940619B2
公开(公告)日：2015-01-27
申请号：US13917973
申请日：2013-06-14
申请人： Wei-Sheng Lei , Brad Eaton , Aparna Iyer , Saravjeet Singh , Todd Egan , Ajay Kumar , Seshadri Ramaswami
发明人： Wei-Sheng Lei , Brad Eaton , Aparna Iyer , Saravjeet Singh , Todd Egan , Ajay Kumar , Seshadri Ramaswami
IPC分类号： H01L21/78 , H01L21/463 , H01L21/47 , H01L21/475 , H01L21/82 , H01L21/56 , H01L21/683
CPC分类号： H01L23/32 , H01L21/463 , H01L21/47 , H01L21/475 , H01L21/561 , H01L21/6835 , H01L21/6836 , H01L21/78 , H01L21/82 , H01L27/04 , H01L2924/0002 , H01L2924/00
摘要： Methods of dicing semiconductor wafers, and transporting singulated die, are described. In an example, a method of dicing a wafer having a plurality of integrated circuits thereon involves dicing the wafer into a plurality of singulated dies disposed above a dicing tape. The method also involves forming a water soluble material layer over and between the plurality of singulated dies, above the dicing tape.
摘要翻译：描述了切割半导体晶片和输送单个模具的方法。在一个示例中，在其上划分具有多个集成电路的晶片的方法包括将晶片切割成设置在切割带上方的多个单片模具。该方法还涉及在切割胶带上方的多个分割模具之上和之间形成水溶性材料层。

3. 发明授权

US06627542B1 Continuous, non-agglomerated adhesion of a seed layer to a barrier layer 有权
标题翻译：种子层与阻挡层的连续的非团聚粘附
公开(公告)号：US06627542B1
公开(公告)日：2003-09-30
申请号：US09604858
申请日：2000-06-27
申请人： Srinivas Gandikota , Rong Tao , Liang-Yuh Chen , Seshadri Ramaswami
发明人： Srinivas Gandikota , Rong Tao , Liang-Yuh Chen , Seshadri Ramaswami
IPC分类号： H01L2144
CPC分类号： H01L21/76868 , H01L21/76843 , H01L21/76846 , H01L21/76873 , H01L21/76877 , H01L2221/1089
摘要： A method and apparatus is provided for improving adherence of metal seed layers to barrier layers in electrochemical deposition techniques. The method includes depositing an adhesion layer continuously or semi-continuously without agglomeration onto a barrier layer prior to depositing a seed layer by controlling the substrate temperature, the chamber pressure, and/or the power delivered to a deposition chamber. Deposition of the adhesion layer prevents layer delamination which leads to agglomeration of the deposited layers and formation of voids in the high aspect ratio features.
摘要翻译：提供了一种用于在电化学沉积技术中改善金属种子层对阻挡层的粘附性的方法和装置。该方法包括通过控制衬底温度，室压力和/或输送到沉积室的功率沉积种子层之前将粘附层连续地或半连续地沉积在阻挡层上。粘附层的沉积防止了层析层，导致沉积层的聚集和高纵横比特征形成空隙。

4. 发明授权

US06391163B1 Method of enhancing hardness of sputter deposited copper films 失效
标题翻译：提高溅射沉积铜膜硬度的方法
公开(公告)号：US06391163B1
公开(公告)日：2002-05-21
申请号：US09518004
申请日：2000-03-02
申请人： Vikram Pavate , Murali Abburi , Murali Narasimhan , Seshadri Ramaswami
发明人： Vikram Pavate , Murali Abburi , Murali Narasimhan , Seshadri Ramaswami
IPC分类号： C23C1434
CPC分类号： H01L21/76871 , C23C14/3407 , C23C14/35 , H01J37/3426 , H01L21/2855 , H01L21/76843 , H01L21/76873 , H01L23/53233 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a method and apparatus for forming a copper layer on a substrate, preferably using a sputtering process. The sputtering process involves bombarding a conductive member of enhanced hardness with ions to dislodge the copper from the conductive member. The hardness of the target may be enhanced by alloying the copper conductive member with another material and/or mechanically working the material of the conductive member during its manufacturing process in order to improve conductive member and film qualities. The copper may be alloyed with magnesium, zinc, aluminum, iron, nickel, silicon and any combination thereof.
摘要翻译：本发明提供了一种在衬底上形成铜层的方法和装置，优选使用溅射工艺。溅射工艺包括用离子轰击具有增强硬度的导电部件，以从导电部件移除铜。可以通过在其制造过程中将铜导电构件与另一材料合金化和/或机械地加工导电构件的材料来增强靶的硬度，以便改善导电构件和膜质量。铜可以与镁，锌，铝，铁，镍，硅及其任何组合合金化。

5. 发明授权

US06228186B1 Method for manufacturing metal sputtering target for use in DC magnetron so that target has reduced number of conduction anomalies 有权
标题翻译：用于制造用于直流磁控管的金属溅射靶的方法，使得目标具有减少的导通异常的数量
公开(公告)号：US06228186B1
公开(公告)日：2001-05-08
申请号：US09418672
申请日：1999-10-14
申请人： Vikram Pavate , Keith J. Hansen , Glen Mori , Murali Narasimhan , Seshadri Ramaswami , Jaim Nulman
发明人： Vikram Pavate , Keith J. Hansen , Glen Mori , Murali Narasimhan , Seshadri Ramaswami , Jaim Nulman
IPC分类号： C22F100
CPC分类号： C23C14/3414 , Y10S29/002 , Y10S29/005 , Y10T29/49988
摘要： Improved targets for use in DC_magnetron sputtering of aluminum or like metals are disclosed for forming metallization films having low defect densities. Methods for manufacturing and using such targets are also disclosed. Conductivity anomalies such as those composed of metal oxide inclusions can induce arcing between the target surface and the plasma. The arcing can lead to production of excessive deposition material in the form of splats or blobs. Reducing the content of conductivity anomalies and strengthening the to-be-deposited material is seen to reduce production of such splats or blobs. Other splat limiting steps include smooth finishing of the target surface and low-stress ramp up of the plasma.
摘要翻译：公开了用于形成具有低缺陷密度的金属化膜的改进的用于铝或类似金属的DC_磁控溅射的靶。还公开了制造和使用这些靶的方法。诸如由金属氧化物夹杂物组成的电导率异常可以引起目标表面和等离子体之间的电弧。电弧会导致过剩的沉积材料以斑块或斑点的形式产生。减少电导率异常的含量和加强待沉积材料可以减少这种斑块或斑点的产生。其它限制步骤包括平滑地对目标表面进行精加工和等离子体的低应力升高。

6. 发明授权

US5539247A Selective metal via plug growth technology for deep sub-micrometer ULSI 失效
公开(公告)号：US5539247A
公开(公告)日：1996-07-23
申请号：US447870
申请日：1995-05-24
申请人： Robin W. Cheung , Seshadri Ramaswami , David F. Kyser
发明人： Robin W. Cheung , Seshadri Ramaswami , David F. Kyser
IPC分类号： H01L21/768 , H01L23/48
CPC分类号： H01L21/76879
摘要： Metal pillars (18) having diameters of less than about 1.0 .mu.m are grown in vias (16) in dielectric layers (14) between metal layers (12, 22) by a process comprising: (a) forming a first metal layer (12) at a first temperature and patterning the metal layer; (b) forming the dielectric layer to encapsulate the first patterned metal layer, the dielectric layer having a compressive stress of at least about 100 MegaPascal and being formed at a second temperature; (c) opening vias in the dielectric layer to exposed underlying portions of the patterned metal layer, the vias being less than about 1.0 .mu.m in diameter; (d) heating the semiconductor wafer at a temperature that is greater than either the first or second temperatures to induce growth of metal in the vias from the metal layer; and (e) forming the second metal layer (22) over the dielectric layer to make contact with the metal pillars.

7. 发明授权

US5365111A Stable local interconnect/active area silicide structure for VLSI applications 失效
标题翻译：用于VLSI应用的稳定的局部互连/有源区硅化物结构
公开(公告)号：US5365111A
公开(公告)日：1994-11-15
申请号：US995869
申请日：1992-12-23
申请人： Seshadri Ramaswami , Robin W. Cheung
发明人： Seshadri Ramaswami , Robin W. Cheung
IPC分类号： H01L21/28 , H01L21/3205 , H01L21/768 , H01L23/52 , H01L23/522 , H01L23/532 , H01L29/45 , H01L23/48 , H01L29/46 , H01L29/62 , H01L29/64
CPC分类号： H01L21/76889 , H01L23/53257 , H01L29/456 , H01L2924/0002 , Y10S148/019
摘要： A local interconnect silicide structure (30) for connecting silicon regions (16) to silicon regions (20) separated by oxide regions (24) comprises a first portion of titanium silicide/titanium nitride/titanium silicide contacting the silicon regions and a second portion of titanium/titanium nitride/titanium silicide contacting the oxide regions. The silicide structure is also useful for connecting source/drain regions (14) and polysilicon interconnects (28). Two separate heating steps are employed, separated by an etch step to form the interconnects (34, 36). The first heating step forms (a) titanium silicides with single or polycrystalline silicon, using a first titanium layer (30a) at the bottom of the silicide structure and (b) titanium silicides with amorphous silicon (30d), using a second titanium layer (30c) on top of the titanium nitride layer (30b) on which the amorphous silicon is deposited and then patterned. The second heating step, which is at a higher temperature than the first, converts all the titanium silicides to titanium disilicide.
摘要翻译：用于将硅区域（16）连接到由氧化物区域（24）分开的硅区域（20）的局部互连硅化物结构（30）包括与硅区域接触的钛硅化物/氮化钛/硅化钛的第一部分和第二部分钛/氮化钛/硅化钛与氧化物区域接触。硅化物结构也可用于连接源/漏区（14）和多晶硅互连（28）。采用两个单独的加热步骤，通过蚀刻步骤分离以形成互连（34,36）。第一加热步骤使用第一钛层（30a）在硅化物结构的底部形成（a）具有单个或多晶硅的硅化钛，和（b）具有非晶硅（30d）的硅化钛，使用第二钛层 30c）在其上沉积非晶硅的氮化钛层（30b）的顶部上，然后构图。在比第一加热步骤高的第二加热步骤将所有的钛硅化物转化成二硅化钛。

8. 发明申请

US20160064267A1 SEALING STRUCTURE FOR WORKPIECE TO SUBSTRATE BONDING IN A PROCESSING CHAMBER 审中-公开
标题翻译：用于在加工室中衬底粘结的工件的密封结构
公开(公告)号：US20160064267A1
公开(公告)日：2016-03-03
申请号：US14602885
申请日：2015-01-22
申请人： Chin Hock Toh , Tuck Foong Koh , Sriskantharajah Thirunavukarasu , Jern Sern Lew , Arvind Sundarrajan , Seshadri Ramaswami
发明人： Chin Hock Toh , Tuck Foong Koh , Sriskantharajah Thirunavukarasu , Jern Sern Lew , Arvind Sundarrajan , Seshadri Ramaswami
IPC分类号： H01L21/687 , H01J37/32 , C23C16/458
CPC分类号： H01L21/68757 , C23C16/4581 , H01J37/32513 , H01J37/32715 , H01L21/67126 , H01L21/68785
摘要： A sealing structure is between a workpiece or substrate and a carrier for plasma processing. In one example, a substrate carrier has a top surface for holding a substrate, the top surface having a perimeter and a resilient sealing ridge on the perimeter of the top surface to contact the substrate when the substrate is being carried on the carrier.
摘要翻译：密封结构在工件或基板与用于等离子体处理的载体之间。在一个示例中，衬底载体具有用于保持衬底的顶表面，顶表面具有周边和在顶表面的周边上的弹性密封脊，以在衬底被承载在载体上时与衬底接触。

9. 发明申请

US20150102467A1 METHOD OF DICED WAFER TRANSPORTATION 审中-公开
标题翻译： DICED WAFER运输方法
公开(公告)号：US20150102467A1
公开(公告)日：2015-04-16
申请号：US14576121
申请日：2014-12-18
申请人： Wei-Sheng Lei , Brad Eaton , Aparna Iyer , Saravjeet Singh , Todd Egan , Ajay Kumar , Seshadri Ramaswami
发明人： Wei-Sheng Lei , Brad Eaton , Aparna Iyer , Saravjeet Singh , Todd Egan , Ajay Kumar , Seshadri Ramaswami
IPC分类号： H01L23/32 , H01L21/78 , H01L27/04
CPC分类号： H01L23/32 , H01L21/463 , H01L21/47 , H01L21/475 , H01L21/561 , H01L21/6835 , H01L21/6836 , H01L21/78 , H01L21/82 , H01L27/04 , H01L2924/0002 , H01L2924/00
摘要： Methods of dicing semiconductor wafers, and transporting singulated die, are described. In an example, a method of dicing a wafer having a plurality of integrated circuits thereon involves dicing the wafer into a plurality of singulated dies disposed above a dicing tape. The method also involves forming a water soluble material layer over and between the plurality of singulated dies, above the dicing tape.
摘要翻译：描述了切割半导体晶片和输送单个模具的方法。在一个示例中，在其上划分具有多个集成电路的晶片的方法包括将晶片切割成设置在切割带上方的多个单片模具。该方法还涉及在切割胶带上方的多个分割模具之上和之间形成水溶性材料层。

10. 发明申请

US20140015109A1 METHOD OF DICED WAFER TRANSPORTATION 有权
标题翻译： DICED WAFER运输方法
公开(公告)号：US20140015109A1
公开(公告)日：2014-01-16
申请号：US13917973
申请日：2013-06-14
申请人： Wei-Sheng Lei , Brad Eaton , Aparna Iyer , Saravjeet Singh , Todd Egan , Ajay Kumar , Seshadri Ramaswami
发明人： Wei-Sheng Lei , Brad Eaton , Aparna Iyer , Saravjeet Singh , Todd Egan , Ajay Kumar , Seshadri Ramaswami
IPC分类号： H01L21/78
CPC分类号： H01L23/32 , H01L21/463 , H01L21/47 , H01L21/475 , H01L21/561 , H01L21/6835 , H01L21/6836 , H01L21/78 , H01L21/82 , H01L27/04 , H01L2924/0002 , H01L2924/00
摘要： Methods of dicing semiconductor wafers, and transporting singulated die, are described. In an example, a method of dicing a wafer having a plurality of integrated circuits thereon involves dicing the wafer into a plurality of singulated dies disposed above a dicing tape. The method also involves forming a water soluble material layer over and between the plurality of singulated dies, above the dicing tape.
摘要翻译：描述了切割半导体晶片和输送单个模具的方法。在一个示例中，在其上划分具有多个集成电路的晶片的方法包括将晶片切割成设置在切割带上方的多个单片模具。该方法还涉及在切割胶带上方的多个分割模具之上和之间形成水溶性材料层。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式