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1. 发明授权

US07610326B2 Arithmetic circuit for calculating a cumulative value as a result of parallel arithmetic processing 失效
标题翻译：用于计算作为并行算术处理结果的累积值的算术电路
公开(公告)号：US07610326B2
公开(公告)日：2009-10-27
申请号：US11078287
申请日：2005-03-14
申请人： Keisuke Korekado , Osamu Nomura , Atsushi Iwata , Takashi Morie
发明人： Keisuke Korekado , Osamu Nomura , Atsushi Iwata , Takashi Morie
IPC分类号： G06G7/00 , G06G7/02
CPC分类号： G06F1/02
摘要： An arithmetic circuit to calculate a cumulative value of results of parallel arithmetic processing, in which the increase of the circuit area for multiple-term arithmetic computation and the degradation of accuracy of holding of computation results in a short time can be prevented. The arithmetic circuit has plural analog arithmetic circuits to perform arithmetic processing based on input analog signals, a capacitor to hold a charge amount proportional to a total sum of results of computations by the plural analog arithmetic circuits, an analog-to-digital (A/D) conversion circuit to convert the charge amount stored in the capacitor to digital data, and a digital arithmetic circuit to calculate a cumulative value based on the converted digital data.
摘要翻译：可以防止用于计算多项算术计算的电路面积的增加和计算结果的保持精度的降低的并行运算处理的结果的累积值的运算电路。算术电路具有多个模拟运算电路，用于根据输入的模拟信号进行算术处理，保持与多个模拟运算电路的运算结果的总和成比例的电荷量的电容器，模数（A / D）转换电路以将存储在电容器中的电荷量转换为数字数据，以及数字运算电路，以基于转换的数字数据计算累积值。

2. 发明申请

US20050160130A1 Arithmetic circuit 失效
标题翻译：算术电路
公开(公告)号：US20050160130A1
公开(公告)日：2005-07-21
申请号：US11078287
申请日：2005-03-14
申请人： Keisuke Korekado , Osamu Nomura , Atsushi Iwata , Takashi Morie
发明人： Keisuke Korekado , Osamu Nomura , Atsushi Iwata , Takashi Morie
IPC分类号： G06F1/02
CPC分类号： G06F1/02
摘要： An arithmetic circuit to calculate a cumulative value of results of parallel arithmetic processing, in which the increase of the circuit area for multiple-term arithmetic computation and the degradation of accuracy of holding of computation results in a short time can be prevented. The arithmetic circuit has plural analog arithmetic circuits (1) to perform arithmetic processing based on input analog signals, a capacitor (2) to hold a charge amount proportional to a total sum of results of computations by the plural analog arithmetic circuits (1), an A/D conversion circuit (3) to convert the charge amount stored in the capacitor (2) to digital data, and a digital arithmetic circuit (4) to calculate a cumulative value based on the converted digital data.
摘要翻译：可以防止用于计算多项算术计算的电路面积的增加和计算结果的保持精度的降低的并行运算处理的结果的累积值的运算电路。算术电路具有多个模拟运算电路（1），用于基于输入的模拟信号进行运算处理，电容器（2）保持与多个模拟运算电路（1）的计算结果的总和成比例的电荷量，用于将存储在电容器（2）中的电荷量转换为数字数据的A / D转换电路（3）和数字运算电路（4），以基于转换的数字数据计算累积值。

3. 发明授权

US07747668B2 Product-sum operation circuit and method 有权
标题翻译：产品总和运算电路及方法
公开(公告)号：US07747668B2
公开(公告)日：2010-06-29
申请号：US11055283
申请日：2005-02-10
申请人： Osamu Nomura , Takashi Morie , Keisuke Korekado
发明人： Osamu Nomura , Takashi Morie , Keisuke Korekado
IPC分类号： G06F7/00
CPC分类号： G06F7/5443 , G06N3/063
摘要： A product-sum operation circuit includes a sorting block (4) which outputs a plurality of operand values x1, x2, . . . xi in descending or ascending order of magnitude, and an operation unit (1) which multiplies each operand value xi output from the sorting block (4) by a corresponding operand value Wi and calculates the accumulated sum of multiplication results.
摘要翻译：产品和运算电路包括输出多个操作数值x1，x2，...的排序块（4）。。。 xi按照降序或升序排列;以及操作单元（1），其将从分类块（4）输出的每个操作数值xi乘以相应的操作数值Wi，并计算乘法结果的累加和。

4. 发明申请

US20050138100A1 Product-sum operation circuit and method 有权
标题翻译：产品总和运算电路及方法
公开(公告)号：US20050138100A1
公开(公告)日：2005-06-23
申请号：US11055283
申请日：2005-02-10
申请人： Osamu Nomura , Takashi Morie , Keisuke Korekado
发明人： Osamu Nomura , Takashi Morie , Keisuke Korekado
IPC分类号： G06F7/24 , G06F7/38 , G06F7/544 , G06F17/10 , G06N3/063
CPC分类号： G06F7/5443 , G06N3/063
摘要： A product-sum operation circuit includes a sorting block (4) which outputs a plurality of operand values x1, x2, . . . xi in descending or ascending order of magnitude, and an operation unit (1) which multiplies each operand value xi output from the sorting block (4) by a corresponding operand value Wi and calculates the accumulated sum of multiplication results.
摘要翻译：产品和运算电路包括输出多个操作数值x1，x2，...的排序块（4）。。。 xi按照降序或升序排列;以及操作单元（1），其将从分类块（4）输出的每个操作数值xi乘以相应的操作数值Wi，并计算乘法结果的累加和。

5. 发明授权

US07272585B2 Operation circuit and operation control method thereof 有权
标题翻译：操作电路及其操作控制方法
公开(公告)号：US07272585B2
公开(公告)日：2007-09-18
申请号：US11434779
申请日：2006-05-17
申请人： Osamu Nomura , Takashi Morie , Teppei Nakano
发明人： Osamu Nomura , Takashi Morie , Teppei Nakano
IPC分类号： G06N3/00 , G06N3/02 , G06J1/00
CPC分类号： G06N3/049 , G06N3/063 , H03K7/08 , H03K9/08 , H03M5/08
摘要： A product-sum operation circuit includes a pulse width/digital conversion circuit (9) which converts a pulse signal having a pulse width representing an operand value into a digital signal, a sorting circuit (4) which outputs, in descending or ascending order of magnitude, a plurality of operand values Xi converted into digital signals by the pulse width/digital conversion circuit (9), and an accumulated sum circuit (1) which multiplies each operand value output from the sorting circuit (4) by a corresponding operand value Wi and calculates the accumulated sum of multiplication results. The pulse width/digital conversion circuit (9) includes a counter (10) which counts a clock and outputs a count value as a digital signal, and n trailing edge latch circuits (11-0-11-(n−1)) each of which latches a common count value output from the counter at the trailing edge of the input pulse signal.
摘要翻译：产品总和运算电路包括将具有表示操作数值的脉冲宽度的脉冲信号转换为数字信号的脉冲宽度/数字转换电路（9），分选电路（4），按照下列或者升序排列由脉冲宽度/数字转换电路（9）转换为数字信号的多个操作数值Xi以及将从分选电路（4）输出的每个操作数值乘以相应的操作数值的累积和电路（1） Wi并计算乘积结果的累加和。脉冲宽度/数字转换电路（9）包括对时钟进行计数的计数器（10），并输出作为数字信号的计数值，以及n个后沿锁存电路（11〜0-11〜（n-1））其在输入脉冲信号的后沿锁存从计数器输出的公共计数值。

6. 发明申请

US20060206555A1 Operation circuit and operation control method thereof 有权
标题翻译：操作电路及其操作控制方法
公开(公告)号：US20060206555A1
公开(公告)日：2006-09-14
申请号：US11434779
申请日：2006-05-17
申请人： Osamu Nomura , Takashi Morie , Teppei Nakano
发明人： Osamu Nomura , Takashi Morie , Teppei Nakano
IPC分类号： G06F7/38
CPC分类号： G06N3/049 , G06N3/063 , H03K7/08 , H03K9/08 , H03M5/08
摘要： A product-sum operation circuit includes a pulse width/digital conversion circuit (9) which converts a pulse signal having a pulse width representing an operand value into a digital signal, a sorting circuit (4) which outputs, in descending or ascending order of magnitude, a plurality of operand values Xi converted into digital signals by the pulse width/digital conversion circuit (9), and an accumulated sum circuit (1) which multiplies each operand value output from the sorting circuit (4) by a corresponding operand value Wi and calculates the accumulated sum of multiplication results. The pulse width/digital conversion circuit (9) includes a counter (10) which counts a clock and outputs a count value as a digital signal, and n trailing edge latch circuits (11-0-11-(n−1)) each of which latches a common count value output from the counter at the trailing edge of the input pulse signal.
摘要翻译：产品总和运算电路包括将具有表示操作数值的脉冲宽度的脉冲信号转换为数字信号的脉冲宽度/数字转换电路（9），分选电路（4），按照下列或者升序排列由脉冲宽度/数字转换电路（9）转换为数字信号的多个操作数值Xi以及将从分选电路（4）输出的每个操作数值乘以相应的操作数值的累积和电路（1） Wi并计算乘积结果的累加和。脉冲宽度/数字转换电路（9）包括对时钟进行计数的计数器（10），并输出作为数字信号的计数值，以及n个后沿锁存电路（11〜0-11〜（n-1））其在输入脉冲信号的后沿锁存从计数器输出的公共计数值。

7. 发明申请

US20050122238A1 Operation circuit and operation control method thereof 有权
标题翻译：操作电路及其操作控制方法
公开(公告)号：US20050122238A1
公开(公告)日：2005-06-09
申请号：US11036001
申请日：2005-01-18
申请人： Osamu Nomura , Takashi Morie , Teppei Nakano
发明人： Osamu Nomura , Takashi Morie , Teppei Nakano
IPC分类号： G06F7/544 , G06N3/04 , G06N3/063 , H03K7/08 , H03K9/08 , H03M1/82 , H03M5/08
CPC分类号： G06N3/049 , G06N3/063 , H03K7/08 , H03K9/08 , H03M5/08
摘要： A product-sum operation circuit includes a pulse width/digital conversion circuit (9) which converts a pulse signal having a pulse width representing an operand value into a digital signal, a sorting circuit (4) which outputs, in descending or ascending order of magnitude, a plurality of operand values Xi converted into digital signals by the pulse width/digital conversion circuit (9), and an accumulated sum circuit (1) which multiplies each operand value output from the sorting circuit (4) by a corresponding operand value Wi and calculates the accumulated sum of multiplication results. The pulse width/digital conversion circuit (9) includes a counter (10) which counts a clock and outputs a count value as a digital signal, and n trailing edge latch circuits (11-0-11-(n−1)) each of which latches a common count value output from the counter at the trailing edge of the input pulse signal.
摘要翻译：产品总和运算电路包括将具有表示操作数值的脉冲宽度的脉冲信号转换为数字信号的脉冲宽度/数字转换电路（9），分选电路（4），按照下列或者升序排列由脉冲宽度/数字转换电路（9）转换为数字信号的多个操作数值Xi以及将从分选电路（4）输出的每个操作数值乘以相应的操作数值的累积和电路（1） Wi并计算乘积结果的累加和。脉冲宽度/数字转换电路（9）包括对时钟进行计数并输出计数值作为数字信号的计数器（10），以及n个后沿锁存电路（11 - 0 - 11 - （n- 1））其在输入脉冲信号的后沿锁存从计数器输出的公共计数值。

8. 发明授权

US07120617B2 Operation circuit and operation control method thereof 有权
标题翻译：操作电路及其操作控制方法
公开(公告)号：US07120617B2
公开(公告)日：2006-10-10
申请号：US11036001
申请日：2005-01-18
申请人： Osamu Nomura , Takashi Morie , Teppei Nakano
发明人： Osamu Nomura , Takashi Morie , Teppei Nakano
IPC分类号： G06N3/00 , H03K23/00
CPC分类号： G06N3/049 , G06N3/063 , H03K7/08 , H03K9/08 , H03M5/08
摘要： A product-sum operation circuit includes a pulse width/digital conversion circuit (9) which converts a pulse signal having a pulse width representing an operand value into a digital signal, a sorting circuit (4) which outputs, in descending or ascending order of magnitude, a plurality of operand values Xi converted into digital signals by the pulse width/digital conversion circuit (9), and an accumulated sum circuit (1) which multiplies each operand value output from the sorting circuit (4) by a corresponding operand value Wi and calculates the accumulated sum of multiplication results. The pulse width/digital conversion circuit (9) includes a counter (10) which counts a clock and outputs a count value as a digital signal, and n trailing edge latch circuits (11-0–11-(n−1)) each of which latches a common count value output from the counter at the trailing edge of the input pulse signal.
摘要翻译：产品总和运算电路包括将具有表示操作数值的脉冲宽度的脉冲信号转换为数字信号的脉冲宽度/数字转换电路（9），分选电路（4），按照下列或者升序排列由脉冲宽度/数字转换电路（9）转换为数字信号的多个操作数值Xi以及将从分选电路（4）输出的每个操作数值乘以相应的操作数值的累积和电路（1） Wi并计算乘积结果的累加和。脉冲宽度/数字转换电路（9）包括对时钟进行计数的计数器（10），并输出作为数字信号的计数值，以及n个后沿锁存电路（11〜0-11〜（n-1））其在输入脉冲信号的后沿锁存从计数器输出的公共计数值。

9. 发明授权

US06661022B2 Information processing structures 失效
公开(公告)号：US06661022B2
公开(公告)日：2003-12-09
申请号：US09926698
申请日：2001-12-04
申请人： Takashi Morie , Atsushi Iwata , Makoto Nagata , Toshio Yamanaka , Tomohiro Matsuura
发明人： Takashi Morie , Atsushi Iwata , Makoto Nagata , Toshio Yamanaka , Tomohiro Matsuura
IPC分类号： H01L2906
CPC分类号： B82Y10/00 , G11C11/34 , G11C2216/08 , H01L29/7613 , H01L29/7888
摘要： An information processing structure is disclosed that is formed of single electron circuits each operating rapidly and stably by way of a single electron operation. The information processing structure includes a MOSFET (11), and a plurality of quantum dots (13) disposed immediately above a gate electrode (12) of the MOSFET and each of which is made of a microconductor or microsemiconductor of a nanometer scale in size. Between each of the quantum dots and the gate electrode is there formed an energy barrier that an electron is capable of directly tunneling. The total number of such electrons moved between the quantum dots and the gate electrode is used to represent information. In the structure, a power source electrode (14) is disposed in contact with the quantum dots and a pair of information electrodes (15) is disposed across a quantum dot in contact therewith for having electric potentials applied thereto, representing data of information. Between each of the quantum dots and the power source electrode is there also formed a potential barrier that an electron is capable of directly tunneling. A capacitive coupling is provided between the information electrodes in pair and the quantum dot between them to prevent movement of an electron between the quantum dot and the information electrodes, and an electron is rendered movable by the Coulomb blockade through the quantum dot between the power source electrode and the gate electrode in response to a relative electric potential determined at the information electrodes.

10. 发明授权

US07911369B2 Pipelined AD converter 有权
标题翻译：流水线AD转换器
公开(公告)号：US07911369B2
公开(公告)日：2011-03-22
申请号：US12600784
申请日：2008-08-21
申请人： Takashi Morie , Kazuo Matsukawa , Shiro Sakiyama , Shiro Dosho , Yusuke Tokunaga
发明人： Takashi Morie , Kazuo Matsukawa , Shiro Sakiyama , Shiro Dosho , Yusuke Tokunaga
IPC分类号： H03M1/38
CPC分类号： H03M1/0678 , H03M1/0695 , H03M1/44
摘要： A pipelined AD converter (1) includes a plurality of conversion stages (11, 11, . . . ). In each of the conversion stages, an analog-to-digital conversion circuit (101) converts an input voltage (Vin) from the preceding stage to a digital code (Dout). A digital-to-analog conversion circuit (102) converts the digital code obtained by the analog-to-digital conversion circuit to an intermediate voltage (Vda). A charge operation circuit (103) has: a capacitor section (C1, C2) for sampling the input voltage; and an amplifier section (104) for amplifying a mixed voltage of the input voltage sampled by the capacitor section and the intermediate voltage obtained by the digital-to-analog conversion circuit. The amplifier section (104) includes a plurality of op-amps (amp1, amp1, . . . ) having the same configuration and connected in parallel with each other.
摘要翻译：流水线式AD转换器（1）包括多个转换级（11,11 ...）。在每个转换级中，模数转换电路（101）将来自前级的输入电压（Vin）转换为数字代码（Dout）。数模转换电路（102）将由模数转换电路获得的数字代码转换为中间电压（Vda）。充电操作电路（103）具有用于对输入电压进行采样的电容器部（C1，C2）以及用于放大由电容器部分采样的输入电压和由数模转换电路获得的中间电压的混合电压的放大器部分（104）。放大器部分（104）包括具有相同配置并且彼此并联的多个运算放大器（amp1，amp1 ...）。

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