专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06661022B2 Information processing structures 失效
公开(公告)号：US06661022B2
公开(公告)日：2003-12-09
申请号：US09926698
申请日：2001-12-04
申请人： Takashi Morie , Atsushi Iwata , Makoto Nagata , Toshio Yamanaka , Tomohiro Matsuura
发明人： Takashi Morie , Atsushi Iwata , Makoto Nagata , Toshio Yamanaka , Tomohiro Matsuura
IPC分类号： H01L2906
CPC分类号： B82Y10/00 , G11C11/34 , G11C2216/08 , H01L29/7613 , H01L29/7888
摘要： An information processing structure is disclosed that is formed of single electron circuits each operating rapidly and stably by way of a single electron operation. The information processing structure includes a MOSFET (11), and a plurality of quantum dots (13) disposed immediately above a gate electrode (12) of the MOSFET and each of which is made of a microconductor or microsemiconductor of a nanometer scale in size. Between each of the quantum dots and the gate electrode is there formed an energy barrier that an electron is capable of directly tunneling. The total number of such electrons moved between the quantum dots and the gate electrode is used to represent information. In the structure, a power source electrode (14) is disposed in contact with the quantum dots and a pair of information electrodes (15) is disposed across a quantum dot in contact therewith for having electric potentials applied thereto, representing data of information. Between each of the quantum dots and the power source electrode is there also formed a potential barrier that an electron is capable of directly tunneling. A capacitive coupling is provided between the information electrodes in pair and the quantum dot between them to prevent movement of an electron between the quantum dot and the information electrodes, and an electron is rendered movable by the Coulomb blockade through the quantum dot between the power source electrode and the gate electrode in response to a relative electric potential determined at the information electrodes.

2. 发明授权

US07039536B2 Method and apparatus for analyzing a source current waveform in a semiconductor integrated circuit 失效
标题翻译：用于分析半导体集成电路中的源电流波形的方法和装置
公开(公告)号：US07039536B2
公开(公告)日：2006-05-02
申请号：US09977994
申请日：2001-10-17
申请人： Makoto Nagata , Atsushi Iwata
发明人： Makoto Nagata , Atsushi Iwata
IPC分类号： G06F17/00
CPC分类号： G06F17/5036 , G01R31/3004
摘要： The invention provides a method of analyzing a source current at a higher speed and an enhanced accuracy in a semiconductor integrated circuit including a digital circuit. The method to analyze a waveform of the source current, with consideration of re-distribution of charges throughout the digital circuit in the semiconductor integrated circuit, expressing the digital circuit with series of parasitic capacitors ΣCch, ↑ (nT) and ΣCch, ↓ (nT) to be charged and connected between the source and the ground lines. The capacitor series are calculated in time series based on the distribution of switching operations of the logic gates included in the digital circuit. An analysis model for determining the waveform of the source current in the digital circuit is obtained by connecting the parasitic capacitor series with a couple of respective parasitic impedances Zd and Zg of the source line and the ground line.
摘要翻译：本发明提供了一种在包括数字电路的半导体集成电路中以更高的速度和更高的精度来分析源电流的方法。考虑到在半导体集成电路中的整个数字电路中的电荷的再分配，分析源极电流的波形的方法，表示具有一系列寄生电容器的数字电路SigmaC＆lt; ch＆gt; nT）和SigmaC ch，↓（nT），以在源极和地线之间被充电和连接。基于包括在数字电路中的逻辑门的开关操作的分布，以时间序列计算电容器系列。用于确定数字电路中的源电流的波形的分析模型通过将寄生电容器系列与一对相应的寄生阻抗Z SUB和Z SUB连接在一起而获得源极线和地线。

3. 发明授权

US6144217A Low switching noise logic circuit 失效
标题翻译：低开关噪声逻辑电路
公开(公告)号：US6144217A
公开(公告)日：2000-11-07
申请号：US348584
申请日：1999-07-07
申请人： Atsushi Iwata , Makoto Nagata , Katsumasa Hijikata
发明人： Atsushi Iwata , Makoto Nagata , Katsumasa Hijikata
IPC分类号： H01L27/04 , H01L21/822 , H03K19/003 , H03K19/0948 , H03K17/16
CPC分类号： H03K19/00361
摘要： An analog-digital hybrid IC device for reducing cross-talk adds an electrostatic capacitance element to the power supply side and/or the ground side of a CMOS logic circuit forming the digital circuit part, connects a resistance between the electrostatic capacitance element and the terminal to which the electrostatic capacitance element was added, and buffers charging and discharging when the logic elements switch on and off to reduce noise produced by current peaks.
摘要翻译：用于减少串扰的模拟数字混合IC装置在形成数字电路部分的CMOS逻辑电路的电源侧和/或接地侧增加静电电容元件，连接静电电容元件与端子之间的电阻添加静电电容元件，并且当逻辑元件接通和断开时缓冲器充电和放电，以减少由电流峰值产生的噪声。

4. 发明授权

US6088490A Apparatus for processing two-dimensional information 失效
标题翻译：二维信息处理装置
公开(公告)号：US6088490A
公开(公告)日：2000-07-11
申请号：US47378
申请日：1998-03-25
申请人： Atsushi Iwata , Makoto Nagata
发明人： Atsushi Iwata , Makoto Nagata
IPC分类号： H04N1/21 , G06T1/20 , G06T7/60 , G06K7/00
CPC分类号： G06T1/20
摘要： A two-dimensional information processing apparatus comprises a plurality of unit cell circuits arranged in a tow-dimensional matrix and each including a detector for detecting information as predetermined part of two-dimensional information, a storage circuit for storing the information detected by the detector, and a signal processing circuit for generating a pulse width modulation signal which has a pulse width corresponding to the information detected or stored, a plurality of address lines extending in a direction of columns of the matrix, and each connected to those unit cell circuits which are included in a corresponding one of the columns, a plurality of bus lines extending in a direction of rows of the matrix, and each connected to those unit cell circuits which are included in a corresponding one of the rows, means for selecting at least one of the address lines and supplying, through the selected address line, a control signal for generating a pulse width modulation signal to those unit cell circuits which are included in the selected bus line, and means for selecting at least one of the bus lines and reading, through the selected bus line, at least one pulse width modulation signal. The control signal includes a ramp signal, and the pulse modulation signal rises when the voltage of the ramp signal starts to increase, and falls when the voltage of the ramp signal is identical to a voltage determined on the basis of the information detected by the detector.
摘要翻译：一种二维信息处理装置，包括：多维单位电路，以多维矩阵的形式排列，每一个都包含检测信息作为二维信息的预定部分的检测器;存储检测器检测出的信息的存储电路; 以及信号处理电路，用于产生具有与检测或存储的信息相对应的脉冲宽度的脉宽调制信号，沿矩阵列的方向延伸的多个地址线，并且每个连接到那些单元电路包括在对应的一列中，沿矩阵行的方向延伸的多个总线，并且每个连接到包括在相应的一行中的那些单元电路，用于选择以下各项中的至少一个的装置：地址线，并通过所选地址线提供用于产生脉宽调制信号的控制信号包括在所选择的总线中的那些单元电路，以及用于选择至少一个总线并通过所选择的总线读取至少一个脉冲宽度调制信号的装置。控制信号包括斜坡信号，并且当斜坡信号的电压开始增加时，脉冲调制信号上升，当斜坡信号的电压与基于由检测器检测到的信息确定的电压相同时，脉冲调制信号下降。

5. 发明授权

US5889424A Pulse width modulation operation circuit 失效
标题翻译：脉宽调制运算电路
公开(公告)号：US5889424A
公开(公告)日：1999-03-30
申请号：US18836
申请日：1998-02-04
申请人： Atsushi Iwata , Makoto Nagata
发明人： Atsushi Iwata , Makoto Nagata
IPC分类号： G06G7/161 , H03K9/08 , H03M1/50 , G06G7/12
CPC分类号： H03K9/08
摘要： The invention provides a pulse width modulation operation circuit for processing an m-bit pulse width modulation signal which is represented by a number n of sub pulse width modulation signals, where n is a divisor of m, characterized by comprising at least two equivalent pulse modulation operation circuits for individually processing the number n of sub pulse width modulation signals and outputting the processing results in the form of binary digital signals, and means for adding the binary digital signals from the pulse modulation operation circuits. The pulse modulation operation circuits include current pulse generating means for generating current pulses corresponding to the sub pulse width modulation signals, a current bus for transmitting the generated current pulses, and means for integrating the current pulses and converting the integrated current pulses into charges, and means for digitizing the sum of the charges to obtain digitized data. Alternatively, the pulse width modulation operation circuit comprises at least one pulse modulation operation circuit for processing the number n of sub pulse width modulation signals in a time-series manner and outputting the processing results in the form of binary digital signals.
摘要翻译：本发明提供了一种用于处理由n个子脉冲宽度调制信号表示的m位脉冲宽度调制信号的脉宽调制运算电路，其中n是m的除数，其特征在于包括至少两个等效脉冲调制用于单独处理子脉冲宽度调制信号的数量n的运算电路，并以二进制数字信号的形式输出处理结果，以及用于从脉冲调制运算电路相加二进制数字信号的装置。脉冲调制运算电路包括电流脉冲发生装置，用于产生对应于子脉冲宽度调制信号的电流脉冲，用于发送所产生的电流脉冲的电流总线，以及用于积分电流脉冲并将积分电流脉冲转换成电荷的装置，以及用于数字化费用总和以获得数字化数据的装置。或者，脉宽调制运算电路包括至少一个用于以时间序列方式处理子脉冲宽度调制信号数量n的脉冲调制运算电路，并以二进制数字信号的形式输出处理结果。

6. 发明授权

US6157672A Pulse modulation operation circuit 失效
标题翻译：脉冲调制运算电路
公开(公告)号：US6157672A
公开(公告)日：2000-12-05
申请号：US18837
申请日：1998-02-04
申请人： Atsushi Iwata , Makoto Nagata
发明人： Atsushi Iwata , Makoto Nagata
IPC分类号： G06G7/161 , H03M1/50 , H03K7/08 , H03K9/08 , G06G7/12
CPC分类号： H03M1/504 , H03M1/502
摘要： A pulse modulation operation circuit includes a current bus, a plurality of switch current sources connected parallel to each other and commonly connected to the current bus for generating current pulses corresponding to external input signals, charge conversion element connected to the current bus for integrating the current pulses and converting them into a charge, and an output for converting the charge into a binary digital signal and outputting the binary digital signal. Each pulse width modulation signal is input to a corresponding one of the switch current sources, which in turn generates a constant current for a period corresponding to the width of each pulse of the signal, to convert each signal pulse into a current pulse. The thus-obtained current pulses are added on the common current bus, thereby obtaining, by capacitive integration, a total charge Q.sub.total proportional to the sum of the widths of the current pulses. To this end, a reference charge counter circuit has a function for integration and a function for digitizing the total charge Q.sub.total in units of a reference charge Q.sub.std in real time.
摘要翻译：脉冲调制运算电路包括电流总线，多个彼此并联连接的开关电流源，并且共同连接到当前总线，用于产生对应于外部输入信号的电流脉冲;电荷转换元件连接到当前总线，用于对电流进行积分脉冲并将其转换成电荷，以及用于将电荷转换成二进制数字信号并输出二进制数字信号的输出。每个脉冲宽度调制信号被输入到相应的一个开关电流源，开关电流源又产生恒定电流一段与信号的每个脉冲宽度相对应的电流，以将每个信号脉冲转换成电流脉冲。这样获得的电流脉冲被加在公共电流总线上，从而通过电容积分获得与电流脉冲宽度之和成比例的总电荷Qtotal。为此，参考电荷计数器电路具有用于积分的功能和用于以基准电荷Qstd为单位实时地数字化总电荷Qtotal的功能。

7. 发明申请

US20140050627A1 OFF GAS PURIFICATION DEVICE 有权
标题翻译：关闭气体净化装置
公开(公告)号：US20140050627A1
公开(公告)日：2014-02-20
申请号：US14114108
申请日：2012-01-11
申请人： Takeshi Mende , Toshinori Okajima , Yasuyuki Banno , Makoto Nagata
发明人： Takeshi Mende , Toshinori Okajima , Yasuyuki Banno , Makoto Nagata
IPC分类号： F01N3/20
CPC分类号： F01N3/208 , B01D53/9418 , B01D53/944 , B01D53/9477 , B01D2255/1021 , B01D2255/1023 , B01D2255/50 , B01D2255/9155 , B01D2255/9202 , B01D2258/012 , B01J23/44 , B01J29/7215 , B01J35/006 , B01J35/023 , B01J35/04 , B01J37/0201 , B01J37/0242 , F01N3/035 , F01N3/103 , F01N3/2066 , F01N13/009 , F01N13/0097 , F01N2510/06 , F01N2510/068 , F01N2610/02 , Y02A50/2341 , Y02T10/24
摘要： An exhaust gas purification catalyst apparatus. The apparatus has a noble metal component for oxidizing NOx in an exhaust gas discharged from a diesel engine, a reducing agent spraying means for supplying the reducing agent selected from a urea component or an ammonia component, and a selective reduction catalyst (SCR) not comprising a noble metal for removing by reduction NOx by contacting with the reducing agent, in this order from the upstream side of an exhaust gas passage. Activity of the selective reduction catalyst (SCR) is maintained by setting that the noble metal component of the oxidation catalyst (DOC) comprises platinum and palladium, and ratio of platinum particles existing alone is 20% or less, or average particle diameter of the noble metal is 4 nm or larger, and by suppressing volatilization of platinum from the oxidation catalyst (DOC), even when catalyst bed temperature increases up to 900° C.
摘要翻译：废气净化催化剂装置。该装置具有用于氧化从柴油发动机排出的废气中的NOx的贵金属成分，用于供给选自尿素成分或氨成分的还原剂的还原剂喷射装置和不包含从废气通道的上游侧起依次通过与还原剂接触还原NOx除去的贵金属。通过设定氧化催化剂（DOC）的贵金属成分含有铂和钯，单独存在的铂粒子的比例为20％以下，或贵金属的平均粒径，可以维持选择还原催化剂（SCR）的活性金属为4nm以上，并且通过抑制铂从氧化催化剂（DOC）的挥发，即使催化剂床温度升高至900℃。

8. 发明申请

US20120164413A1 Inorganic Particle Composite Body and Method for Producing Inorganic Particle Composite Body 审中-公开
标题翻译：无机粒子复合体及其制备方法
公开(公告)号：US20120164413A1
公开(公告)日：2012-06-28
申请号：US13376008
申请日：2010-06-04
申请人： Makiko Hara , Makoto Nagata , Taiichi Sakaya , Naoko Sakaya
发明人： Makiko Hara , Makoto Nagata , Taiichi Sakaya , Naoko Sakaya
IPC分类号： B32B7/02 , B05D3/06 , B05D3/10
CPC分类号： B29C43/003 , B05D1/30 , B29C70/606 , B29C70/64 , B29K2023/12 , B29K2033/12 , B29K2067/003 , B29K2105/16 , B29K2509/00 , B29K2995/0024 , B29K2995/007 , B29K2995/0087 , B29K2995/0093 , C22C1/1026 , C22C1/1094 , C22C29/12 , C22C32/001 , Y10T428/24942
摘要： There is provided an inorganic particle composite body comprising a layer of a substrate formed of a plastically deformable solid material and an inorganic particle layer that is composed of inorganic particles that do not plastically deform under a condition under which the solid material plastically deforms, that contains gaps defined by the inorganic particles, and that adjoins the layer of the substrate, wherein part of the solid material is in at least part of the gaps in the inorganic particle layer. This inorganic particle composite body is produced by a method including a preparation step of preparing an inorganic particle structural body comprising a layer of a substrate formed of a plastically deformable solid material and an inorganic particle layer that is composed of inorganic particles that do not plastically deform under a condition under which the solid material plastically deforms, that contains gaps defined by the inorganic particles, and that adjoins the layer of the substrate; and a filling step of plastically deforming at least part of the solid material contained in the inorganic particle structural body, thereby filling at least part of the gaps in the inorganic particle layer with part of the plastically deformed solid material.
摘要翻译：提供了一种无机颗粒复合体，其包括由可塑性变形的固体材料形成的基材层和由固体材料塑性变形的条件下不会塑性变形的无机颗粒组成的无机颗粒层，其包含由无机颗粒限定的间隙，并且与衬底层相邻，其中固体材料的一部分在无机颗粒层的至少部分间隙中。该无机颗粒复合体是通过包括制备无机颗粒结构体的制备步骤的方法生产的，该无机颗粒结构体包括由可塑性变形的固体材料形成的基材层和由不会塑性变形的无机颗粒组成的无机颗粒层在固体材料塑性变形的条件下，其含有由无机颗粒限定的间隙，并且与基底层相邻; 以及使包含在无机颗粒结构体中的固体材料的至少一部分塑性变形的填充步骤，从而用部分塑性变形的固体材料填充无机颗粒层中的至少一部分间隙。

9. 发明申请

US20120114518A1 Method for Producing Inorganic Particle Composite Body 审中-公开
标题翻译：生产无机粒子复合体的方法
公开(公告)号：US20120114518A1
公开(公告)日：2012-05-10
申请号：US13375965
申请日：2010-06-04
申请人： Makiko Hara , Makoto Nagata , Taiichi Sakaya , Naoko Sakaya
发明人： Makiko Hara , Makoto Nagata , Taiichi Sakaya , Naoko Sakaya
IPC分类号： B22F3/02
CPC分类号： B29C43/003 , B05D1/30 , B29C70/606 , B29C70/64 , B29K2023/12 , B29K2033/12 , B29K2067/003 , B29K2105/16 , B29K2509/00 , B29K2995/0024 , B29K2995/007 , B29K2995/0087 , B29K2995/0093 , C22C1/1026 , C22C1/1094 , C22C29/12 , C22C32/001 , Y10T428/24942
摘要： A method for producing an inorganic particle composite body formed of a mixture of a plastically deformable metal, and inorganic particles that do not plastically deform under a condition under which the metal plastically deforms, wherein the method comprises: a step of preparing an inorganic particles structural body that is formed of a mixture of the metal and the inorganic particles and that contains a vacant space therein, and a step of plastically deforming the metal in the structural body.
摘要翻译：一种无机粒子复合体的制造方法，其特征在于，在所述金属塑性变形的条件下，由塑性变形金属和不会塑性变形的无机粒子的混合物构成的无机粒子复合体的制造方法包括：由金属和无机颗粒的混合物形成并且在其中包含空的空间的主体以及使结构体中的金属发生塑性变形的步骤。

10. 发明授权

US08144045B2 Timing signal generator circuit for use in signal waveform measurement system for measuring multi-channel on-chip signals flowing on VLSI 有权
标题翻译：定时信号发生器电路，用于信号波形测量系统，用于测量在VLSI上流动的多通道片上信号
公开(公告)号：US08144045B2
公开(公告)日：2012-03-27
申请号：US12828641
申请日：2010-07-01
申请人： Makoto Nagata , Takushi Hashida
发明人： Makoto Nagata , Takushi Hashida
IPC分类号： H03M1/82
CPC分类号： H03K5/2472 , G01R31/31922
摘要： A timing signal generator circuit includes a DA converter converting an input digital value into an analog voltage, and a VT converter converting the analog voltage into a corresponding delay time. The DA converter includes a current source circuit, which supplies a current (n×Is) (“n” is a number corresponding to the input digital value) selected from a total supply current (N×Is) as a current Iout to the resistors, and supplies the remaining current (N−n)×Is as a current Idump to the resistors, outputs a voltage across the resistors as an analog voltage Vdac, and outputs a voltage across the resistor as a reset voltage Vreset. The VT converter charges the integration capacitor with a constant current from the constant current source by using the reset voltage as an initial voltage, and outputs a timing signal when the integral voltage exceeds the analog voltage.
摘要翻译：定时信号发生器电路包括将输入数字值转换为模拟电压的DA转换器和将模拟电压转换为相应的延迟时间的VT转换器。 DA转换器包括电流源电路，其将从总供电电流（N×Is）中选择的电流（n×Is）（“n”为与输入数字值对应的数字）作为电流Iout提供给电阻器，并将剩余电流（N-n）×Is作为当前Idump提供给电阻器，将电阻器两端的电压作为模拟电压Vdac输出，并将电阻两端的电压输出为复位电压Vreset。 VT转换器通过使用复位电压作为初始电压从恒流源以恒定电流对积分电容器充电，当积分电压超过模拟电压时，输出定时信号。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式