专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20050160130A1 Arithmetic circuit 失效
标题翻译：算术电路
公开(公告)号：US20050160130A1
公开(公告)日：2005-07-21
申请号：US11078287
申请日：2005-03-14
申请人： Keisuke Korekado , Osamu Nomura , Atsushi Iwata , Takashi Morie
发明人： Keisuke Korekado , Osamu Nomura , Atsushi Iwata , Takashi Morie
IPC分类号： G06F1/02
CPC分类号： G06F1/02
摘要： An arithmetic circuit to calculate a cumulative value of results of parallel arithmetic processing, in which the increase of the circuit area for multiple-term arithmetic computation and the degradation of accuracy of holding of computation results in a short time can be prevented. The arithmetic circuit has plural analog arithmetic circuits (1) to perform arithmetic processing based on input analog signals, a capacitor (2) to hold a charge amount proportional to a total sum of results of computations by the plural analog arithmetic circuits (1), an A/D conversion circuit (3) to convert the charge amount stored in the capacitor (2) to digital data, and a digital arithmetic circuit (4) to calculate a cumulative value based on the converted digital data.
摘要翻译：可以防止用于计算多项算术计算的电路面积的增加和计算结果的保持精度的降低的并行运算处理的结果的累积值的运算电路。算术电路具有多个模拟运算电路（1），用于基于输入的模拟信号进行运算处理，电容器（2）保持与多个模拟运算电路（1）的计算结果的总和成比例的电荷量，用于将存储在电容器（2）中的电荷量转换为数字数据的A / D转换电路（3）和数字运算电路（4），以基于转换的数字数据计算累积值。

2. 发明授权

US07610326B2 Arithmetic circuit for calculating a cumulative value as a result of parallel arithmetic processing 失效
标题翻译：用于计算作为并行算术处理结果的累积值的算术电路
公开(公告)号：US07610326B2
公开(公告)日：2009-10-27
申请号：US11078287
申请日：2005-03-14
申请人： Keisuke Korekado , Osamu Nomura , Atsushi Iwata , Takashi Morie
发明人： Keisuke Korekado , Osamu Nomura , Atsushi Iwata , Takashi Morie
IPC分类号： G06G7/00 , G06G7/02
CPC分类号： G06F1/02
摘要： An arithmetic circuit to calculate a cumulative value of results of parallel arithmetic processing, in which the increase of the circuit area for multiple-term arithmetic computation and the degradation of accuracy of holding of computation results in a short time can be prevented. The arithmetic circuit has plural analog arithmetic circuits to perform arithmetic processing based on input analog signals, a capacitor to hold a charge amount proportional to a total sum of results of computations by the plural analog arithmetic circuits, an analog-to-digital (A/D) conversion circuit to convert the charge amount stored in the capacitor to digital data, and a digital arithmetic circuit to calculate a cumulative value based on the converted digital data.
摘要翻译：可以防止用于计算多项算术计算的电路面积的增加和计算结果的保持精度的降低的并行运算处理的结果的累积值的运算电路。算术电路具有多个模拟运算电路，用于根据输入的模拟信号进行算术处理，保持与多个模拟运算电路的运算结果的总和成比例的电荷量的电容器，模数（A / D）转换电路以将存储在电容器中的电荷量转换为数字数据，以及数字运算电路，以基于转换的数字数据计算累积值。

3. 发明申请

US20050138100A1 Product-sum operation circuit and method 有权
标题翻译：产品总和运算电路及方法
公开(公告)号：US20050138100A1
公开(公告)日：2005-06-23
申请号：US11055283
申请日：2005-02-10
申请人： Osamu Nomura , Takashi Morie , Keisuke Korekado
发明人： Osamu Nomura , Takashi Morie , Keisuke Korekado
IPC分类号： G06F7/24 , G06F7/38 , G06F7/544 , G06F17/10 , G06N3/063
CPC分类号： G06F7/5443 , G06N3/063
摘要： A product-sum operation circuit includes a sorting block (4) which outputs a plurality of operand values x1, x2, . . . xi in descending or ascending order of magnitude, and an operation unit (1) which multiplies each operand value xi output from the sorting block (4) by a corresponding operand value Wi and calculates the accumulated sum of multiplication results.
摘要翻译：产品和运算电路包括输出多个操作数值x1，x2，...的排序块（4）。。。 xi按照降序或升序排列;以及操作单元（1），其将从分类块（4）输出的每个操作数值xi乘以相应的操作数值Wi，并计算乘法结果的累加和。

4. 发明授权

US07747668B2 Product-sum operation circuit and method 有权
标题翻译：产品总和运算电路及方法
公开(公告)号：US07747668B2
公开(公告)日：2010-06-29
申请号：US11055283
申请日：2005-02-10
申请人： Osamu Nomura , Takashi Morie , Keisuke Korekado
发明人： Osamu Nomura , Takashi Morie , Keisuke Korekado
IPC分类号： G06F7/00
CPC分类号： G06F7/5443 , G06N3/063
摘要： A product-sum operation circuit includes a sorting block (4) which outputs a plurality of operand values x1, x2, . . . xi in descending or ascending order of magnitude, and an operation unit (1) which multiplies each operand value xi output from the sorting block (4) by a corresponding operand value Wi and calculates the accumulated sum of multiplication results.
摘要翻译：产品和运算电路包括输出多个操作数值x1，x2，...的排序块（4）。。。 xi按照降序或升序排列;以及操作单元（1），其将从分类块（4）输出的每个操作数值xi乘以相应的操作数值Wi，并计算乘法结果的累加和。

5. 发明申请

US20060206555A1 Operation circuit and operation control method thereof 有权
标题翻译：操作电路及其操作控制方法
公开(公告)号：US20060206555A1
公开(公告)日：2006-09-14
申请号：US11434779
申请日：2006-05-17
申请人： Osamu Nomura , Takashi Morie , Teppei Nakano
发明人： Osamu Nomura , Takashi Morie , Teppei Nakano
IPC分类号： G06F7/38
CPC分类号： G06N3/049 , G06N3/063 , H03K7/08 , H03K9/08 , H03M5/08
摘要： A product-sum operation circuit includes a pulse width/digital conversion circuit (9) which converts a pulse signal having a pulse width representing an operand value into a digital signal, a sorting circuit (4) which outputs, in descending or ascending order of magnitude, a plurality of operand values Xi converted into digital signals by the pulse width/digital conversion circuit (9), and an accumulated sum circuit (1) which multiplies each operand value output from the sorting circuit (4) by a corresponding operand value Wi and calculates the accumulated sum of multiplication results. The pulse width/digital conversion circuit (9) includes a counter (10) which counts a clock and outputs a count value as a digital signal, and n trailing edge latch circuits (11-0-11-(n−1)) each of which latches a common count value output from the counter at the trailing edge of the input pulse signal.
摘要翻译：产品总和运算电路包括将具有表示操作数值的脉冲宽度的脉冲信号转换为数字信号的脉冲宽度/数字转换电路（9），分选电路（4），按照下列或者升序排列由脉冲宽度/数字转换电路（9）转换为数字信号的多个操作数值Xi以及将从分选电路（4）输出的每个操作数值乘以相应的操作数值的累积和电路（1） Wi并计算乘积结果的累加和。脉冲宽度/数字转换电路（9）包括对时钟进行计数的计数器（10），并输出作为数字信号的计数值，以及n个后沿锁存电路（11〜0-11〜（n-1））其在输入脉冲信号的后沿锁存从计数器输出的公共计数值。

6. 发明申请

US20050122238A1 Operation circuit and operation control method thereof 有权
标题翻译：操作电路及其操作控制方法
公开(公告)号：US20050122238A1
公开(公告)日：2005-06-09
申请号：US11036001
申请日：2005-01-18
申请人： Osamu Nomura , Takashi Morie , Teppei Nakano
发明人： Osamu Nomura , Takashi Morie , Teppei Nakano
IPC分类号： G06F7/544 , G06N3/04 , G06N3/063 , H03K7/08 , H03K9/08 , H03M1/82 , H03M5/08
CPC分类号： G06N3/049 , G06N3/063 , H03K7/08 , H03K9/08 , H03M5/08
摘要： A product-sum operation circuit includes a pulse width/digital conversion circuit (9) which converts a pulse signal having a pulse width representing an operand value into a digital signal, a sorting circuit (4) which outputs, in descending or ascending order of magnitude, a plurality of operand values Xi converted into digital signals by the pulse width/digital conversion circuit (9), and an accumulated sum circuit (1) which multiplies each operand value output from the sorting circuit (4) by a corresponding operand value Wi and calculates the accumulated sum of multiplication results. The pulse width/digital conversion circuit (9) includes a counter (10) which counts a clock and outputs a count value as a digital signal, and n trailing edge latch circuits (11-0-11-(n−1)) each of which latches a common count value output from the counter at the trailing edge of the input pulse signal.
摘要翻译：产品总和运算电路包括将具有表示操作数值的脉冲宽度的脉冲信号转换为数字信号的脉冲宽度/数字转换电路（9），分选电路（4），按照下列或者升序排列由脉冲宽度/数字转换电路（9）转换为数字信号的多个操作数值Xi以及将从分选电路（4）输出的每个操作数值乘以相应的操作数值的累积和电路（1） Wi并计算乘积结果的累加和。脉冲宽度/数字转换电路（9）包括对时钟进行计数并输出计数值作为数字信号的计数器（10），以及n个后沿锁存电路（11 - 0 - 11 - （n- 1））其在输入脉冲信号的后沿锁存从计数器输出的公共计数值。

7. 发明授权

US07120617B2 Operation circuit and operation control method thereof 有权
标题翻译：操作电路及其操作控制方法
公开(公告)号：US07120617B2
公开(公告)日：2006-10-10
申请号：US11036001
申请日：2005-01-18
申请人： Osamu Nomura , Takashi Morie , Teppei Nakano
发明人： Osamu Nomura , Takashi Morie , Teppei Nakano
IPC分类号： G06N3/00 , H03K23/00
CPC分类号： G06N3/049 , G06N3/063 , H03K7/08 , H03K9/08 , H03M5/08
摘要： A product-sum operation circuit includes a pulse width/digital conversion circuit (9) which converts a pulse signal having a pulse width representing an operand value into a digital signal, a sorting circuit (4) which outputs, in descending or ascending order of magnitude, a plurality of operand values Xi converted into digital signals by the pulse width/digital conversion circuit (9), and an accumulated sum circuit (1) which multiplies each operand value output from the sorting circuit (4) by a corresponding operand value Wi and calculates the accumulated sum of multiplication results. The pulse width/digital conversion circuit (9) includes a counter (10) which counts a clock and outputs a count value as a digital signal, and n trailing edge latch circuits (11-0–11-(n−1)) each of which latches a common count value output from the counter at the trailing edge of the input pulse signal.
摘要翻译：产品总和运算电路包括将具有表示操作数值的脉冲宽度的脉冲信号转换为数字信号的脉冲宽度/数字转换电路（9），分选电路（4），按照下列或者升序排列由脉冲宽度/数字转换电路（9）转换为数字信号的多个操作数值Xi以及将从分选电路（4）输出的每个操作数值乘以相应的操作数值的累积和电路（1） Wi并计算乘积结果的累加和。脉冲宽度/数字转换电路（9）包括对时钟进行计数的计数器（10），并输出作为数字信号的计数值，以及n个后沿锁存电路（11〜0-11〜（n-1））其在输入脉冲信号的后沿锁存从计数器输出的公共计数值。

8. 发明授权

US07272585B2 Operation circuit and operation control method thereof 有权
标题翻译：操作电路及其操作控制方法
公开(公告)号：US07272585B2
公开(公告)日：2007-09-18
申请号：US11434779
申请日：2006-05-17
申请人： Osamu Nomura , Takashi Morie , Teppei Nakano
发明人： Osamu Nomura , Takashi Morie , Teppei Nakano
IPC分类号： G06N3/00 , G06N3/02 , G06J1/00
CPC分类号： G06N3/049 , G06N3/063 , H03K7/08 , H03K9/08 , H03M5/08
摘要： A product-sum operation circuit includes a pulse width/digital conversion circuit (9) which converts a pulse signal having a pulse width representing an operand value into a digital signal, a sorting circuit (4) which outputs, in descending or ascending order of magnitude, a plurality of operand values Xi converted into digital signals by the pulse width/digital conversion circuit (9), and an accumulated sum circuit (1) which multiplies each operand value output from the sorting circuit (4) by a corresponding operand value Wi and calculates the accumulated sum of multiplication results. The pulse width/digital conversion circuit (9) includes a counter (10) which counts a clock and outputs a count value as a digital signal, and n trailing edge latch circuits (11-0-11-(n−1)) each of which latches a common count value output from the counter at the trailing edge of the input pulse signal.
摘要翻译：产品总和运算电路包括将具有表示操作数值的脉冲宽度的脉冲信号转换为数字信号的脉冲宽度/数字转换电路（9），分选电路（4），按照下列或者升序排列由脉冲宽度/数字转换电路（9）转换为数字信号的多个操作数值Xi以及将从分选电路（4）输出的每个操作数值乘以相应的操作数值的累积和电路（1） Wi并计算乘积结果的累加和。脉冲宽度/数字转换电路（9）包括对时钟进行计数的计数器（10），并输出作为数字信号的计数值，以及n个后沿锁存电路（11〜0-11〜（n-1））其在输入脉冲信号的后沿锁存从计数器输出的公共计数值。

9. 发明授权

US09098909B2 Three-dimensional distance measurement apparatus, three-dimensional distance measurement method, and non-transitory computer-readable storage medium 有权
标题翻译：三维距离测量装置，三维距离测量方法和非暂时计算机可读存储介质
公开(公告)号：US09098909B2
公开(公告)日：2015-08-04
申请号：US13412738
申请日：2012-03-06
申请人： Osamu Nomura
发明人： Osamu Nomura
IPC分类号： G06T7/00 , G01B11/02 , G01B11/25
CPC分类号： G06T7/0057 , G01B11/026 , G01B11/25 , G06T7/521 , G06T2207/10028
摘要： A three-dimensional distance measurement apparatus comprising: a distance information calculation unit configured to calculate distance information of a measurement object based on a captured image of the measurement object on which pattern light is projected; and a local pattern setting unit configured to adaptively set a spatial resolution of measurement points of the pattern light for each local region, wherein the local pattern setting unit sets the spatial resolution of the measurement points of the pattern light based on information about an arithmetic amount of the distance information calculation unit.
摘要翻译：一种三维距离测量装置，包括：距离信息计算单元，被配置为基于投射有图案光的测量对象的拍摄图像来计算测量对象的距离信息; 以及局部图案设定单元，被配置为针对每个局部区域自适应地设置图案光的测量点的空间分辨率，其中所述局部图案设置单元基于关于算术量的信息来设置所述图案光的测量点的空间分辨率的距离信息计算单元。

10. 发明申请

US20120327224A1 INFORMATION PROCESSING APPARATUS AND METHOD FOR CONTROLLING THE SAME 有权
标题翻译：信息处理装置及其控制方法
公开(公告)号：US20120327224A1
公开(公告)日：2012-12-27
申请号：US13582116
申请日：2011-03-07
申请人： Osamu Nomura , Masakazu Matsugu
发明人： Osamu Nomura , Masakazu Matsugu
IPC分类号： H04N7/18
CPC分类号： B25J9/1671
摘要： An information processing apparatus includes an imaging unit and is capable of setting arrangement of a structural member of a robot system which works based on an image captured by the imaging unit. The information processing apparatus includes an arrangement unit configured to arrange a virtual object corresponding to the structural member in a virtual space corresponding to a working space of the robot system, a first acquisition unit configured to acquire a virtual space image in the virtual space which corresponds to the captured image and in which the virtual object is arranged, and a second acquisition unit configured to acquire an evaluation value indicating adaptation of arrangement of the virtual object to the work of the robot system based on the virtual space image.
摘要翻译：信息处理设备包括成像单元，并且能够基于由成像单元捕获的图像来设置机器人系统的结构构件的布置。该信息处理装置包括：配置单元，被配置为将与结构构件相对应的虚拟对象布置在与机器人系统的工作空间对应的虚拟空间中;第一获取单元，被配置为获取虚拟空间中的虚拟空间图像以及第二获取单元，被配置为基于虚拟空间图像获取指示虚拟对象的布置适应于机器人系统的工作的评估值。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式