专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20050139946A1 Photosensitive semiconductor package and method for fabricating the same 失效
标题翻译：光敏半导体封装及其制造方法
公开(公告)号：US20050139946A1
公开(公告)日：2005-06-30
申请号：US10959786
申请日：2004-10-05
申请人： Chia-Yu Hung , Chien-Ping Huang , Ke-Chuan Yang
发明人： Chia-Yu Hung , Chien-Ping Huang , Ke-Chuan Yang
IPC分类号： H01L23/28 , H01L23/48
CPC分类号： H01L27/14625 , H01L27/14618 , H01L27/14683 , H01L2224/32245 , H01L2224/48091 , H01L2224/4824 , H01L2224/48247 , H01L2224/8592 , H01L2924/00014
摘要： A photosensitive semiconductor package and a method for fabricating the same are proposed. The package includes a carrier having a first surface, an opposite second surface, and an opening penetrating the carrier; a photosensitive chip having an active surface and a non-active surface, wherein a plurality of bond pads are formed close to edges of the active surface, and the chip is mounted via corner positions of its active surface to the second surface of the carrier, with the bond pads being exposed via the opening; a plurality of bonding wires formed in the opening, for electrically connecting the bond pads of the chip to the first surface of the carrier; a light-penetrable unit attached to the active surface of the chip and received in the opening; and an encapsulant for encapsulating the bonding wires and peripheral sides of the chip to seal the opening.
摘要翻译：提出了一种光敏半导体封装及其制造方法。该包装包括具有第一表面，相对的第二表面和穿透载体的开口的载体; 具有活性表面和非活性表面的感光芯片，其中多个接合焊盘形成在靠近有源表面的边缘处，并且芯片通过其有源表面的拐角位置安装到载体的第二表面，接合垫通过开口露出; 形成在所述开口中的多个接合线，用于将所述芯片的接合焊盘电连接到所述载体的所述第一表面; 附着在芯片的活动表面并容纳在开口中的可透光单元; 以及用于封装芯片的接合线和周边的密封剂以密封开口。

2. 发明申请

US20080157344A1 Heat dissipation semiconductor pakage 审中-公开
标题翻译：散热半导体贴片
公开(公告)号：US20080157344A1
公开(公告)日：2008-07-03
申请号：US11732866
申请日：2007-04-04
申请人： Chin-Te Chen , Ke-Chuan Yang , Chung-Hsing Ko
发明人： Chin-Te Chen , Ke-Chuan Yang , Chung-Hsing Ko
IPC分类号： H01L23/34
CPC分类号： H01L23/4334 , H01L23/3121 , H01L24/48 , H01L24/97 , H01L2224/16225 , H01L2224/32245 , H01L2224/48227 , H01L2224/73253 , H01L2224/97 , H01L2924/00011 , H01L2924/00014 , H01L2924/01015 , H01L2924/01033 , H01L2924/181 , H01L2924/19041 , H01L2924/3025 , H01L2224/81 , H01L2224/0401 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A heat dissipation semiconductor package is disclosed according to the present invention. The heat dissipation semiconductor package comprises: a substrate that has a plurality of solder pads and at least one ground pad; a semiconductor chip that is mounted on the substrate and electrically connects to the solder pads; a plurality of passive elements that are mounted on the solder pads of the substrate; at least one metal bump or passive element of zero resistance, which are mounted on the at least one ground pad of the substrate; and a heat sink, which is capable of being mounted on the passive elements, and the at least one passive element of zero resistance or the metal bump, and the heat sink is electrically connecting to the at least one passive element of zero resistance or the metal bump, and then is further electrically coupling with the at least one ground pad of the substrate to form a ground return circuit, thus provides a shielding effect on electromagnetic interference (EMI).
摘要翻译：根据本发明公开了散热半导体封装。散热半导体封装包括：具有多个焊盘和至少一个接地焊盘的基板; 半导体芯片，其安装在所述基板上并电连接到所述焊盘; 多个无源元件，其安装在所述基板的所述焊盘上; 至少一个金属凸块或零电阻的无源元件，其安装在所述衬底的所述至少一个接地焊盘上; 以及散热器，其能够安装在无源元件上，以及至少一个零电阻的无源元件或金属凸块，并且散热器电连接到零电阻的至少一个无源元件或者金属凸块，然后进一步与衬底的至少一个接地焊盘电耦合以形成接地返回电路，从而对电磁干扰（EMI）提供屏蔽效应。

3. 发明申请

US20080142955A1 Heat-dissipating structure and heat-dissipating semiconductor package having the same 有权
标题翻译：散热结构及其散热半导体封装
公开(公告)号：US20080142955A1
公开(公告)日：2008-06-19
申请号：US12001612
申请日：2007-12-11
申请人： Chin-Te Chen , Ke-Chuan Yang , Chang-Fu Lin
发明人： Chin-Te Chen , Ke-Chuan Yang , Chang-Fu Lin
IPC分类号： H01L23/373
CPC分类号： H01L23/367 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2224/73253 , H01L2924/00011 , H01L2924/00014 , H01L2924/3011 , H01L2924/00 , H01L2224/0401
摘要： A heat-dissipating structure and a heat-dissipating semiconductor package having the same are disclosed in the present invention. The heat-dissipating semiconductor package includes a chip carrier, a flip chip semiconductor chip attached and electrically connected to the chip carrier, and a heat sink bonded to the flip chip semiconductor chip via a thermal interface material, such as a solder material, wherein a groove is formed on the heat sink around the bonding area of the thermal interface material, and a blocking layer, such as a metal oxide layer, is formed on the surface of the groove to reduce the wetting capability of the thermal interface material, thus further prevents the thermal interface material from wetting the groove in the fusion process performed the thermal interface material, therefore, it ensures the thermal interface material has sufficient thickness for forming solder bonding between the heat sink and the flip chip semiconductor chip.
摘要翻译：在本发明中公开了一种散热结构和具有该散热结构的散热半导体封装。散热半导体封装包括芯片载体，安装并电连接到芯片载体的倒装芯片半导体芯片，以及通过诸如焊料材料的热界面材料接合到倒装芯片半导体芯片的散热器，其中a 在热界面材料的接合区域周围的散热器上形成凹槽，并且在凹槽的表面上形成诸如金属氧化物层的阻挡层，以降低热界面材料的润湿能力，因此进一步防止热界面材料在进行热界面材料的熔融过程中润湿槽，因此，确保热界面材料具有足够的厚度，用于在散热器和倒装芯片半导体芯片之间形成焊接。

4. 发明申请

US20060017173A1 Flip-chip semiconductor package with lead frame and method for fabricating the same 有权
标题翻译：带引线框的倒装芯片半导体封装及其制造方法
公开(公告)号：US20060017173A1
公开(公告)日：2006-01-26
申请号：US10965093
申请日：2004-10-13
申请人： Chi-Chuan Wu , Ke-Chuan Yang
发明人： Chi-Chuan Wu , Ke-Chuan Yang
IPC分类号： H01L23/48 , H01L21/50
CPC分类号： H01L21/4828 , H01L23/3107 , H01L23/49548 , H01L2224/16 , H01L2224/16245 , H01L2924/00011 , H01L2924/00014 , H01L2924/01322 , H01L2924/01327 , H01L2924/15151 , H01L2924/00 , H01L2224/0401
摘要： A flip-chip semiconductor package with a lead frame and a method for fabricating the same are provided. The lead frame has a plurality of leads, each lead having an upper surface, a lower surface, and an inner end directed toward the center of the lead frame. A recessed portion is formed on the upper surface of the inner end of each lead, making the inner end shaped as a stepped structure. The depth of the recessed portion is equal to a height of a reflow-collapsed solder bump that is for electrically connecting a chip to the lead. At least one chip is electrically connected to the leads in a flip-chip manner via a plurality of solder bumps bonded to the recessed portions. An encapsulation body is formed to encapsulate the lead frame, chip and solder bumps, with the lower surfaces of the leads being exposed from the encapsulation body.
摘要翻译：提供具有引线框架的倒装芯片半导体封装及其制造方法。引线框架具有多个引线，每个引线具有上表面，下表面和指向引线框架的中心的内端。在每个引线的内端的上表面上形成凹部，使内端形成阶梯状。凹部的深度等于用于将芯片电连接到引线的回流塌陷的焊料凸块的高度。至少一个芯片通过多个焊接到凹部的焊料凸块以倒装芯片方式与引线电连接。形成封装体以封装引线框架，芯片和焊料凸块，引线的下表面从封装体露出。

5. 发明授权

US07863731B2 Heat-dissipating structure and heat-dissipating semiconductor package having the same 有权
标题翻译：散热结构及其散热半导体封装
公开(公告)号：US07863731B2
公开(公告)日：2011-01-04
申请号：US12001612
申请日：2007-12-11
申请人： Chin-Te Chen , Ke-Chuan Yang , Chang-Fu Lin
发明人： Chin-Te Chen , Ke-Chuan Yang , Chang-Fu Lin
IPC分类号： H01L23/10
CPC分类号： H01L23/367 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2224/73253 , H01L2924/00011 , H01L2924/00014 , H01L2924/3011 , H01L2924/00 , H01L2224/0401
摘要： A heat-dissipating structure and a heat-dissipating semiconductor package having the same are disclosed in the present invention. The heat-dissipating semiconductor package includes a chip carrier, a flip chip semiconductor chip attached and electrically connected to the chip carrier, and a heat sink bonded to the flip chip semiconductor chip via a thermal interface material, such as a solder material, wherein a groove is formed on the heat sink around the bonding area of the thermal interface material, and a blocking layer, such as a metal oxide layer, is formed on the surface of the groove to reduce the wetting capability of the thermal interface material, thus further prevents the thermal interface material from wetting the groove in the fusion process performed the thermal interface material, therefore, it ensures the thermal interface material has sufficient thickness for forming solder bonding between the heat sink and the flip chip semiconductor chip.
摘要翻译：在本发明中公开了一种散热结构和具有该散热结构的散热半导体封装。散热半导体封装包括芯片载体，安装并电连接到芯片载体的倒装芯片半导体芯片，以及通过诸如焊料材料的热界面材料接合到倒装芯片半导体芯片的散热器，其中a 在热界面材料的接合区域周围的散热器上形成凹槽，并且在凹槽的表面上形成诸如金属氧化物层的阻挡层，以降低热界面材料的润湿能力，因此进一步防止热界面材料在进行热界面材料的熔融过程中润湿槽，因此，确保热界面材料具有足够的厚度，用于在散热器和倒装芯片半导体芯片之间形成焊接。

6. 发明授权

US06821876B2 Fabrication method of strengthening flip-chip solder bumps 有权
标题翻译：加强倒装焊料凸块的制作方法
公开(公告)号：US06821876B2
公开(公告)日：2004-11-23
申请号：US10400349
申请日：2003-03-26
申请人： Ke-Chuan Yang
发明人： Ke-Chuan Yang
IPC分类号： H01L2144
CPC分类号： H01L24/13 , H01L24/11 , H01L2224/05001 , H01L2224/05026 , H01L2224/05572 , H01L2224/056 , H01L2224/1147 , H01L2224/13099 , H01L2224/131 , H01L2924/0001 , H01L2924/00014 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2224/05099
摘要： A fabrication method for strengthening flip-chip solder bumps is provided to form a solder bump on a UBM (under bump metallurgy) structure formed over a semiconductor chip, which can prevent the UBM structure against oxidation and contamination and also enhance bondability between the solder bump and UBM structure, thereby improving reliability for packaging the semiconductor chip. This fabrication method is characterized in that before forming the solder bump, a dielectric layer made of BCB (benzo-cyclo-butene) or polyimide is deposited on the UBM structure, and used to protect the UBM structure against oxidation and contamination. Further, before forming the solder bump, a plasma-etching process is performed to remove the dielectric layer; the plasma-etching process is environmental-friendly without having to use a chemical solvent.
摘要翻译：提供了一种用于加强倒装焊料凸块的制造方法，以在半导体芯片上形成的UBM（凸块下金属冶金）结构上形成焊料凸块，这可以防止UBM结构抗氧化和污染，并且还增强了焊料凸块和UBM结构，从而提高了封装半导体芯片的可靠性。该制造方法的特征在于，在形成焊料凸块之前，在UBM结构上沉积由BCB（苯并环丁烯）或聚酰亚胺制成的电介质层，并用于保护UBM结构免受氧化和污染。此外，在形成焊料凸块之前，进行等离子体蚀刻工艺以去除电介质层; 等离子体蚀刻工艺是环境友好的，而不必使用化学溶剂。

7. 发明授权

US06774499B1 Non-leaded semiconductor package and method of fabricating the same 有权
标题翻译：非铅半导体封装及其制造方法
公开(公告)号：US06774499B1
公开(公告)日：2004-08-10
申请号：US10437562
申请日：2003-05-13
申请人： Ke-Chuan Yang
发明人： Ke-Chuan Yang
IPC分类号： H01L2348
CPC分类号： H01L21/568 , H01L21/6835 , H01L23/3121 , H01L23/5389 , H01L24/24 , H01L24/48 , H01L24/82 , H01L25/0657 , H01L2221/68345 , H01L2224/05599 , H01L2224/24051 , H01L2224/24145 , H01L2224/24225 , H01L2224/24226 , H01L2224/45099 , H01L2224/48091 , H01L2224/82001 , H01L2224/82106 , H01L2224/85399 , H01L2225/06524 , H01L2225/06551 , H01L2225/06582 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/181 , H01L2924/18162 , H01L2924/00012 , H01L2224/45015 , H01L2924/207
摘要： A non-leaded semiconductor package and method of fabricating the same is proposed, which can be used for the fabrication of a non-leaded type of semiconductor package, such as a CQFN (Carrierless Quad Flat No-lead) package. The proposed semiconductor packaging technology is characterized by the use of a metal plate as provisional chip carrier during fabrication and by the use of RDL (Redistribution Layer) technology to provide internal electrical interconnections between the I/O pads of the packaged chip and the non-leaded external electrical contacts. These features allow the fabrication of the CQFN package to be implemented without the use of bonding wires for internal electrical connections and without the use of substrate as a permanent chip carrier.
摘要翻译：提出了一种非引线半导体封装及其制造方法，其可用于制造诸如CQFN（无载四方扁平无引线）封装的非引线型半导体封装。所提出的半导体封装技术的特征在于在制造期间使用金属板作为临时芯片载体，并且通过使用RDL（再分配层）技术来提供封装芯片的I / O焊盘和非封装芯片之间的内部电互连，引导外部电气触点。这些特征允许在不使用用于内部电连接的接合线并且不使用衬底作为永久性芯片载体的情况下实现CQFN封装的制造。

8. 发明授权

US06692629B1 Flip-chip bumbing method for fabricating solder bumps on semiconductor wafer 有权
标题翻译：用于在半导体晶片上制造焊料凸块的倒装芯片方式
公开(公告)号：US06692629B1
公开(公告)日：2004-02-17
申请号：US09656843
申请日：2000-09-07
申请人： Chih-Shun Chen , Po-Hao Yuan , Shih-Kuang Chiu , Feng-Lung Chien , Ke-Chuan Yang
发明人： Chih-Shun Chen , Po-Hao Yuan , Shih-Kuang Chiu , Feng-Lung Chien , Ke-Chuan Yang
IPC分类号： C25D502
CPC分类号： H01L24/03 , C25D7/12 , H01L21/2885 , H01L24/11 , H01L2224/0401 , H01L2224/13099 , H01L2924/01013 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/14 , H01L2924/181 , H01L2924/00
摘要： A flip-chip bumping method is proposed for the fabrication of solder bumps on a semiconductor wafer for flip-chip application. The proposed flip-chip bumping method is intended for use on a semiconductor wafer predefined with a plurality of chip regions which are delimited from each other by a predefined cutting line and each of which is formed with a plurality of aluminum or copper based bond pads, and is characterized in the provision of a plating bus over and along the cutting line and connected to each bond pad. By means of this plating bus, the required UBM (Under Bump Metallization) fabrication and solder-bump fabrication can be both carried out through plating. Since plating process is considerably lower in cost than sputtering process and etching process, the proposed flip-chip bumping method can be more cost-effective to implement than prior art.
摘要翻译：提出了用于在用于倒装芯片应用的半导体晶片上制造焊料凸块的倒装芯片凸块方法。所提出的倒装芯片凸块方法旨在用于预定有多个芯片区域的半导体晶片，该多个芯片区域由预定的切割线彼此界定，并且每个芯片区域形成有多个铝或铜基键合焊盘，并且其特征在于在切割线上并沿切割线设置电镀母线并连接到每个接合焊盘。通过这种电镀母线，所需的UBM（低品位金属化）制造和焊料凸块制造都可以通过电镀进行。由于电镀工艺的成本比溅射工艺和蚀刻工艺低得多，因此与现有技术相比，提出的倒装芯片凸块方法可以更具成本效益。

9. 发明授权

US07999189B2 Circuit board structure and method for fabricating the same 有权
标题翻译：电路板结构及其制造方法
公开(公告)号：US07999189B2
公开(公告)日：2011-08-16
申请号：US12218891
申请日：2008-07-18
申请人： Chin-Te Chen , Ke-Chuan Yang , Hung-Ming Chang
发明人： Chin-Te Chen , Ke-Chuan Yang , Hung-Ming Chang
IPC分类号： H05K1/09
CPC分类号： H01L23/49816 , H01L23/49822 , H01L23/49838 , H01L2924/0002 , H05K1/114 , H05K3/108 , H05K3/3452 , H05K3/4644 , H05K2201/09236 , H05K2201/09436 , H05K2203/025 , H05K2203/0733 , Y10T29/49149 , H01L2924/00
摘要： A circuit board structure and a method for fabricating the same are disclosed, including providing a core board having conductive traces and solder pads respectively formed thereon, wherein width of the solder pads corresponds to that of the conductive traces, and pitch between adjacent solder pads is made wide enough to allow multiple conductive traces to pass through; forming on the core board an insulating layer with openings for exposing the solder pads therefrom; forming on the insulating layer a plurality of extending pads electrically connected to the solder pads respectively, wherein the projection area of the extending pads is larger than that of the corresponding solder pads and covers conductive traces adjacent to the corresponding solder pads. Thus, more conductive traces are allowed to pass between adjacent solder pads and meanwhile, the extending pads provide an effective solder ball wetting area for achieving good solder joints and sufficient height after collapse.
摘要翻译：公开了一种电路板结构及其制造方法，包括提供具有分别形成在其上的导电迹线和焊盘的芯板，其中焊盘的宽度对应于导电迹线的宽度，相邻焊盘之间的间距是足够宽以允许多个导电迹线通过; 在所述芯板上形成具有用于从其露出焊盘的开口的绝缘层; 在所述绝缘层上形成分别电连接到所述焊盘的多个延伸焊盘，其中所述延伸焊盘的所述投影区域大于相应焊接焊盘的所述投影区域并且覆盖与相应焊盘相邻的导电迹线。因此，允许更多的导电迹线在相邻焊盘之间通过，同时，延伸焊盘提供有效的焊球润湿区域，以实现良好的焊点和崩溃后的足够的高度。

10. 发明授权

US07084474B2 Photosensitive semiconductor package and method for fabricating the same 失效
标题翻译：光敏半导体封装及其制造方法
公开(公告)号：US07084474B2
公开(公告)日：2006-08-01
申请号：US10959786
申请日：2004-10-05
申请人： Chia-Yu Hung , Chien-Ping Huang , Ke-Chuan Yang
发明人： Chia-Yu Hung , Chien-Ping Huang , Ke-Chuan Yang
IPC分类号： H01L31/0232 , H01L31/0203
CPC分类号： H01L27/14625 , H01L27/14618 , H01L27/14683 , H01L2224/32245 , H01L2224/48091 , H01L2224/4824 , H01L2224/48247 , H01L2224/8592 , H01L2924/00014
摘要： A photosensitive semiconductor package and a method for fabricating the same are proposed. The package includes a carrier having a first surface, an opposite second surface, and an opening penetrating the carrier; a photosensitive chip having an active surface and a non-active surface, wherein a plurality of bond pads are formed close to edges of the active surface, and the chip is mounted via corner positions of its active surface to the second surface of the carrier, with the bond pads being exposed via the opening; a plurality of bonding wires formed in the opening, for electrically connecting the bond pads of the chip to the first surface of the carrier; a light-penetrable unit attached to the active surface of the chip and received in the opening; and an encapsulant for encapsulating the bonding wires and peripheral sides of the chip to seal the opening.
摘要翻译：提出了一种光敏半导体封装及其制造方法。该包装包括具有第一表面，相对的第二表面和穿透载体的开口的载体; 具有活性表面和非活性表面的感光芯片，其中多个接合焊盘形成在靠近有源表面的边缘处，并且芯片通过其有源表面的拐角位置安装到载体的第二表面，接合垫通过开口露出; 形成在所述开口中的多个接合线，用于将所述芯片的接合焊盘电连接到所述载体的所述第一表面; 附着在芯片的活动表面并容纳在开口中的可透光单元; 以及用于封装芯片的接合线和周边的密封剂以密封开口。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式