专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5094967A Method for manufacturing semiconductor device having a non-volatile memory cell and logic regions by using a CVD second insulating film 失效
标题翻译：使用CVD第二绝缘膜制造具有非易失性存储单元和逻辑区域的半导体器件的方法
公开(公告)号：US5094967A
公开(公告)日：1992-03-10
申请号：US620701
申请日：1990-12-03
申请人： Kazuyoshi Shinada , Masayuki Yoshida , Takahide Mizutani , Naoki Hanada
发明人： Kazuyoshi Shinada , Masayuki Yoshida , Takahide Mizutani , Naoki Hanada
IPC分类号： H01L21/82 , H01L21/8234 , H01L21/8247 , H01L27/088 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11526 , H01L21/82 , H01L27/115 , H01L27/11539 , Y10S148/138
摘要： A method for manufacturing a semiconductor substrate device having a non-volatile memory cell region and a logic region including MOS transistors. A first insulating film and a first electrode layer are formed on a semiconductor substrate. Only those portions of the first insulating film and first electrode layer which are located in the logic region are removed, without removing those portions of the first insulating film and first electrode layer which are located in the non-volatile memory cell region. A sacrificial film is deposited for insulation over the entire surface of the memory cell region and logic region, and then a resist film is coated on the sacrificial film. Subsequently, impurity ions are implanted into a desired channel region located in the logic region. The resist film and sacrificial film are removed, and thereafter a second insulating film and a second electrode layer are formed.

2. 发明授权

US5200636A Semiconductor device having E.sup.2 PROM and EPROM in one chip 失效
标题翻译：具有一个芯片中的E2PROM和EPROM的半导体器件
公开(公告)号：US5200636A
公开(公告)日：1993-04-06
申请号：US594173
申请日：1990-10-10
申请人： Teruo Uemura , Takahide Mizutani , Naoki Hanada , Tatsuo Mori , Kazuyoshi Shinada
发明人： Teruo Uemura , Takahide Mizutani , Naoki Hanada , Tatsuo Mori , Kazuyoshi Shinada
IPC分类号： H01L21/8247 , H01L27/105 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11541
摘要： An E.sup.2 PROM and an EPROM are formed on the same substrate. An E.sup.2 PROM memory cell has a floating gate and a control gate. A tunnel insulating film is formed between the floating gate and source/drain regions, thereby constituting a memory cell of an "FLOTOX" type. An EPROM memory cell has a floating gate and a control gate, thus constituting a memory cell of an "SAMOS" type.

3. 发明授权

US06002609A Semiconductor device having a security circuit for preventing illegal access 失效
标题翻译：具有用于防止非法访问的安全电路的半导体装置
公开(公告)号：US06002609A
公开(公告)日：1999-12-14
申请号：US111484
申请日：1998-07-08
申请人： Kazuyoshi Shinada
发明人： Kazuyoshi Shinada
IPC分类号： G01R31/28 , G06F12/14 , G11C16/02 , G11C16/22 , G11C29/02 , H01L21/3205 , H01L21/66 , H01L21/822 , H01L21/8247 , H01L23/52 , H01L27/04 , H01L27/10 , H01L27/115 , G11C16/04 , G11C7/00 , G11C29/00
CPC分类号： G11C16/22 , G06F12/1433
摘要： A testing pad is connected to an EEPROM through a wiring layer of a security circuit and a test circuit, while a testing pad is connected to the EEPROM through a wiring different from the wiring layer and the test circuit. A polysilicon pattern is connected to the wiring layer, and an n-type diffusion region is connected to the wiring. A tunnel insulation film having a thickness of about 100 .ANG. is formed between the polysilicon pattern and the n-type diffusion region. After a test for the function and stored information of the EEPROM is completed, a voltage, which is not lower than a predetermined voltage applied during the test, is applied between the testing pads to break the tunnel insulation film, thereby making the polysilicon pattern and n-type diffusion region conductive.
摘要翻译：测试垫通过安全电路和测试电路的布线层连接到EEPROM，而测试垫通过不同于布线层和测试电路的布线连接到EEPROM。多晶硅图案连接到布线层，并且n型扩散区域连接到布线。在多晶硅图案和n型扩散区域之间形成厚度约为100的隧道绝缘膜。在EEPROM的功能和存储信息的测试完成之后，在测试焊盘之间施加不低于在测试期间施加的预定电压的电压，以破坏隧道绝缘膜，从而使多晶硅图案和 n型扩散区导电。

4. 发明授权

US4464128A Seal arrangement between an outdrive unit and a hull of a vessel 失效
标题翻译：外部装置和船体的密封装置
公开(公告)号：US4464128A
公开(公告)日：1984-08-07
申请号：US320691
申请日：1981-11-12
申请人： Kinichi Aso , Kazuyoshi Shinada
发明人： Kinichi Aso , Kazuyoshi Shinada
IPC分类号： B63H21/30 , B63B43/00 , B63H5/07 , B63H20/04 , B63H23/04 , F16J15/52 , B63H5/12
CPC分类号： B63H5/07 , B63H20/04 , B63H23/04 , B63B43/00 , B63H2005/075 , B63H21/305 , Y10S277/919
摘要： This invention discloses a seal arrangement between an outdrive unit and a hull of a vessel, comprising an outdrive unit connected to an engine and mounted on a bed of the hull, the outdrive unit projecting downward through an opening in the hull; a diaphragm seal fixed to the hull and the outdrive unit for sealing a space between the hull and the outdrive unit; an annular seal flange projecting above the diaphragm seal from the bed toward the outdrive unit; and a ring seal arranged between the outdrive unit and the seal flange for sealing a space therebetween; characterized in that; both ends of the ring seal are fastened to the outdrive unit and the seal flange, respectively. A water sensor connected to a warning device is arranged in a space between the diaphragm seal and the ring seal.
摘要翻译：本发明公开了一种外部驱动装置和船体的密封装置，包括连接到发动机并安装在船体的床上的驱动装置，外驱装置向下突出穿过船体中的开口; 固定到船体的隔膜密封件和用于密封船体和外部驱动单元之间的空间的超速单元; 环形密封凸缘，其从所述床朝向所述外驱单元突出于所述隔膜密封件上方; 以及环形密封件，其布置在所述外驱动单元和所述密封凸缘之间，用于密封其间的空间; 其特征在于：环形密封件的两端分别固定在外驱装置和密封法兰上。连接到警告装置的水传感器布置在隔膜密封件和环形密封件之间的空间中。

5. 发明申请

US20050136597A1 Method of manufacturing semiconductor device including nonvolatile memory 失效
标题翻译：包括非易失性存储器的半导体器件的制造方法
公开(公告)号：US20050136597A1
公开(公告)日：2005-06-23
申请号：US10961084
申请日：2004-10-12
申请人： Kazuyoshi Shinada , Akira Kimitsuka
发明人： Kazuyoshi Shinada , Akira Kimitsuka
IPC分类号： H01L21/8247 , H01L21/336 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11521 , H01L27/115 , H01L27/11524
摘要： There is provided a method of manufacturing a semiconductor device including a nonvolatile memory including forming an element isolation area surrounding an element area in a semiconductor substrate doped with a first type conductive impurity, forming a gate insulating film on the element area, forming selectively a cap film on the gate insulating film, burying selectively with a mask film surrounding the cap film on the gate insulating film, forming a tunnel window by removing selectively the cap film, forming an impurity diffusion layer in a surface region of the semiconductor substrate underneath the gate insulating film by introducing a second type conductive impurity using the mask film as a mask, removing the gate insulating film in the tunnel window, forming a tunnel insulating film in the tunnel window, forming a floating gate electrode film, an inter-gate electrode film, and a control gate electrode film on the tunnel insulating film, and forming a source-drain in the semiconductor substrate to interpose a surface region of the semiconductor substrate beneath the control gate electrode film by introducing the second type conductive impurity into the surface region using the control gate electrode film as a mask.
摘要翻译：提供一种制造包括非易失性存储器的半导体器件的方法，包括在掺杂有第一类型导电杂质的半导体衬底中形成围绕元件区域的元件隔离区域，在元件区域上形成栅极绝缘膜，选择性地形成帽在栅极绝缘膜上形成膜，在栅极绝缘膜上选择性地掩盖围绕盖膜的掩模膜，通过选择性地去除盖膜形成隧道窗，在栅极下方的半导体衬底的表面区域中形成杂质扩散层通过使用掩模膜作为掩模引入第二类导电杂质的绝缘膜，去除隧道窗中的栅极绝缘膜，在隧道窗中形成隧道绝缘膜，形成浮栅电极膜，栅极间电极膜，以及在隧道绝缘膜上的控制栅电极膜，并在半沟形成源极漏极通过使用控制栅电极膜作为掩模将第二类导电杂质引入到表面区域中，将半导体衬底的表面区域设置在控制栅电极膜的下方。

6. 发明授权

US4504332A Method of making a bipolar transistor 失效
标题翻译：制造双极晶体管的方法
公开(公告)号：US4504332A
公开(公告)日：1985-03-12
申请号：US374232
申请日：1982-05-03
申请人： Kazuyoshi Shinada
发明人： Kazuyoshi Shinada
IPC分类号： H01L29/73 , H01L21/20 , H01L21/3215 , H01L21/331 , H01L29/732 , H01L21/225 , H01L21/265 , H01L21/28
CPC分类号： H01L29/66287 , H01L21/02381 , H01L21/02532 , H01L21/02639 , H01L21/32155 , H01L29/7325 , Y10S438/969
摘要： This invention provides a method for manufacturing a bipolar transistor which comprises steps of selectively forming in the surface of a semiconductor substrate an embedded layer of a conductivity type opposite to that of the substrate, covering the substrate with an insulating layer doped, at the surface thereof with an impurity in the superficial region thereof, removing by etching the insulating layer to form an opening portion through which part of the embedded layer is exposed, simultaneously forming by epitaxial growth a single-crystal semiconductor layer of the same conductivity type as that of the embedded layer on the embedded layer at the opening portion and a polycrystalline semiconductor layer on the insulating layer, diffusing by heating the impurity in the insulating layer into the polycrystalline semiconductor layer to provide a conductivity type opposite to that of the single-crystal semiconductor layer, and successively forming an internal base region and an emitter region in the single-crystal semiconductor layer. The invention also provided a bipolar transistor manufactured by the aforementioned method.
摘要翻译：本发明提供了一种制造双极晶体管的方法，包括以下步骤：在半导体衬底的表面上选择性地形成与衬底相反的导电类型的嵌入层，在衬底的表面上覆盖掺杂有绝缘层的衬底在其表面区域具有杂质，通过蚀刻绝缘层去除以形成嵌入层的一部分暴露的开口部分，同时通过外延生长形成与所述绝缘层相同的导电类型的单晶半导体层在开口部分的嵌入层上的嵌入层和绝缘层上的多晶半导体层，通过将绝缘层中的杂质加热到多晶半导体层中以提供与单晶半导体层相反的导电类型而扩散，并依次形成内基区和发射极 ion在单晶半导体层。本发明还提供了通过上述方法制造的双极晶体管。

7. 发明授权

US4338139A Method of forming Schottky-I.sup.2 L devices by implantation and laser bombardment 失效
标题翻译：通过注入和激光轰击形成肖特基I2L器件的方法
公开(公告)号：US4338139A
公开(公告)日：1982-07-06
申请号：US210749
申请日：1980-11-26
申请人： Kazuyoshi Shinada
发明人： Kazuyoshi Shinada
IPC分类号： H01L21/266 , H01L21/768 , H01L21/8226 , H01L21/263 , H01L21/285 , H01L29/48
CPC分类号： H01L21/76888 , H01L21/266 , H01L21/8226 , Y10S148/092 , Y10S148/093
摘要： A method for manufacturing a semiconductor device having a Schottky junction which comprises a process for burying first and second regions of a second conductivity type spaced from each other in a semiconductor body of a first conductivity type, a process for locally disposing a first interconnection layer made of a metal on a surface region of the semiconductor body facing the first region, a process for forming an insulating film on the surface of the first interconnection layer by subjecting the surface to anodic oxidation, a process for ion-implanting an impurity of the second conductivity type into the semiconductor body except a portion thereof under the first interconnection layer at such an energy level that the impurity may reach the first and second regions, a process for activating the ion-implanted layer by applying a laser beam thereto, and a process for forming a second interconnection layer connected with the activated layer by covering the whole surface of the semiconductor body with a metal and patterning the metal.
摘要翻译：一种用于制造具有肖特基结的半导体器件的方法，该半导体器件包括在第一导电类型的半导体本体中相互隔开的第二导电类型的第一和第二区域的掩埋工艺，用于局部地布置第一互连层的工艺在半导体主体的面向第一区域的表面区域上的金属，通过对表面进行阳极氧化在第一互连层的表面上形成绝缘膜的工艺，用于离子注入第二区域的杂质的工艺导电类型进入半导体本体，除了第一互连层下方的部分，杂质可以到达第一和第二区域的能级，通过施加激光束来激活离子注入层的工艺，以及工艺用于通过覆盖半圆形的整个表面来形成与活化层连接的第二互连层具有金属的导体和图案化金属。

8. 发明授权

US07115471B2 Method of manufacturing semiconductor device including nonvolatile memory 失效
标题翻译：包括非易失性存储器的半导体器件的制造方法
公开(公告)号：US07115471B2
公开(公告)日：2006-10-03
申请号：US10961084
申请日：2004-10-12
申请人： Kazuyoshi Shinada , Akira Kimitsuka
发明人： Kazuyoshi Shinada , Akira Kimitsuka
IPC分类号： H01L21/336
CPC分类号： H01L27/11521 , H01L27/115 , H01L27/11524
摘要： There is provided a method of manufacturing a semiconductor device including a nonvolatile memory including forming an element isolation area surrounding an element area in a semiconductor substrate doped with a first type conductive impurity, forming a gate insulating film on the element area, forming selectively a cap film on the gate insulating film, burying selectively with a mask film surrounding the cap film on the gate insulating film, forming a tunnel window by removing selectively the cap film, forming an impurity diffusion layer in a surface region of the semiconductor substrate underneath the gate insulating film by introducing a second type conductive impurity using the mask film as a mask, removing the gate insulating film in the tunnel window, forming a tunnel insulating film in the tunnel window, forming a floating gate electrode film, an inter-gate electrode film, and a control gate electrode film on the tunnel insulating film, and forming a source-drain in the semiconductor substrate to interpose a surface region of the semiconductor substrate beneath the control gate electrode film by introducing the second type conductive impurity into the surface region using the control gate electrode film as a mask.
摘要翻译：提供一种制造包括非易失性存储器的半导体器件的方法，包括在掺杂有第一类型导电杂质的半导体衬底中形成围绕元件区域的元件隔离区域，在元件区域上形成栅极绝缘膜，选择性地形成帽在栅极绝缘膜上形成膜，在栅极绝缘膜上选择性地掩盖围绕盖膜的掩模膜，通过选择性地去除盖膜形成隧道窗，在栅极下方的半导体衬底的表面区域中形成杂质扩散层通过使用掩模膜作为掩模引入第二类导电杂质的绝缘膜，去除隧道窗中的栅极绝缘膜，在隧道窗中形成隧道绝缘膜，形成浮栅电极膜，栅极间电极膜，以及在隧道绝缘膜上的控制栅电极膜，并在半沟形成源极漏极通过使用控制栅电极膜作为掩模将第二类导电杂质引入到表面区域中，将半导体衬底的表面区域设置在控制栅电极膜的下方。

9. 发明授权

US06478646B1 Drive device of inboard and outboard engines 有权
标题翻译：内侧和外侧发动机的驱动装置
公开(公告)号：US06478646B1
公开(公告)日：2002-11-12
申请号：US09647999
申请日：2000-11-21
申请人： Teruhito Fukuoka , Yuji Hashimoto , Kazuyoshi Shinada
发明人： Teruhito Fukuoka , Yuji Hashimoto , Kazuyoshi Shinada
IPC分类号： B63H2336
CPC分类号： B63H23/08 , B63B43/00 , B63B2043/006 , B63H5/07 , B63H21/386 , B63H23/04 , B63H23/32 , B63H2005/075
摘要： A drive of inboard-and-outboard engines, wherein a drive gear unit (10) meshing with driven gears (25, 26) disposed on the upper end side of a drive shaft (28) disposed generally in vertical direction is formed slidably in a direction perpendicular to the drive shaft (28), whereby the drive gear unit (10) can be operated slidably from the outside of an upper unit (9) located at the top of an outer drive unit (5) disposed inside a hull (1).
摘要翻译：内侧和外侧发动机的驱动器，其中，与设置在大致垂直方向设置的驱动轴（28）的上端侧的从动齿轮（25,26）啮合的驱动齿轮单元（10）可滑动地形成在方向垂直于驱动轴（28），由此驱动齿轮单元（10）能够从设置在船体（1）内部的外部驱动单元（5）的顶部的上部单元（9）的外部可滑动地操作）。

10. 发明授权

US4597824A Method of producing semiconductor device 失效
标题翻译：半导体器件的制造方法
公开(公告)号：US4597824A
公开(公告)日：1986-07-01
申请号：US670010
申请日：1984-11-09
申请人： Kazuyoshi Shinada , Masaki Sato
发明人： Kazuyoshi Shinada , Masaki Sato
IPC分类号： H01L21/033 , H01L21/225 , H01L21/336 , H01L29/10 , H01L29/78 , H01L21/306 , B44C1/22 , C03C15/00 , C03C25/06
CPC分类号： H01L29/6659 , H01L21/0337 , H01L21/2255 , H01L29/1083 , H01L29/78 , H01L29/7836
摘要： A method of producing a MOS transistor of LDD structure with p(n) type pockets. A doped oxide film in which impurities such as phosphorus and impurities such as arsenic are doped is formed on a semiconductor substrate, and a nitride film is formed in regions where p type pockets are formed on the both sides of a gate electrode. By implementing heat treatment in the atmosphere of oxygen, the portion below the nitride film is placed in the condition where it is equivalent when heat treated in the atmosphere of nitrogen whereby a p type impurity region and an n.sup.- type impurity region are formed. The region except for that below the nitride film is heat treated in the atmosphere of oxygen to form an n.sup.+ type impurity region. Further, with the gate electrode as a mask, n.sup.- type impurity region and p type impurity region are formed, thereafter selectively growing a film on the side walls of the gate electrode to form an n.sup.+ type impurity region with the gate electrode and the film as masks, thus producing a MOS transistor.
摘要翻译：一种制造具有p（n）型袋的LDD结构的MOS晶体管的方法。在半导体衬底上形成掺杂有杂质如砷的杂质如砷的掺杂氧化物膜，并且在栅电极的两侧形成有p型穴的区域中形成氮化物膜。通过在氧气氛下进行热处理，将氮化膜下方的部分置于在氮气气氛中进行热处理时相当的状态，由此形成p型杂质区域和n型杂质区域。除了氮化物膜下方的区域在氧气氛中进行热处理以形成n +型杂质区域。此外，以栅电极为掩模，形成n型杂质区和p型杂质区，然后在栅电极的侧壁上选择性地生长膜以与栅电极和膜形成n +型杂质区作为掩模，从而产生MOS晶体管。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式