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1. 发明申请

US20110134695A1 SEMICONDUCTOR MEMORY DEVICE 失效
标题翻译：半导体存储器件
公开(公告)号：US20110134695A1
公开(公告)日：2011-06-09
申请号：US12957865
申请日：2010-12-01
申请人： Kazushige Kanda , Toshiki Hisada , Katsuaki Isobe
发明人： Kazushige Kanda , Toshiki Hisada , Katsuaki Isobe
IPC分类号： G11C16/04
CPC分类号： H01L27/11519 , H01L27/11521 , H01L27/11524
摘要： Provided is a semiconductor memory device including: multiple bit lines arranged in parallel to one another; multiple sense-amplifier bit lines arranged away from end portions of the bit lines; a fourth sense-amplifier bit line formed with a wire of a first layer arranged below the bit lines; selection transistors with a pair of gate electrodes arranged in a direction normal to the first to sixth bit lines; a first wire arranged below the bit lines and the sense-amplifier bit lines, and having an end portion extending to below the third bit line and connected to the bit line; a third wire formed with a layer of the gate electrode used as a wire, the third wire including a first end portion positioned below the fourth sense-amplifier bit line and connected to the fourth sense-amplifier bit line, and a second end portion positioned below the second sense-amplifier bit line; and a fourth wire formed with a wire of the first layer and arranged between the third wire and the second sense-amplifier bit line to connect the third wire to the second sense-amplifier bit line.
摘要翻译：提供一种半导体存储器件，包括：彼此平行布置的多个位线; 多个读出放大器位线布置成远离位线的端部; 第四感测放大器位线，其布置在位线下方的第一层的导线; 选择晶体管，其具有沿与第一至第六位线垂直的方向排列的一对栅电极; 布置在位线下方的第一线和读出放大器位线，并且具有延伸到第三位线下方并连接到位线的端部; 第三线，其形成有用作线的栅极电极层，所述第三线包括位于所述第四感测放大器位线下方并连接到所述第四感测放大器位线的第一端部，以及位于低于第二感测放大器位线; 以及第四导线，其由第一层的导线形成，并且布置在第三导线和第二读出放大器位线之间，以将第三导线连接到第二感测放大器位线。

2. 发明授权

US08315094B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US08315094B2
公开(公告)日：2012-11-20
申请号：US12957865
申请日：2010-12-01
申请人： Kazushige Kanda , Toshiki Hisada , Katsuaki Isobe
发明人： Kazushige Kanda , Toshiki Hisada , Katsuaki Isobe
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： H01L27/11519 , H01L27/11521 , H01L27/11524
摘要： Provided is a semiconductor memory device including: multiple bit lines arranged in parallel to one another; multiple sense-amplifier bit lines arranged away from end portions of the bit lines; a fourth sense-amplifier bit line formed with a wire of a first layer arranged below the bit lines; selection transistors with a pair of gate electrodes arranged in a direction normal to the first to sixth bit lines; a first wire arranged below the bit lines and the sense-amplifier bit lines, and having an end portion extending to below the third bit line and connected to the bit line; a third wire formed with a layer of the gate electrode used as a wire, the third wire including a first end portion positioned below the fourth sense-amplifier bit line and connected to the fourth sense-amplifier bit line, and a second end portion positioned below the second sense-amplifier bit line; and a fourth wire formed with a wire of the first layer and arranged between the third wire and the second sense-amplifier bit line to connect the third wire to the second sense-amplifier bit line.
摘要翻译：提供一种半导体存储器件，包括：彼此平行布置的多个位线; 多个读出放大器位线布置成远离位线的端部; 第四感测放大器位线，其布置在位线下方的第一层的导线; 选择晶体管，其具有沿与第一至第六位线垂直的方向排列的一对栅电极; 布置在位线下方的第一线和读出放大器位线，并且具有延伸到第三位线下方并连接到位线的端部; 第三线，其形成有用作线的栅极电极层，所述第三线包括位于所述第四感测放大器位线下方并连接到所述第四感测放大器位线的第一端部，以及位于低于第二感测放大器位线; 以及第四导线，其由第一层的导线形成，并且布置在第三导线和第二读出放大器位线之间，以将第三导线连接到第二感测放大器位线。

3. 发明授权

US08644051B2 Semiconductor memory device and control method of the same 有权
标题翻译：半导体存储器件及其控制方法相同
公开(公告)号：US08644051B2
公开(公告)日：2014-02-04
申请号：US13230156
申请日：2011-09-12
申请人： Kazushige Kanda
发明人： Kazushige Kanda
IPC分类号： G11C11/00
CPC分类号： G11C13/00 , G11C7/1021 , G11C7/22 , G11C13/0023 , G11C13/004 , G11C13/0061 , G11C13/0069 , G11C2213/51 , G11C2213/71 , G11C2213/72
摘要： According to one embodiment, a semiconductor memory device includes a plurality of memory cell arrays each includes a plurality of memory cells, the plurality of memory cell arrays being stacked on a semiconductor substrate to form a three-dimensional structure, and a data input/output circuit includes a first address buffer and a second address buffer configured to store a first address and a second address of the plurality of memory cells, and a controller configured to perform control to time-divisionally output the first address and the second address to a first address bus and a second address bus in data input/output.
摘要翻译：根据一个实施例，半导体存储器件包括多个存储单元阵列，每个存储单元阵列包括多个存储单元，多个存储单元阵列堆叠在半导体衬底上以形成三维结构，以及数据输入/输出电路包括：第一地址缓冲器和第二地址缓冲器，被配置为存储多个存储器单元的第一地址和第二地址;以及控制器，被配置为执行控制以将第一地址和第二地址时分输出到第一地址地址总线和数据输入/输出中的第二个地址总线。

4. 发明授权

US08593852B2 Test device and test method for resistive random access memory and resistive random access memory device 有权
标题翻译：电阻随机存取存储器和电阻随机存取存储器件的测试装置和测试方法
公开(公告)号：US08593852B2
公开(公告)日：2013-11-26
申请号：US13238479
申请日：2011-09-21
申请人： Kazuaki Kawaguchi , Kazushige Kanda
发明人： Kazuaki Kawaguchi , Kazushige Kanda
IPC分类号： G11C11/00
CPC分类号： G11C29/56 , G11C11/16 , G11C13/00 , G11C29/50012 , G11C29/56012
摘要： According to the embodiments, a first write enable signal that changes with a constant period and a second write enable signal that changes at a time portion in which a limit time between activation/deactivation control of word lines and activation/deactivation control of bit lines is checked are input, a plurality of core control signals in which a time interval with which the core control signals change is locally shorter than a period of the first write enable signal based on the first write enable signal and the second write enable signal that are input is generated, and an operation verification of the resistive random access memory is performed by using the generated core control signals, whereby a cycle time in an arbitrary test cycle is locally and arbitrary adjusted.
摘要翻译：根据实施例，在恒定周期改变的第一写入使能信号和在字线的激活/停止控制和位线的激活/去激活控制之间的限制时间的时间部分发生变化的第二写使能信号是多个核心控制信号，其中核心控制信号改变的时间间隔基于输入的第一写入使能信号和第二写入使能信号而局部地短于第一写入使能信号的周期并且通过使用所生成的核心控制信号来执行电阻性随机存取存储器的操作验证，从而局部地和任意地调整任意测试周期中的周期时间。

5. 发明授权

US08289793B2 Nonvolatile semiconductor memory device capable of testing diodes and manufacturing method thereof 失效
标题翻译：能够测试二极管的非易失性半导体存储器件及其制造方法
公开(公告)号：US08289793B2
公开(公告)日：2012-10-16
申请号：US12861309
申请日：2010-08-23
申请人： Kazushige Kanda
发明人： Kazushige Kanda
IPC分类号： G11C29/00
CPC分类号： G11C29/08 , G01R31/2635 , Y10T29/49004
摘要： According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array, and a control circuit. The memory cell array includes plural memory cells arranged in rows and columns and each including a diode and resistance-change element. The control circuit tests the diodes for the respective memory cells. The control circuit tests the diode at least at one of times before and after one of a write operation, erase operation and read operation with respect to the memory cell is performed.
摘要翻译：根据一个实施例，非易失性半导体存储器件包括存储单元阵列和控制电路。存储单元阵列包括排成行和列的多个存储单元，每个存储单元包括二极管和电阻变化元件。控制电路测试各个存储单元的二极管。控制电路至少在执行相对于存储器单元的写入操作，擦除操作和读取操作之一之前和之后的一个时刻测试二极管。

6. 发明申请

US20120243365A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD OF SETTING OPERATION ENVIRONMENT THEREIN 有权
标题翻译：半导体存储器件及其操作环境设置方法
公开(公告)号：US20120243365A1
公开(公告)日：2012-09-27
申请号：US13423608
申请日：2012-03-19
申请人： Kazushige Kanda , Toshihiro Suzuki
发明人： Kazushige Kanda , Toshihiro Suzuki
IPC分类号： G11C8/10 , G11C8/00
CPC分类号： G11C8/10 , G11C7/1045
摘要： A semiconductor memory device comprises: a memory cell array including a plurality of memory cells; an internal circuit having a function required in a storage operation of the memory cell array; a parameter storage unit configured to store a certain parameter and to have a storage place specified by a parameter address, the certain parameter designating an operation of the internal circuit; a command register configured to store a command instructing an operation of the internal circuit; and a converting circuit configured to adjust at least one of the parameter address and the command that differ between products or between standards to the internal circuit.
摘要翻译：半导体存储器件包括：包括多个存储单元的存储单元阵列; 具有存储单元阵列的存储操作所需功能的内部电路; 参数存储单元，被配置为存储特定参数并且具有由参数地址指定的存储位置，所述特定参数指定所述内部电路的操作; 命令寄存器，被配置为存储指示所述内部电路的操作的命令; 以及转换电路，被配置为将产品之间或标准之间不同的参数地址和命令中的至少一个调整到内部电路。

7. 发明申请

US20110141794A1 SEMICONDUCTOR MEMORY DEVICE AND INSPECTING METHOD OF THE SAME 失效
标题翻译：半导体存储器件及其检测方法
公开(公告)号：US20110141794A1
公开(公告)日：2011-06-16
申请号：US12884694
申请日：2010-09-17
申请人： Tomonori Kurosawa , Takahiko Sasaki , Kazushige Kanda
发明人： Tomonori Kurosawa , Takahiko Sasaki , Kazushige Kanda
IPC分类号： G11C29/02 , G11C11/21
CPC分类号： G11C29/02 , G11C11/16 , G11C29/025 , G11C2029/1204
摘要： According to one embodiment, a semiconductor memory device includes a memory cell array includes memory cells, lines provided to correspond to the memory cells, a first decoder configured to select a first line as an inspection target from the lines, a second decoder configured to select a second line for generating a reference voltage from the lines, a driver configured to charge the first and second lines, a discharging circuit configured to simultaneously discharge the first and second lines, and a sense amplifier configured to compare a voltage of the first line with a voltage of the second line to detect a defect of the first line while the first line is discharged.
摘要翻译：根据一个实施例，半导体存储器件包括存储单元阵列，其包括存储单元，提供用于对应于存储单元的线，第一解码器，被配置为从线选择第一行作为检查对象;第二解码器，被配置为选择用于从所述线路产生参考电压的第二线路，被配置为对所述第一和第二线路充电的驱动器，配置成同时对所述第一和第二线路进行放电的放电电路;以及读出放大器，被配置为将所述第一线路的电压与第一线的电压在第一线放电时检测第一线的缺陷。

8. 发明申请

US20070201299A1 SEMICONDUCTOR MEMORY DEVICE WITH MOS TRANSISTORS EACH HAVING FLOATING GATE AND CONTROL GATE 有权
标题翻译：具有浮动门和控制门的MOS晶体管的半导体存储器件
公开(公告)号：US20070201299A1
公开(公告)日：2007-08-30
申请号：US11733796
申请日：2007-04-11
申请人： Kazushige Kanda , Akira Umezawa , Kazuhiko Kakizoe , Yoshiaki Hashiba , Yoshiharu Hirata
发明人： Kazushige Kanda , Akira Umezawa , Kazuhiko Kakizoe , Yoshiaki Hashiba , Yoshiharu Hirata
IPC分类号： G11C8/00
CPC分类号： G11C8/10 , G11C8/08 , G11C11/005 , G11C16/0425 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/26 , H01L27/115
摘要： A semiconductor memory device includes a memory cell array, word lines, and a row decoder. The memory cell array includes memory cells arranged in a matrix. The memory cell includes a first MOS transistor having a charge accumulation layer and a control gate and a second MOS transistor. The word line connects the control gates of the first MOS transistors. The row decoder includes a first address decode circuit, a second address decode circuit, and a transfer gate. The first address decode circuit decodes m bits in a n-bit row address signal (m and n are a natural number satisfying the expression m
摘要翻译：半导体存储器件包括存储单元阵列，字线和行解码器。存储单元阵列包括排列成矩阵的存储单元。存储单元包括具有电荷累积层的第一MOS晶体管和控制栅极和第二MOS晶体管。字线连接第一MOS晶体管的控制栅极。行解码器包括第一地址解码电路，第二地址解码电路和传输门。第一地址解码电路解码n位行地址信号中的m位（m和n是满足表达式m

9. 发明授权

US06901012B2 Semiconductor memory device having a power-on reset circuit 有权
标题翻译：具有上电复位电路的半导体存储器件
公开(公告)号：US06901012B2
公开(公告)日：2005-05-31
申请号：US10655294
申请日：2003-09-05
申请人： Tamio Ikehashi , Kazushige Kanda
发明人： Tamio Ikehashi , Kazushige Kanda
IPC分类号： G11C7/00 , G11C5/14 , H03K17/22 , G11C16/04
CPC分类号： H03K17/223 , G11C5/143 , G11C5/145
摘要： A semiconductor device includes an internal power supply terminal for supplying an internal power supply voltage, an oscillator generating a clock pulse when the internal power supply voltage becomes higher than a first voltage, a charge pump circuit charge pumping upon receiving the clock pulse, a reference voltage generator using the output voltage from the charge pump circuit as a power supply, and a voltage monitor which uses the output voltage from the charge pump circuit as a power supply, has a comparator for comparing a divided voltage of the internal power supply voltage with the reference voltage, and outputs a first signal of a first logic level as the power-on reset signal when the internal power supply voltage is higher than a second voltage. With this arrangement, a power-on reset circuit with little variation in power-on monitoring level can be provided.
摘要翻译：一种半导体器件包括用于提供内部电源电压的内部电源端子，当内部电源电压变得高于第一电压时产生时钟脉冲的振荡器，接收时钟脉冲时的电荷泵电路电荷泵浦，电压发生器，使用来自电荷泵电路的输出电压作为电源，以及使用来自电荷泵电路的输出电压作为电源的电压监视器，具有比较器，用于将内部电源电压的分压与参考电压，并且当内部电源电压高于第二电压时，输出第一逻辑电平的第一信号作为上电复位信号。通过这种布置，可以提供上电监视级别变化小的上电复位电路。

10. 发明授权

US06522583B2 Nonvolatile semiconductor memory 有权
公开(公告)号：US06522583B2
公开(公告)日：2003-02-18
申请号：US09860613
申请日：2001-05-21
申请人： Kazushige Kanda , Hiroshi Nakamura , Koji Hosono , Tamio Ikehashi , Kenichi Imamiya
发明人： Kazushige Kanda , Hiroshi Nakamura , Koji Hosono , Tamio Ikehashi , Kenichi Imamiya
IPC分类号： G11C1604
CPC分类号： G11C16/10 , G11C16/0483
摘要： A drain-side select gate line is set to VSG1 (>VDD) capable of sufficiently transferring VDD (time t1). Since all word lines in the selected block are set to Vread, VDD is applied to the channels of all memory cells in the cell units. After this, the drain-side select gate line is set to VSG2, and a program potential Vpgm is applied to the selected word line (times t2 to t3). Since VSG2 is sufficiently low, all drain-side select gate transistors are kept off, and the channel potentials of memory cells in all cell units are boosted. After this, since the drain-side select gate line is set to VSG3, the channel of the selected memory cell is set to 0V (time t4).

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