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1. 发明授权

US06278639B1 Booster circuit having booster cell sections connected in parallel, voltage generating circuit and semiconductor memory which use such booster circuit 失效
标题翻译：具有并联连接的升压电池部分的升压电路，电压产生电路和使用这种升压电路的半导体存储器
公开(公告)号：US06278639B1
公开(公告)日：2001-08-21
申请号：US09392127
申请日：1999-09-08
申请人： Koji Hosono , Hiroshi Nakamura , Tamio Ikehashi , Kazushige Kanda , Ken Takeuchi , Kenichi Imamiya
发明人： Koji Hosono , Hiroshi Nakamura , Tamio Ikehashi , Kazushige Kanda , Ken Takeuchi , Kenichi Imamiya
IPC分类号： G11C700
CPC分类号： G11C5/145
摘要： The booster circuit of the present invention includes a first booster cell section in which one or more booster cells are connected in series, and a second booster cell section having an end which is connected to the first booster cell section, in which a plurality of booster cell groups each containing one or more booster cells connected in series, are connected to each other in parallel.
摘要翻译：本发明的升压电路包括其中一个或多个升压电池串联连接的第一升压电池部分和具有连接到第一升压电池部分的端部的第二升压电池部分，其中多个增压器每个包含串联连接的一个或多个升压电池的电池组彼此并联连接。

2. 发明授权

US06522583B2 Nonvolatile semiconductor memory 有权
公开(公告)号：US06522583B2
公开(公告)日：2003-02-18
申请号：US09860613
申请日：2001-05-21
申请人： Kazushige Kanda , Hiroshi Nakamura , Koji Hosono , Tamio Ikehashi , Kenichi Imamiya
发明人： Kazushige Kanda , Hiroshi Nakamura , Koji Hosono , Tamio Ikehashi , Kenichi Imamiya
IPC分类号： G11C1604
CPC分类号： G11C16/10 , G11C16/0483
摘要： A drain-side select gate line is set to VSG1 (>VDD) capable of sufficiently transferring VDD (time t1). Since all word lines in the selected block are set to Vread, VDD is applied to the channels of all memory cells in the cell units. After this, the drain-side select gate line is set to VSG2, and a program potential Vpgm is applied to the selected word line (times t2 to t3). Since VSG2 is sufficiently low, all drain-side select gate transistors are kept off, and the channel potentials of memory cells in all cell units are boosted. After this, since the drain-side select gate line is set to VSG3, the channel of the selected memory cell is set to 0V (time t4).

3. 发明授权

US06507518B2 Fail number detecting circuit of flash memory 有权
公开(公告)号：US06507518B2
公开(公告)日：2003-01-14
申请号：US09985017
申请日：2001-11-01
申请人： Koji Hosono , Tamio Ikehashi , Tomoharu Tanaka , Kenichi Imamiya , Hiroshi Nakamura , Ken Takeuchi
发明人： Koji Hosono , Tamio Ikehashi , Tomoharu Tanaka , Kenichi Imamiya , Hiroshi Nakamura , Ken Takeuchi
IPC分类号： G11C1606
CPC分类号： G11C16/3445 , G11C16/3436 , G11C16/3459
摘要： A semiconductor memory device includes a memory cell array, a plurality of latch circuits, first circuit, second circuit and third circuit. The memory cell array has electrically rewritable nonvolatile memory cells arranged therein. The plurality of latch circuits temporarily hold data read out from the memory cell array. The first circuit is configured to generate a first current varying in proportion to “1” or “0” of binary logical data of one end of the plurality of latch circuits. The second circuit is configured to generate a second preset current. The third circuit is configured to compare the first current with the second current. The number of “1” or “0” of binary logical data of one end of the plurality of latch circuits is detected based on the result of comparison between the first current and the second current.

4. 发明授权

US06859401B2 Fail number detecting circuit of flash memory 有权
标题翻译：闪存的故障号检测电路
公开(公告)号：US06859401B2
公开(公告)日：2005-02-22
申请号：US10674404
申请日：2003-10-01
申请人： Koji Hosono , Tamio Ikehashi , Tomoharu Tanaka , Kenichi Imamiya , Hiroshi Nakamura , Ken Takeuchi
发明人： Koji Hosono , Tamio Ikehashi , Tomoharu Tanaka , Kenichi Imamiya , Hiroshi Nakamura , Ken Takeuchi
IPC分类号： G11C16/02 , G11C16/04 , G11C16/06 , G11C16/34 , G11C29/04 , G11C29/12
CPC分类号： G11C16/3445 , G11C16/3436 , G11C16/3459
摘要： A semiconductor device includes a memory cell array, latch circuits, first to third circuits and a current control circuit. The memory cell array includes NAND cells arranged therein. The latch circuits temporarily hold data read out from the memory cell array. The first circuit generates a first current varying in proportion to “1” or “0” of binary logic data of one end of the plurality of latch circuits. The second circuit generates a second current which is preset. The third circuit compares the first current with the second current. The value of “1” or “0” of binary logic data of the one end of the plurality of latch circuits is detected based on a result of the comparison between the first current and the second current.
摘要翻译：半导体器件包括存储单元阵列，锁存电路，第一至第三电路和电流控制电路。存储单元阵列包括其中布置的NAND单元。锁存电路暂时保存从存储单元阵列读出的数据。第一电路产生与多个锁存电路的一端的二进制逻辑数据的“1”或“0”成比例变化的第一电流。第二电路产生预置的第二电流。第三电路将第一电流与第二电流进行比较。基于第一电流和第二电流之间的比较结果，检测多个锁存电路一端的二进制逻辑数据的“1”或“0”值。

5. 发明授权

US06657896B2 Fail number detecting circuit of flash memory 有权
标题翻译：闪存的故障号检测电路
公开(公告)号：US06657896B2
公开(公告)日：2003-12-02
申请号：US10315050
申请日：2002-12-10
申请人： Koji Hosono , Tamio Ikehashi , Tomoharu Tanaka , Kenichi Imamiya , Hiroshi Nakamura , Ken Takeuchi
发明人： Koji Hosono , Tamio Ikehashi , Tomoharu Tanaka , Kenichi Imamiya , Hiroshi Nakamura , Ken Takeuchi
IPC分类号： G11C1606
CPC分类号： G11C16/3445 , G11C16/3436 , G11C16/3459
摘要： A semiconductor memory device includes a memory cell array, latch circuits, first to third circuits and a current control circuit. The memory cell array includes electrically rewritable nonvolatile memory cells arranged therein. The latch circuits temporarily hold data read out from the memory cell array. The first circuit generates a first current which varies in proportion to “1” or “0” of binary logical data of one end of the latch circuits. The second circuit generates a predetermined second current. The current control circuit is connected to the first and second circuits, and configured to determined absolute values of the first and second currents. The third circuit is configured to compare the first and second currents. The number of binary logical data of “1” or “0” of one end of the latch circuits is detected based on the result of comparison between the first and second currents.
摘要翻译：半导体存储器件包括存储单元阵列，锁存电路，第一至第三电路和电流控制电路。存储单元阵列包括布置在其中的电可重写非易失性存储单元。锁存电路暂时保存从存储单元阵列读出的数据。第一电路产生与锁存电路的一端的二进制逻辑数据的“1”或“0”成比例变化的第一电流。第二电路产生预定的第二电流。电流控制电路连接到第一和第二电路，并被配置为确定第一和第二电流的绝对值。第三电路被配置为比较第一和第二电流。基于第一和第二电流之间的比较结果来检测锁存电路的一端的“1”或“0”的二进制逻辑数据的数量。

6. 发明授权

US08477541B2 Semiconductor integrated circuit adapted to output pass/fail results of internal operations 有权
公开(公告)号：US08477541B2
公开(公告)日：2013-07-02
申请号：US13489977
申请日：2012-06-06
申请人： Hiroshi Nakamura , Kenichi Imamiya , Toshio Yamamura , Koji Hosono , Koichi Kawai
发明人： Hiroshi Nakamura , Kenichi Imamiya , Toshio Yamamura , Koji Hosono , Koichi Kawai
IPC分类号： G11C7/10
CPC分类号： G11C16/3459 , G06F3/0659 , G06F12/0246 , G11C7/065 , G11C7/1006 , G11C7/1051 , G11C7/106 , G11C7/1063 , G11C16/06 , G11C16/08 , G11C16/10 , G11C16/26 , G11C2207/104 , G11C2216/14
摘要： In a semiconductor integrated circuit, an internal circuit is capable of executing a first operation and a second operation concurrently, and an output circuit outputs to the outside of the semiconductor integrated circuit information indicating whether or not the first operation is being executed and information indicating whether or not the second operation is executable.

7. 发明授权

US07916555B2 Semiconductor integrated circuit adapted to output pass/fail results of internal operations 有权
标题翻译：半导体集成电路适用于输出内部操作的通过/失败结果
公开(公告)号：US07916555B2
公开(公告)日：2011-03-29
申请号：US12252896
申请日：2008-10-16
申请人： Hiroshi Nakamura , Kenichi Imamiya , Toshio Yamamura , Koji Hosono , Koichi Kawai
发明人： Hiroshi Nakamura , Kenichi Imamiya , Toshio Yamamura , Koji Hosono , Koichi Kawai
IPC分类号： G11C7/10
CPC分类号： G11C16/3459 , G06F3/0659 , G06F12/0246 , G11C7/065 , G11C7/1006 , G11C7/1051 , G11C7/106 , G11C7/1063 , G11C16/06 , G11C16/08 , G11C16/10 , G11C16/26 , G11C2207/104 , G11C2216/14
摘要： In a semiconductor integrated circuit, an internal circuit is capable of executing a first operation and a second operation concurrently, and an output circuit outputs to the outside of the semiconductor integrated circuit information indicating whether or not the first operation is being executed and information indicating whether or not the second operation is executable.
摘要翻译：在半导体集成电路中，内部电路能够同时执行第一操作和第二操作，并且输出电路向半导体集成电路的外部输出指示是否正在执行第一操作的信息以及指示是否或者不是第二操作是可执行的。

8. 发明申请

US20080225618A1 Non-Volatile Semiconductor Memory 有权
标题翻译：非易失性半导体存储器
公开(公告)号：US20080225618A1
公开(公告)日：2008-09-18
申请号：US12123157
申请日：2008-05-19
申请人： Koji Hosono , Hiroshi Nakamura , Ken Takeuchi , Kenichi Imamiya
发明人： Koji Hosono , Hiroshi Nakamura , Ken Takeuchi , Kenichi Imamiya
IPC分类号： G11C7/06
CPC分类号： G11C16/0483 , G11C5/145 , G11C7/1006 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/10 , G11C16/24 , G11C16/26 , G11C16/3445 , G11C16/3454 , G11C16/3459 , G11C2211/5621 , G11C2211/5641 , G11C2211/5642 , G11C2211/5643
摘要： A non-volatile semiconductor device has a memory cell array having electrically erasable programmable non-volatile memory cells, reprogramming and retrieval circuits that temporarily store data to be programmed in the memory cell array and sense data retrieved from the memory cell array. Each reprogramming and retrieval circuit has first and second latches that are selectively connected to the memory cell array and transfer data. A controller controls the reprogramming and retrieval circuits on a data-reprogramming operation to and a data-retrieval operation from the memory cell array. Each reprogramming and retrieval circuit has a multilevel logical operation mode and a caching operation mode. In the multilevel logical operation mode, re-programming and retrieval of upper and lower bits of two-bit four-level data is performed using the first and the second latches to store the two-bit four-level data in one of the memory cells in a predetermined threshold level range. In the caching operation mode, data transfer between one of the memory cells selected in accordance with a first address and the first latch is performed while data transfer is performed between the second latch and input/output terminals in accordance with a second address with respect to one-bit two-level data to be stored in one of the memory cells.
摘要翻译：非易失性半导体器件具有存储单元阵列，其具有电可擦除可编程非易失性存储器单元，重新编程和检索电路，其临时存储要存储在存储单元阵列中的要编程的数据并感测从存储器单元阵列检索的数据。每个重新编程和检索电路具有选择性地连接到存储单元阵列和传送数据的第一和第二锁存器。控制器控制数据重新编程操作中的重新编程和检索电路以及来自存储单元阵列的数据检索操作。每个重新编程和检索电路都具有多级逻辑操作模式和缓存操作模式。在多级逻辑操作模式中，使用第一和第二锁存器来执行二位四电平数据的高位和低位的重新编程和检索，以将两位四电平数据存储在存储单元之一中在预定的阈值电平范围内。在高速缓存操作模式中，根据第一地址选择的存储器单元之一和第一锁存器之间的数据传输是在第二锁存器和输入/输出端子之间根据第二地址相对于要存储在其中一个存储单元中的一位二电平数据。

9. 发明授权

US07123515B2 Semiconductor integrated circuit adapted to output pass/fail results of internal operations 有权
公开(公告)号：US07123515B2
公开(公告)日：2006-10-17
申请号：US11119744
申请日：2005-05-03
申请人： Hiroshi Nakamura , Kenichi Imamiya , Toshio Yamamura , Koji Hosono , Koichi Kawai
发明人： Hiroshi Nakamura , Kenichi Imamiya , Toshio Yamamura , Koji Hosono , Koichi Kawai
IPC分类号： G11C11/34
CPC分类号： G11C16/3459 , G06F3/0659 , G06F12/0246 , G11C7/065 , G11C7/1006 , G11C7/1051 , G11C7/106 , G11C7/1063 , G11C16/06 , G11C16/08 , G11C16/10 , G11C16/26 , G11C2207/104 , G11C2216/14
摘要： In a semiconductor integrated circuit, an internal circuit is capable of executing a first operation and a second operation concurrently, and an output circuit outputs to the outside of the semiconductor integrated circuit information indicating whether or not the first operation is being executed and information indicating whether or not the second operation is executable.

10. 发明授权

US07117296B2 Method of programming non-volatile semiconductor memory device having an electrically erasable and programmable memory cell array 失效
标题翻译：编程具有电可擦除可编程存储单元阵列的非易失性半导体存储器件的方法
公开(公告)号：US07117296B2
公开(公告)日：2006-10-03
申请号：US11117669
申请日：2005-04-28
申请人： Koji Hosono , Kenichi Imamiya , Hiroshi Nakamura , Mikito Nakabayashi , Koichi Kawai
发明人： Koji Hosono , Kenichi Imamiya , Hiroshi Nakamura , Mikito Nakabayashi , Koichi Kawai
IPC分类号： G06F12/00 , G06F13/00
CPC分类号： G11C16/3463 , G11C16/3454 , G11C16/3459
摘要： A non-volatile semiconductor memory device includes a memory cell array in which electrically erasable and programmable memory cells are arrayed, each of the memory cells storing therein a first logic state with a threshold voltage lower than or equal to a first value or a second logic state with a threshold voltage higher than or equal to a second value that is higher than the first value, a data hold circuit for holding program data and sensing data as read out of the memory cell array, and a controller configured to control a program sequence, wherein the controller has the control functions of: a program control function for applying a program voltage to a selected memory cell of the memory cell array to let the data shift from the first logic state to the second logic state; a program verify control function for verifying that the programmed data of the selected memory cell shifted to the second logic state; an erratic program verify control function for checking that the threshold voltage of a memory cell to be held in the first logic state does not exceed a third value set as an upper limit value of a variation of the first logic state; and an over-program verify control function for checking that the threshold voltage of the selected memory cell shifted to the second logic state does not exceed a fourth value set as an upper limit thereof.
摘要翻译：一种非易失性半导体存储器件包括存储单元阵列，其中电可擦除可编程存储单元被排列，每个存储单元存储第一逻辑状态，阈值电压低于或等于第一值或第二逻辑具有高于或等于高于第一值的第二值的阈值电压的状态，用于保存从存储单元阵列读出的程序数据和感测数据的数据保持电路，以及控制器，其被配置为控制程序序列其中所述控制器具有以下控制功能：用于将程序电压施加到所述存储单元阵列的选定存储单元以使数据从第一逻辑状态移位到第二逻辑状态的程序控制功能; 程序验证控制功能，用于验证所选择的存储单元的编程数据移动到第二逻辑状态; 用于检查要保持在第一逻辑状态的存储单元的阈值电压不超过设置为第一逻辑状态的变化的上限值的第三值的不规则程序验证控制功能; 以及用于检查移动到第二逻辑状态的选择的存储单元的阈值电压不超过设定为其上限的第四值的过程序验证控制功能。

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