会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 5. 发明授权
    • Integrated circuit tester
    • 集成电路测试仪
    • US5398252A
    • 1995-03-14
    • US794894
    • 1991-11-20
    • Kazuhiko Ohashi
    • Kazuhiko Ohashi
    • G01R31/28G01R31/3193G06F11/00
    • G01R31/31935G06F2201/865
    • An integrated circuit tester uses the information compared between a test executed result and an expected value, for the operation of a driver, which applies test patterns to a device under test. Once a test executed result obtained from the device is compared with an expected value, the compared information is fedback to the driver so as to specify, for example, test cycles and test patterns. Therefore, in an evaluation of maximum operating frequencies, the failure which occurs in the (n+1)th lower frequency can be effectively observed without being masked by other failures which occur in the nth lower frequency or less.
    • 集成电路测试仪使用将测试模式应用于被测设备的驱动程序的操作的测试执行结果与期望值之间的信息进行比较。 将从设备获得的测试执行结果与预期值进行比较后,将比较的信息反馈给驱动器,以指定例如测试周期和测试模式。 因此,在最大工作频率的评价中,可以有效地观察发生在第(n + 1)低频中的故障,而不会被发生在第n次以下频率以下的其他故障所掩盖。
    • 8. 发明授权
    • Data processing device with test circuit
    • 具有测试电路的数据处理设备
    • US5515517A
    • 1996-05-07
    • US357052
    • 1994-12-14
    • Yasuyuki NozuyamaKazuhiko Ohashi
    • Yasuyuki NozuyamaKazuhiko Ohashi
    • G06F11/22G01R31/3185G06F11/26
    • G01R31/318541G01R31/318536
    • A data processing device with a test circuit has a plurality of macro blocks, a common bus for transferring the output of one of the macro blocks to the other macro blocks, and a tri-state buffer incorporated into each macro block. A bus control circuit selects the tri-state buffer in a normal operation mode in which the device performs its normal functions, in order to transfer the information stored in the macro block corresponding to the tri-state buffer selected by the bus control circuit to the common bus. A selecting control circuit, which includes a selector, an AND gate, and a flip-flop (F/F), is used for selecting the tri-state buffer in a test operation mode which the device has entered, then for transferring the information stored in the macro block corresponding to the tri-state buffer selected by the selecting control circuit to the common bus. A F/F is provided for setting the device in either the normal operation mode or the test operation mode. In the data processing device according to the present invention, in addition to the bus control circuit, which is used in the normal operation mode, the selecting control circuit, which is used in the test operation mode, is provided, so that the efficiency of the test vector generation is greatly improved.
    • 具有测试电路的数据处理装置具有多个宏块,用于将宏块中的一个的输出传送到其他宏块的公共总线,以及并入每个宏块中的三态缓冲器。 总线控制电路在设备执行其正常功能的正常操作模式中选择三态缓冲器,以将存储在与由总线控制电路选择的三态缓冲器相对应的宏块中的信息传送到 公车 包括选择器,与门和触发器(F / F)的选择控制电路用于在设备输入的测试操作模式中选择三态缓冲器,然后用于传送信息 存储在与由选择控制电路选择的三态缓冲器对应的宏块中的公共总线。 提供F / F用于在正常操作模式或测试操作模式下设置设备。 在根据本发明的数据处理装置中,除了在正常操作模式下使用的总线控制电路之外,还提供了在测试操作模式中使用的选择控制电路, 测试向量生成得到很大的改善。