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1. 发明授权

US5294812A Semiconductor device having identification region for carrying out failure analysis 失效
标题翻译：具有用于进行故障分析的识别区域的半导体装置
公开(公告)号：US5294812A
公开(公告)日：1994-03-15
申请号：US38063
申请日：1993-03-26
申请人： Kazuhiko Hashimoto , Masataka Matsui , Syoichi Asoh
发明人： Kazuhiko Hashimoto , Masataka Matsui , Syoichi Asoh
IPC分类号： H01L21/02 , G01R31/28 , H01L21/00 , H01L23/544 , H01L29/34
CPC分类号： G01R31/2884 , H01L23/544 , H01L2223/54406 , H01L2223/54413 , H01L2223/54433 , H01L2223/5444 , H01L2223/54473 , H01L2223/5448 , H01L2924/0002
摘要： A semiconductor device capable of performing a failure analysis includes a semiconductor substrate having a plurality of circuit elements, and an identification region provided above the semiconductor substrate so as to record identification information such as position information within wafers, information for wafer numbers, etc. The identification information is given by binary coded patterns, fused patterns of fuse elements, etc.
摘要翻译：能够执行故障分析的半导体器件包括具有多个电路元件的半导体器件和设置在半导体衬底上方的识别区域，以便记录晶片内的位置信息等识别信息，晶片号码信息等。识别信息由二进制编码图案，熔丝元件的融合图案等给出。

2. 发明授权

US07487370B2 Semiconductor device and system 有权
标题翻译：半导体器件和系统
公开(公告)号：US07487370B2
公开(公告)日：2009-02-03
申请号：US11216018
申请日：2005-09-01
申请人： Shinichiro Shiratake , Yukihito Oowaki , Hiroyuki Hara , Tetsuya Fujita , Fumitoshi Hatori , Masataka Matsui
发明人： Shinichiro Shiratake , Yukihito Oowaki , Hiroyuki Hara , Tetsuya Fujita , Fumitoshi Hatori , Masataka Matsui
IPC分类号： G06F1/00
CPC分类号： G06F1/26 , G06F1/3203 , G06F1/3296 , Y02D10/172
摘要： According to the present invention, there is provided a semiconductor device including a power supply circuit which receives an external power supply voltage supplied, and outputs an internal power supply voltage not higher than the external power supply voltage; a system module which receives the internal power supply voltage, and performs a predetermined operation; and a performance monitor circuit which measures a processing speed of said system module when the internal power supply voltage is applied, and, on the basis of the processing speed, outputs a first control signal which requests to set the external power supply voltage at a first level, and a second control signal which requests said power supply circuit to set the internal power supply voltage at a second level. The power supply circuit outputs the internal power supply voltage having the second level on the basis of the second control signal applied thereto.
摘要翻译：根据本发明，提供了一种半导体器件，包括：电源电路，接收所提供的外部电源电压，并输出不高于外部电源电压的内部电源电压; 接收内部电源电压并执行预定操作的系统模块; 以及性能监视电路，其在施加所述内部电源电压时测量所述系统模块的处理速度，并且基于所述处理速度，输出请求将所述外部电源电压设置为第一的第一控制信号电平和第二控制信号，其请求所述电源电路将内部电源电压设定在第二电平。电源电路基于施加到其上的第二控制信号输出具有第二电平的内部电源电压。

3. 发明授权

US5399894A Semiconductor device having bipolar transistor and MOS transistor 失效
标题翻译：具有双极晶体管和MOS晶体管的半导体器件
公开(公告)号：US5399894A
公开(公告)日：1995-03-21
申请号：US23153
申请日：1992-10-28
申请人： Takeo Maeda , Hiroshi Momose , Yukihiro Urakawa , Masataka Matsui
发明人： Takeo Maeda , Hiroshi Momose , Yukihiro Urakawa , Masataka Matsui
IPC分类号： H01L29/73 , H01L21/331 , H01L21/8249 , H01L27/06 , H01L29/165 , H01L29/737 , H01L27/02 , H01L29/161
CPC分类号： H01L27/0623 , H01L29/7378
摘要： A semiconductor device of the present invention includes a bipolar transistor and MOS transistors which are formed on the same semiconductor substrate. The bipolar transistor is heterojunction transistor having a hetero junction. The hetero-bipolar transistor is a bipolar transistor of double-hetero structure in which a material used for forming the base region thereof has a band gap narrower than a material used for forming the emitter and collector regions thereof.
摘要翻译：本发明的半导体器件包括形成在同一半导体衬底上的双极晶体管和MOS晶体管。双极晶体管是具有异质结的异质结晶体管。异双极晶体管是双异质结构的双极晶体管，其中用于形成其基极区的材料的带隙比用于形成其发射极和集电极区域的材料窄。

4. 发明授权

US5357479A Static random access memory capable of preventing erroneous writing 失效
标题翻译：能够防止错误写入的静态随机存取存储器
公开(公告)号：US5357479A
公开(公告)日：1994-10-18
申请号：US693608
申请日：1991-04-30
申请人： Masataka Matsui
发明人： Masataka Matsui
IPC分类号： G11C8/10 , G11C8/18 , G11C11/407 , G11C11/418 , G11C7/00 , G11C8/00
CPC分类号： G11C8/10 , G11C11/418 , G11C8/18
摘要： Memory cell arranged in a matrix configuration are selected by a particular word line to supply the stored data to particular bit lines. The row address decoder selects a particular word line based on the address signal, while the column address decoder selects particular bit lines based on the address signal. Each of the row address decoder and column address decoder contains a first decoder for decoding the address signal, a delay circuit for delaying the output from the first decoder when data is written into the memory cell, and a second decoder for receiving the output signals from the first decoder and delay circuit and based on these signals, selecting either a particular word line or particular bit lines.
摘要翻译：通过特定字线选择以矩阵配置布置的存储单元，以将存储的数据提供给特定的位线。行地址解码器基于地址信号选择特定字线，而列地址解码器基于地址信号选择特定的位线。行地址解码器和列地址解码器中的每一个包含用于解码地址信号的第一解码器，用于当数据被写入存储单元时将来自第一解码器的输出延迟的延迟电路，以及用于从第一解码器接收来自第一解码器和延迟电路，并且基于这些信号，选择特定字线或特定位线。

5. 发明授权

US4815040A Static memory using a MIS field effect transistor 失效
标题翻译：使用MIS场效应晶体管的静态存储器
公开(公告)号：US4815040A
公开(公告)日：1989-03-21
申请号：US100640
申请日：1987-09-24
申请人： Masataka Matsui , Takayuki Ohtani
发明人： Masataka Matsui , Takayuki Ohtani
IPC分类号： G11C11/41 , G11C11/413 , G11C11/419 , G11C7/00
CPC分类号： G11C11/419
摘要： In a selected column, a pull-up transistor pair is not selected but, instead, a transmission gate transistor pair is selected. In the read mode, the transmission gate transistor pair serves as pull-up loads between the bit line pair. However, the transmission gate transistor pair is kept off until the voltage across the bit line pair is decreased from the power supply potential level to the threshold voltage level of the transmission gate transistors. Therefore, no DC current path is formed in the bit line pair when the voltage across the bit line pair is within a range from a voltage equal to the power supply potential level to a potential lower than the power supply potential by an amount equal to the threshold voltage level, and the rate of increase of a potential difference across the bit line pair is determined by a pull-in current of the memory cell. Therefore, a high-speed sense operation can be realized. In the write mode, the transmission gate transistor pair serves a bit line pull-up function. Since no normally-ON bit line load transistor is arranged, no direct current path including the bit line pair is present, and hence, low power consumption can be achieved.
摘要翻译：在选定的列中，不选择上拉晶体管对，而是选择传输栅极晶体管对。在读取模式下，传输栅极晶体管对用作位线对之间的上拉负载。然而，传输栅极晶体管对保持截止，直到位线对上的电压从电源电位电平降低到传输栅极晶体管的阈值电压电平。因此，当位线对上的电压在等于电源电位电平的电压到低于电源电位的电位的范围内时，在位线对中不形成直流电流路径，阈值电压电平，并且位线对上的电位差的增加速率由存储单元的引入电流决定。因此，可以实现高速感测操作。在写入模式下，传输栅极晶体管对用于位线上拉功能。由于没有布置正常导通的位线负载晶体管，所以不存在包括位线对的直流电路，因此可以实现低功耗。

6. 发明授权

US4813022A Static memory with pull-up circuit for pulling-up a potential on a bit line 失效
标题翻译：具有上拉电路的静态存储器，用于提升位线上的电位
公开(公告)号：US4813022A
公开(公告)日：1989-03-14
申请号：US136769
申请日：1987-12-22
申请人： Masataka Matsui , Tetsuya Iizuka , Jun-ichi Tsujimoto , Takayuki Ohtani , Mitsuo Isobe
发明人： Masataka Matsui , Tetsuya Iizuka , Jun-ichi Tsujimoto , Takayuki Ohtani , Mitsuo Isobe
IPC分类号： G11C11/417 , G11C7/12 , G11C11/41 , G11C11/413 , G11C11/419 , G11C7/00 , G11C11/34
CPC分类号： G11C7/12 , G11C11/419
摘要： The threshold voltage of bit line percharge/equalize MOS transistors is smaller than that of normally ON type bit line pull-up transistors. With this feature, there is no current flows through a bit line from power source V.sub.DD during a read-out operation. The voltage difference between a pair of bit lines can be increased at high speed, thereby increasing the read-out speed.
摘要翻译：位线的每个充电/均衡MOS晶体管的阈值电压小于通常的ON型位线上拉晶体管的阈值电压。通过这一功能，在读出操作期间，没有电流从电源VDD流过位线。可以高速地增加一对位线之间的电压差，从而增加读出速度。

7. 发明授权

US5930163A Semiconductor memory device having two P-well layout structure 失效
标题翻译：具有两个P阱布局结构的半导体存储器件
公开(公告)号：US5930163A
公开(公告)日：1999-07-27
申请号：US993180
申请日：1997-12-18
申请人： Hiroyuki Hara , Masataka Matsui
发明人： Hiroyuki Hara , Masataka Matsui
IPC分类号： H01L29/78 , H01L21/8238 , H01L21/8244 , H01L27/092 , H01L27/11 , G11C11/00
CPC分类号： H01L27/1104 , Y10S257/903
摘要： This invention relates to P- and N-well regions where inverters constituting an SRAM cell are formed. The P-well region is divided into two parts, which are laid out on the two sides of the N-well region. Boundaries (BL11, BL12) are formed to run parallel to bit lines (BL, /BL). With this layout, diffusion layers (ND1, ND2) within the P-well regions can be formed into simple shapes free from any bent portion, reducing the cell area.
摘要翻译：本发明涉及其中形成有构成SRAM单元的反相器的P-阱区域。 P井区分为两部分，分布在N井区两侧。边界（BL11，BL12）形成为平行于位线（BL，/ BL）延伸。通过这种布局，P阱区域内的扩散层（ND1，ND2）可以形成为没有任何弯曲部分的简单形状，从而减小了单元面积。

8. 发明授权

US5646873A Barrel shifter device and variable-length decoder 失效
标题翻译：桶式移位器和可变长度解码器
公开(公告)号：US5646873A
公开(公告)日：1997-07-08
申请号：US314735
申请日：1994-09-29
申请人： Takayoshi Shimazawa , Katsuhiro Seta , Masataka Matsui
发明人： Takayoshi Shimazawa , Katsuhiro Seta , Masataka Matsui
IPC分类号： G06F7/00 , G06F5/01 , G06F7/76 , H03M7/40
CPC分类号： G06F5/015
摘要： A first and second barrel shifters (BSA0 and BSA1) are connected directly without intervening any pipe-line register between the two, and a sense amplifier (R3A0) is provided at an output side of the second barrel register (BSA1). Further, the circuit patterns of the first and second barrel shifters are formed being overlapped with each other in such a way that the elements of one of the first and second barrel shifters are formed at the dead space of the other of the two barrel shifters to reduce the pattern area. In the shift circuit and the variable-length decoder, the data lines of the barrel shifters can be minimized in size and width.
摘要翻译：第一和第二桶形移位器（BSA0和BSA1）直接连接，而不插入两者之间的任何管线寄存器，并且在第二桶寄存器（BSA1）的输出侧提供读出放大器（R3A0）。此外，第一和第二桶形移位器的电路图案被形成为彼此重叠，使得第一和第二桶形移位器中的一个的元件形成在两个桶形移位器中的另一个的死区以至减少图案面积。在移位电路和可变长度解码器中，桶形移位器的数据线可以在尺寸和宽度上最小化。

9. 发明授权

US5337276A Read/write control device for random access memory 失效
标题翻译：随机存取存储器的读/写控制装置
公开(公告)号：US5337276A
公开(公告)日：1994-08-09
申请号：US969436
申请日：1992-10-30
申请人： Masataka Matsui
发明人： Masataka Matsui
IPC分类号： G11C11/413 , G11C7/22 , H01L27/10 , G11C7/00
CPC分类号： G11C7/22
摘要： A first threshold value for detecting a potential indicating a read state, and a second threshold value for detecting a write state are set in an inverter circuit, to which a read/write signal R/W for setting the state of a memory cell is supplied, by means of a P-channel transistor, an N-channel transistor, and another P-channel transistor which is much smaller in gate width than the above transistors. The first or second threshold value is selected by a logic circuit constituted by an inverter circuit and a delay circuit in accordance with the level of the read/write signal R/W. Therefore, a change from a read state to a write state and a reverse change can be detected at high speed, thus providing a read/write control circuit for a random access memory, which can increase the speed of a read operation immediately after a write operation while ensuring a sufficient data write time, and can shorten the write recovery time.
摘要翻译：用于检测指示读取状态的电位的第一阈值和用于检测写入状态的第二阈值被设置在反相器电路中，用于设置存储单元的状态的读/写信号R / W被提供到该反相器电路中通过P沟道晶体管，N沟道晶体管和栅极宽度比上述晶体管小得多的P沟道晶体管。第一或第二阈值由根据读/写信号R / W的电平由逆变器电路和延迟电路构成的逻辑电路选择。因此，可以高速检测从读取状态到写入状态和反向变化的改变，从而为随机存取存储器提供读/写控制电路，这可以在写入之后立即增加读取操作的速度同时确保数据写入时间足够，并可以缩短写入恢复时间。

10. 发明授权

US5010521A CMOS static memory 失效
标题翻译： CMOS静态存储器
公开(公告)号：US5010521A
公开(公告)日：1991-04-23
申请号：US401811
申请日：1989-09-01
申请人： Masataka Matsui
发明人： Masataka Matsui
IPC分类号： G11C11/407 , G11C11/412 , G11C11/418 , G11C11/419 , H01L21/8244 , H01L27/11
CPC分类号： G11C11/412 , G11C11/418 , G11C11/419
摘要： A CMOS static memory includes a memory cell array having a plurality of memory cells two-dimensionally arranged in word and bit line directions, and peripheral circuits including n-type MOSFETs for performing a write/read operation for the memory cell. The memory cell includes a flip-flop circuit constituted by a pair of pull-down n-type MOSFETs and a pair of pull-up resistor elements, and a pair of transmission gate n-type MOSFETs. Each of a pair of pull-down n-type MOSFETs and the pair of transmission gate n-type MOSFETs have a gate oxide film having a thickness and gate length which are smaller than those of a gate oxide film of each n-type MOSFET in the peripheral circuits.
摘要翻译： CMOS静态存储器包括具有以字和位线方向二维排列的多个存储单元的存储单元阵列，以及包括用于对存储单元进行写/读操作的n型MOSFET的外围电路。存储单元包括由一对下拉n型MOSFET和一对上拉电阻元件构成的触发电路，以及一对传输栅n型MOSFET。一对下拉式n型MOSFET和一对传输栅极n型MOSFET中的每一个具有栅极氧化膜，栅极氧化膜的厚度和栅极长度小于每个n型MOSFET的栅极氧化膜的厚度外围电路。

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