专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20070143719A1 Synthesizing current source driver model for analysis of cell characteristics 失效
标题翻译：合成电流源驱动器模型，用于分析电池特性
公开(公告)号：US20070143719A1
公开(公告)日：2007-06-21
申请号：US11311038
申请日：2005-12-19
申请人： Kaviraj Chopra , Chandramouli Kashyap , Haihua Su
发明人： Kaviraj Chopra , Chandramouli Kashyap , Haihua Su
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F17/5045
摘要： A method for performing an analysis of at least one logic stage in a netlist, which include one or more drivers, is provided. The method includes operations of generating at least one look-up table for an output transient current to be based on values of input and output voltages using data available from a cell library; synthesizing analytically at least one current source model, which includes a DC component and a plurality of parasitic capacitances, using the look-up table; simulating the logic stage using the current source model to model the drivers; and obtaining characteristics of the simulated logic stage. A system and a machine-readable medium for performing the method are also provided.
摘要翻译：提供了一种用于对包括一个或多个驱动程序的网表中的至少一个逻辑级执行分析的方法。该方法包括使用从单元库获得的数据，基于输入和输出电压的值来产生用于输出瞬态电流的至少一个查找表的操作; 使用查找表合成分析性的至少一个电流源模型，其包括DC分量和多个寄生电容; 使用当前的源模型模拟逻辑阶段来模拟驱动程序; 并获得仿真逻辑阶段的特性。还提供了一种用于执行该方法的系统和机器可读介质。

2. 发明申请

US20060190881A1 Method for estimating propagation noise based on effective capacitance in an integrated circuit chip 失效
标题翻译：基于集成电路芯片中的有效电容估计传播噪声的方法
公开(公告)号：US20060190881A1
公开(公告)日：2006-08-24
申请号：US11048422
申请日：2005-02-01
申请人： Haihua Su , David Widiger , Ying Liu , Byron Krauter , Chandramouli Kashyap
发明人： Haihua Su , David Widiger , Ying Liu , Byron Krauter , Chandramouli Kashyap
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A system and method for estimating propagation noise that is induced by a non-zero noise glitch at the input of the driver circuit. Such propagation noise is a function of both the input noise glitch and the driver output effective capacitive load, which is typically part of the total wiring capacitance due to resistive shielding in deep sub-micron interconnects. The noise-driven effective capacitance solution provided herein also estimates the propagation noise induced by a non-zero noise glitch at the input of the driving gate. Gate propagation noise rules describing a relationship between the output noise properties and the input noise properties and the output loading capacitance are used within the noise-driven effective capacitance process to determine the linear Thevenin model of the driving gate. The linearized Thevenin driver model is then employed to analyze both the propagation noise and the combined coupling and propagation noise typically seen in global signal nets.
摘要翻译：用于估计在驱动器电路的输入处由非零噪声毛刺引起的传播噪声的系统和方法。这种传播噪声是输入噪声毛刺和驱动器输出有效电容性负载两者的函数，这通常是由于深亚微米互连中的电阻屏蔽而导致的总布线电容的一部分。本文提供的噪声驱动的有效电容解决方案还估计在驱动门的输入处由非零噪声毛刺引起的传播噪声。在噪声驱动的有效电容过程中使用描述输出噪声特性和输入噪声特性与输出负载电容之间的关系的门传播噪声规则来确定驱动门的线性戴维宁模型。然后使用线性化的戴维南驱动器模型来分析传播噪声和通常在全局信号网中看到的组合耦合和传播噪声。

3. 发明授权

US07346867B2 Method for estimating propagation noise based on effective capacitance in an integrated circuit chip 失效
标题翻译：基于集成电路芯片中的有效电容估计传播噪声的方法
公开(公告)号：US07346867B2
公开(公告)日：2008-03-18
申请号：US11048422
申请日：2005-02-01
申请人： Haihua Su , David J. Widiger , Ying Liu , Byron L. Krauter , Chandramouli V. Kashyap
发明人： Haihua Su , David J. Widiger , Ying Liu , Byron L. Krauter , Chandramouli V. Kashyap
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A system and method for estimating propagation noise that is induced by a non-zero noise glitch at the input of the driver circuit. Such propagation noise is a function of both the input noise glitch and the driver output effective capacitive load, which is typically part of the total wiring capacitance due to resistive shielding in deep sub-micron interconnects. The noise-driven effective capacitance solution provided herein also estimates the propagation noise induced by a non-zero noise glitch at the input of the driving gate. Gate propagation noise rules describing a relationship between the output noise properties and the input noise properties and the output loading capacitance are used within the noise-driven effective capacitance process to determine the linear Thevenin model of the driving gate. The linearized Thevenin driver model is then employed to analyze both the propagation noise and the combined coupling and propagation noise typically seen in global signal nets.
摘要翻译：用于估计在驱动器电路的输入处由非零噪声毛刺引起的传播噪声的系统和方法。这种传播噪声是输入噪声毛刺和驱动器输出有效电容性负载两者的函数，这通常是由于深亚微米互连中的电阻屏蔽而导致的总布线电容的一部分。本文提供的噪声驱动的有效电容解决方案还估计在驱动门的输入处由非零噪声毛刺引起的传播噪声。在噪声驱动的有效电容过程中使用描述输出噪声特性和输入噪声特性与输出负载电容之间的关系的门传播噪声规则来确定驱动门的线性戴维宁模型。然后使用线性化的戴维南驱动器模型来分析传播噪声和通常在全局信号网中看到的组合耦合和传播噪声。

4. 发明授权

US07761275B2 Synthesizing current source driver model for analysis of cell characteristics 失效
标题翻译：合成电流源驱动器模型，用于分析电池特性
公开(公告)号：US07761275B2
公开(公告)日：2010-07-20
申请号：US11311038
申请日：2005-12-19
申请人： Kaviraj S. Chopra , Chandramouli V. Kashyap , Haihua Su
发明人： Kaviraj S. Chopra , Chandramouli V. Kashyap , Haihua Su
IPC分类号： G06G7/62
CPC分类号： G06F17/5036 , G06F17/5045
摘要： A method for performing an analysis of at least one logic stage in a netlist, which include one or more drivers, is provided. The method includes operations of generating at least one look-up table for an output transient current to be based on values of input and output voltages using data available from a cell library; synthesizing analytically at least one current source model, which includes a DC component and a plurality of parasitic capacitances, using the look-up table; simulating the logic stage using the current source model to model the drivers; and obtaining characteristics of the simulated logic stage. A system and a machine-readable medium for performing the method are also provided.
摘要翻译：提供了一种用于对包括一个或多个驱动程序的网表中的至少一个逻辑级执行分析的方法。该方法包括使用从单元库获得的数据，基于输入和输出电压的值来产生用于输出瞬态电流的至少一个查找表的操作; 使用查找表合成分析性的至少一个电流源模型，其包括DC分量和多个寄生电容; 使用当前的源模型模拟逻辑阶段来模拟驱动程序; 并获得仿真逻辑阶段的特性。还提供了一种用于执行该方法的系统和机器可读介质。

5. 发明授权

US06842714B1 Method for determining the leakage power for an integrated circuit 失效
标题翻译：确定集成电路漏电功率的方法
公开(公告)号：US06842714B1
公开(公告)日：2005-01-11
申请号：US10646426
申请日：2003-08-22
申请人： Emrah Acar , Anirudh Devgan , Ying Liu , Sani R. Nassif , Haihua Su
发明人： Emrah Acar , Anirudh Devgan , Ying Liu , Sani R. Nassif , Haihua Su
IPC分类号： G01R31/30 , G01R21/00 , G06F15/00 , G06F19/00
CPC分类号： G01R31/3004 , G01R31/3008
摘要： A method for determining full chip leakage power first estimates leakage power and dynamic power for each circuit macro. The power supply voltage to each macro is first assumed to be nominal. The power dissipation for each macro is modeled as a current source whose value is the estimated power divided by the nominal power supply voltage. The power distribution network is modeled as a resistive grids. The thermal environment of the IC and its electronic package are modeled as multi dimensional grids of thermal elements. Algebraic multi-grid (AMG) methods are used to calculate updated circuit macro voltages and temperatures. The macro voltages and temperatures are updated and updated leakage and dynamic power dissipation are calculated. Iterations are continued until leakage power converges to a final value.
摘要翻译：用于确定全芯片泄漏功率的方法首先估计每个电路宏的泄漏功率和动态功率。首先假设每个宏的电源电压为标称值。每个宏的功耗被建模为电流源，其值是估计功率除以标称电源电压。配电网被建模为电阻网格。 IC及其电子封装的热环境被模拟为热元件的多维栅格。代数多网格（AMG）方法用于计算更新的电路宏观电压和温度。更新宏电压和温度，并计算泄漏和动态功耗。直到泄漏功率收敛到最终值为止，继续进行迭代。

6. 发明授权

US06898769B2 Decoupling capacitor sizing and placement 失效
标题翻译：去耦电容器尺寸和放置
公开(公告)号：US06898769B2
公开(公告)日：2005-05-24
申请号：US10268236
申请日：2002-10-10
申请人： Sani Richard Nassif , Haihua Su
发明人： Sani Richard Nassif , Haihua Su
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A method and system for reducing noise in a power grid of an integrated circuit, which optimizes the placement and sizing of decoupling capacitors in the power grid. Logic cells are located in a first layout of the integrated circuit with empty spaces between the adjacent cells, and the placement of the cells is changed to a second layout wherein the size of the empty spaces between the adjacent cells also change. The decoupling capacitors are placed in the empty spaces of the second layout. In the example of a row-oriented cell structure, the empty spaces may be uniformly distributed along each row for the initial layout. An adjoint sensitivity analysis is performed of the sensitivity of a noise function of the integrated circuit with respect to sizes of the empty spaces between adjacent cells, and an original noise waveform is convolved with an adjoint noise waveform. The convolution may use piecewise linear compressions of the original and adjoint noise waveforms. A quadratic programming solver is then used to iteratively determine the sizes of the empty spaces between adjacent cells.
摘要翻译：一种用于降低集成电路电网噪声的方法和系统，其优化了电网中去耦电容器的布局和尺寸。逻辑单元位于集成电路的第一布局中，在相邻单元之间具有空白空间，并且单元的布置被改变为第二布局，其中相邻单元之间的空白空间的大小也改变。去耦电容器被放置在第二布局的空的空间中。在面向行的单元结构的示例中，空格可以沿着每一行均匀地分布用于初始布局。执行集成电路的噪声功能相对于相邻小区之间的空白空间的大小的灵敏度的伴随灵敏度分析，原始噪声波形与伴随噪声波形卷积。卷积可以使用原始和伴随噪声波形的分段线性压缩。然后使用二次规划求解器来迭代地确定相邻单元之间的空白空间的大小。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式