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1. 发明授权

US06756981B2 Graphics processor and system for determining colors of the vertices of a figure 失效
标题翻译：用于确定图形顶点颜色的图形处理器和系统
公开(公告)号：US06756981B2
公开(公告)日：2004-06-29
申请号：US10223600
申请日：2002-08-20
申请人： Katsunori Suzuki , Ryo Fujita , Kazuyoshi Koga , Yuichi Abe , Mitsuru Soga , Kazuhisa Takami , Koyo Katsura , Hideki Fujii , Kazunori Oniki
发明人： Katsunori Suzuki , Ryo Fujita , Kazuyoshi Koga , Yuichi Abe , Mitsuru Soga , Kazuhisa Takami , Koyo Katsura , Hideki Fujii , Kazunori Oniki
IPC分类号： G06T1500
CPC分类号： G06T15/506 , G06T15/50
摘要： A graphics processor comprises: a light source table holding light source data; a conversion unit for converting the light source data to be set in the light source table from a float type (single-precision floating point real number type) into an int type (integer type); an inner product calculation unit for calculating the inner products of normal directions, light source directions and sight line directions at the vertices based on the light source data; and a color calculation unit for performing light source computations based on the calculated inner products to determine the colors of the vertices.
摘要翻译：图形处理器包括：保持光源数据的光源表; 转换单元，用于将在光源表中设置的光源数据从浮点型（单精度浮点实数型）转换成int型（整数型）; 内积计算单元，用于基于光源数据计算顶点的法线方向，光源方向和视线方向的内积; 以及颜色计算单元，用于基于所计算的内积执行光源计算，以确定顶点的颜色。

2. 发明授权

US6118453A Graphics processor and system for determining colors of the vertices of a figure 失效
公开(公告)号：US6118453A
公开(公告)日：2000-09-12
申请号：US769356
申请日：1996-12-19
申请人： Katsunori Suzuki , Ryo Fujita , Kazuyoshi Koga , Yuichi Abe , Mitsuru Soga , Kazuhisa Takami , Koyo Katsura , Hideki Fujii , Kazunori Oniki
发明人： Katsunori Suzuki , Ryo Fujita , Kazuyoshi Koga , Yuichi Abe , Mitsuru Soga , Kazuhisa Takami , Koyo Katsura , Hideki Fujii , Kazunori Oniki
IPC分类号： G06T15/00 , G06T15/50 , G06T15/80
CPC分类号： G06T15/506 , G06T15/50
摘要： A graphics processor comprises: a light source table holding light source data; a conversion unit for converting the light source data to be set in the light source table from a float type (single-precision floating point real number type) into an int type (integer type); an inner product calculation unit for calculating the inner products of normal directions, light source directions and sight line directions at the vertices based on the light source data; and a color calculation unit for performing light source computations based on the calculated inner products to determine the colors of the vertices.

3. 发明申请

US20060250397A1 Graphics processing unit and graphics processing system 审中-公开
公开(公告)号：US20060250397A1
公开(公告)日：2006-11-09
申请号：US11484812
申请日：2006-07-12
申请人： Yuichi Abe , Ryo Fujita , Katsunori Suzuki , Kazuhisa Takami , Kazunori Oniki
发明人： Yuichi Abe , Ryo Fujita , Katsunori Suzuki , Kazuhisa Takami , Kazunori Oniki
IPC分类号： G06T15/50
CPC分类号： G06T15/50 , G06F1/0307 , G06T1/20
摘要： A device for controlling the table capacity smaller comprises a table of logarithms and a table of exponents preserving values of a logarithmic function and exponential function with a base of the second power, a multiplier, a shift unit for shifting the input value by a proper integer when the domain of logarithm is not included in the input value range of the table of logarithms, a logarithm addition unit for adding the shift amount to the value referred to in the table of logarithms, an exponent subtraction unit for subtracting a proper integer L from the input value when the domain of the exponential function is not included in the input value range of the table of exponents, and an exponent shift unit for shifting the referred value in the table of exponents the subtraction amount. A high-speed processing unit comprises a converter for converting floating-point data to fixed-point data having a bit of decimal point. By doing this, a structured graphics system can perform high-speed processing with a small table capacity.

4. 发明授权

US6049343A Graphics processing unit and graphics processing system 失效
公开(公告)号：US6049343A
公开(公告)日：2000-04-11
申请号：US9588
申请日：1998-01-20
申请人： Yuichi Abe , Ryo Fujita , Katsunori Suzuki , Kazuhisa Takami , Kazunori Oniki
发明人： Yuichi Abe , Ryo Fujita , Katsunori Suzuki , Kazuhisa Takami , Kazunori Oniki
IPC分类号： G06F1/03 , G06T1/20 , G06T15/50 , G06T1/00 , G06F15/00
CPC分类号： G06T15/50 , G06F1/0307 , G06T1/20
摘要： A device for controlling the table capacity smaller comprises a table of logarithms and a table of exponents preserving values of a logarithmic function and exponential function with a base of the second power, a multiplier, a shift unit for shifting the input value by a proper integer when the domain of logarithm is not included in the input value range of the table of logarithms, a logarithm addition unit for adding the shift amount to the value referred to in the table of logarithms, an exponent subtraction unit for subtracting a proper integer L from the input value when the domain of the exponential function is not included in the input value range of the table of exponents, and an exponent shift unit for shifting the referred value in the table of exponents the subtraction amount. A high-speed processing unit comprises a converter for converting floating-point data to fixed-point data having a bit of decimal point. By doing this, a structured graphics system can perform high-speed processing with a small table capacity.

5. 发明授权

US5666520A Graphics display system including graphics processor having a register storing a series of vertex data relating to a polygonal line 失效
标题翻译：图形显示系统，包括具有存储与多边形线相关的一系列顶点数据的寄存器的图形处理器
公开(公告)号：US5666520A
公开(公告)日：1997-09-09
申请号：US215244
申请日：1994-03-21
申请人： Ryo Fujita , Kazuhisa Takami , Mitsuru Soga , Koji Ozawa , Takaharu Morishige , Kazuyoshi Koga
发明人： Ryo Fujita , Kazuhisa Takami , Mitsuru Soga , Koji Ozawa , Takaharu Morishige , Kazuyoshi Koga
IPC分类号： G06T1/20 , G06T11/20 , G06F12/00
CPC分类号： G06T11/203 , G06T1/20
摘要： A graphics display system includes a host processor calculating graphic data and providing the graphic data to a graphics processor, and frame memories which store the graphic pixel data and supply display data to display devices. The graphics display system also includes a first register group which stores the graphics data, a second register group which converts and/or stores the data in the first register group, a pixel generator which generates pixels according to the graphic data in the second register group, and a plotter which writes the pixel data generated in the pixel generator in the frame memories. The second register group fetches the data from the first register group when the host processor issues a command for plotting, holds the data previously written by the host processor. At the same time, when the host processor issues a command for plotting, the specified graphic type is written in the graphic processor as sell as data calculated based on the first and second register groups.
摘要翻译：图形显示系统包括主处理器，其计算图形数据并将图形数据提供给图形处理器，以及存储图形像素数据并向显示装置提供显示数据的帧存储器。图形显示系统还包括存储图形数据的第一寄存器组，在第一寄存器组中转换和/或存储数据的第二寄存器组，根据第二寄存器组中的图形数据生成像素的像素生成器，以及将在像素生成器中生成的像素数据写入帧存储器的绘图仪。当主机处理器发出绘制命令时，第二个寄存器组从第一个寄存器组中获取数据，保存由主机处理器先前写入的数据。同时，当主机处理器发出用于绘图的命令时，指定的图形类型以作为基于第一和第二寄存器组计算的数据作为卖出而被写入图形处理器。

6. 发明授权

US5847715A Graphics display system including parallel graphics processors executing Bresenham's algorithm 失效
标题翻译：图形显示系统包括执行Bresenham算法的并行图形处理器
公开(公告)号：US5847715A
公开(公告)日：1998-12-08
申请号：US856081
申请日：1997-05-14
申请人： Ryo Fujita , Kazuhisa Takami , Mitsuru Soga , Koji Ozawa , Takaharu Morishige , Kazuyoshi Koga
发明人： Ryo Fujita , Kazuhisa Takami , Mitsuru Soga , Koji Ozawa , Takaharu Morishige , Kazuyoshi Koga
IPC分类号： G06T1/20 , G06T11/20 , G06F17/10
CPC分类号： G06T11/203 , G06T1/20
摘要： A graphics display system includes a host processor calculating graphic data and providing the graphic data to a graphics processor, and frame memories which store the graphic pixel data and supply display data to display devices. The graphics display system also includes a first register group which stores the graphics data, a second register group which converts and/or stores the data in the first register group, a pixel generator which generates pixels according to the graphic data in the second register group, and a plotter which writes the pixel data generated in the pixel generator in the frame memories. The second register group fetches the data from the first register group when the host processor issues a command for plotting, holds the data previously written by the host processor. At the same time, when the host processor issues a command for plotting, the specified graphic type is written in the graphic processor as well as data calculated based on the first and second register groups.
摘要翻译：图形显示系统包括主处理器，其计算图形数据并将图形数据提供给图形处理器，以及存储图形像素数据并向显示装置提供显示数据的帧存储器。图形显示系统还包括存储图形数据的第一寄存器组，在第一寄存器组中转换和/或存储数据的第二寄存器组，根据第二寄存器组中的图形数据生成像素的像素生成器，以及将在像素生成器中生成的像素数据写入帧存储器的绘图仪。当主机处理器发出绘制命令时，第二个寄存器组从第一个寄存器组中获取数据，保存由主机处理器先前写入的数据。同时，当主机处理器发出绘制命令时，指定的图形类型被写入图形处理器以及基于第一和第二寄存器组计算的数据。

7. 发明授权

US06344809B1 Line interface circuit and information communication apparatus using it 有权
标题翻译：线路接口电路和使用它的信息通信设备
公开(公告)号：US06344809B1
公开(公告)日：2002-02-05
申请号：US09704687
申请日：2000-11-03
申请人： Nobuyasu Kanekawa , Yasuyuki Kojima , Seigou Yukutake , Minehiro Nemoto , Kazuhisa Takami , Takayuki Iwasaki , Yusuke Takeuchi , Yasuo Shima
发明人： Nobuyasu Kanekawa , Yasuyuki Kojima , Seigou Yukutake , Minehiro Nemoto , Kazuhisa Takami , Takayuki Iwasaki , Yusuke Takeuchi , Yasuo Shima
IPC分类号： H03M900
CPC分类号： H04L12/10 , H04M1/573 , H04M3/005
摘要： In order to reduce the consumption of power of an isolator interface and an ADC, it is proposed to operate a calling signal reception or Caller ID signal reception function only with power supplied from the system switch while maintaining the on-hook condition of a telephone. At the time of normal operation, the output of the analogue digital converter is input to an isolator through the isolator interface, and at the time of the calling signal reception or the caller identification information reception, the output of the analogue digital converter is input directly to the isolator.
摘要翻译：为了减少隔离器接口和ADC的功率消耗，建议仅在保持电话机的挂机状态的同时从系统交换机提供的电源来操作呼叫信号接收或来电显示信号接收功能。在正常运行时，模拟数字转换器的输出通过隔离器接口输入到隔离器，在呼叫信号接收或来电识别信息接收时，模拟数字转换器的输出直接输入到隔离器。

8. 发明授权

US09118173B2 Digital Protection control system and digital protection control apparatus 有权
标题翻译：数字保护控制系统和数字保护控制装置
公开(公告)号：US09118173B2
公开(公告)日：2015-08-25
申请号：US13576843
申请日：2010-02-03
申请人： Chikashi Komatsu , Mitsuyasu Kido , Shoji Yoshida , Kazuhisa Takami
发明人： Chikashi Komatsu , Mitsuyasu Kido , Shoji Yoshida , Kazuhisa Takami
IPC分类号： H02H3/00 , H02H7/00 , H02H7/26 , H02H1/00
CPC分类号： H02H1/0061 , H02H1/0084 , H02H7/261
摘要： Disclosed are a digital protection control system and a digital protection control apparatus, wherein the digital protection control apparatus can easily be made to have more terminals, even when the number of terminals of a power transmission line increases. The digital protection control system has, as terminal stations thereof, a reference station that is to become the reference point for the sampling time at which power grid current information is to be taken in, tail-end stations that take in power grid current information from the power grid system, and intermediate stations that are connected between the reference station and the tail-end stations via transmission paths. The intermediate station is provided with an uplink transmission unit that is connected to a transmission path at the reference station side thereof, and a plurality of downlink transmission units that are connected to transmission paths at the tail-end station side thereof. The intermediate station also has the time thereof to be subordinate to the time of the terminal station connected to the uplink transmission unit thereof, and the time of the terminal stations connected to the downlink transmission units thereof are made to be subordinate to the intermediate station, with the time thereof used as reference time.
摘要翻译：公开了一种数字保护控制系统和数字保护控制装置，其中即使当输电线路的端子数量增加时，也可以容易地使数字保护控制装置具有更多的端子。数字保护控制系统作为其终端站具有要成为要采集电网电流信息的采样时间的参考点的参考站，从电网电流信息中获取电力网电流信息的尾端站电网系统和通过传输路径连接在参考站和尾端站之间的中间站。中间站设置有连接到其参考站侧的传输路径的上行链路传输单元，以及在其尾端站侧连接到传输路径的多个下行链路传输单元。中间站也具有从属于连接到其上行链路传输单元的终端的时间，并且连接到其下行链路传输单元的终端的时间被制成从属于中间站的时间，其时间用作参考时间。

9. 发明申请

US20140146430A1 Digital Protection Control System and Digital Protection Control Apparatus 有权
标题翻译：数字保护控制系统和数字保护控制装置
公开(公告)号：US20140146430A1
公开(公告)日：2014-05-29
申请号：US13576843
申请日：2010-02-03
申请人： Chikashi Komatsu , Mitsuyasu Kido , Shoji Yoshida , Kazuhisa Takami
发明人： Chikashi Komatsu , Mitsuyasu Kido , Shoji Yoshida , Kazuhisa Takami
IPC分类号： H02H1/00
CPC分类号： H02H1/0061 , H02H1/0084 , H02H7/261
摘要： Disclosed are a digital protection control system and a digital protection control apparatus, wherein the digital protection control apparatus can easily be made to have more terminals, even when the number of terminals of a power transmission line increases. The digital protection control system has, as terminal stations thereof, a reference station that is to become the reference point for the sampling time at which power grid current information is to be taken in, tail-end stations that take in power grid current information from the power grid system, and intermediate stations that are connected between the reference station and the tail-end stations via transmission paths. The intermediate station is provided with an uplink transmission unit that is connected to a transmission path at the reference station side thereof, and a plurality of downlink transmission units that are connected to transmission paths at the tail-end station side thereof. The intermediate station also has the time thereof to be subordinate to the time of the terminal station connected to the uplink transmission unit thereof, and the time of the terminal stations connected to the downlink transmission units thereof are made to be subordinate to the intermediate station, with the time thereof used as reference time.
摘要翻译：公开了一种数字保护控制系统和数字保护控制装置，其中即使当输电线路的端子数量增加时，也可以容易地使数字保护控制装置具有更多的端子。数字保护控制系统作为其终端站具有要成为要采集电网电流信息的采样时间的参考点的参考站，从电网电流信息中获取电力电流信息的尾端站电网系统和通过传输路径连接在参考站和尾端站之间的中间站。中间站设置有连接到其参考站侧的传输路径的上行链路传输单元，以及在其尾端站侧连接到传输路径的多个下行链路传输单元。中间站也具有从属于连接到其上行链路传输单元的终端的时间，并且连接到其下行链路传输单元的终端的时间被制成从属于中间站的时间，其时间用作参考时间。

10. 发明授权

US06476750B1 Over-sampling A/D, D/A converter 失效
标题翻译：过采样A / D，D / A转换器
公开(公告)号：US06476750B1
公开(公告)日：2002-11-05
申请号：US09485349
申请日：2000-02-09
申请人： Nobuyasu Kanekawa , Yasuyuki Kojima , Seigou Yukutake , Minehiro Nemoto , Kazuhisa Takami , Takayuki Iwasaki , Yusuke Takeuchi , Katsuhiro Furukawa
发明人： Nobuyasu Kanekawa , Yasuyuki Kojima , Seigou Yukutake , Minehiro Nemoto , Kazuhisa Takami , Takayuki Iwasaki , Yusuke Takeuchi , Katsuhiro Furukawa
IPC分类号： H03M112
CPC分类号： H03M3/392 , H03M3/498
摘要： The hardware of an over-sampling A/D and D/A converter is provided, which hardware is capable of being operated with either kind of software: one corresponding to a first method in which the over-sampling ratio is fixed and the other corresponding to a second method in which the over-sampling ratio is variable. The value N3 written on the pseudo-frequency-dividing-ratio-register 11 and the value N4 written on the pseudo-over-sampling-ratio-register 21 are converted through a user interface into the frequency dividing ratio N1 by the conversion circuit 12 and the converted result is written in the frequency-dividing-ratio-register 10.
摘要翻译：提供过采样A / D和D / A转换器的硬件，哪个硬件能够使用任何一种软件进行操作：一种对应于过采样率固定的第一种方法，另一种对应到过采样比是可变的第二种方法。写入伪分频比寄存器11的值N3和写在伪过采样比寄存器21上的值N4由转换电路12通过用户接口转换成分频比N1 转换后的结果写入分频比寄存器10。

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