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1. 发明申请

US20070226669A1 Method and apparatus for repeat execution of delay analysis in circuit design 失效
标题翻译：在电路设计中重复执行延迟分析的方法和装置
公开(公告)号：US20070226669A1
公开(公告)日：2007-09-27
申请号：US11524342
申请日：2006-09-20
申请人： Izumi Nitta , Toshiyuki Shibuya , Katsumi Homma , Hidetoshi Matsuoka
发明人： Izumi Nitta , Toshiyuki Shibuya , Katsumi Homma , Hidetoshi Matsuoka
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： An apparatus includes: a detecting unit that detects a target path from among a plurality of paths in a target circuit based on a result of a delay analysis of the target circuit, wherein the result of the delay analysis includes delay data of a first circuit component of the target path; an extracting unit that extracts delay data of a second circuit component having an identical type to that of the first circuit component; and a generating unit that generates a directive for replacing the first circuit component with the second circuit component.
摘要翻译：一种装置包括：检测单元，基于目标电路的延迟分析结果，从目标电路中的多个路径中检测目标路径，其中延迟分析的结果包括第一电路部件的延迟数据的目标路径; 提取单元，其提取具有与所述第一电路部件相同类型的第二电路部件的延迟数据; 以及生成单元，其生成用于用第二电路部件替换第一电路部件的指令。

2. 发明授权

US07516432B2 Circuit delay analyzing method, circuit delay analyzing apparatus, and computer product 有权
标题翻译：电路延迟分析方法，电路延迟分析装置和计算机产品
公开(公告)号：US07516432B2
公开(公告)日：2009-04-07
申请号：US11521138
申请日：2006-09-14
申请人： Katsumi Homma , Toshiyuki Shibuya , Hidetoshi Matsuoka , Izumi Nitta
发明人： Katsumi Homma , Toshiyuki Shibuya , Hidetoshi Matsuoka , Izumi Nitta
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A delay analyzing apparatus receives a result of timing analysis of a target circuit, and detects, from paths in the target circuit, critical paths based on the result of the timing analysis with a detecting unit. A first calculating unit calculates an average delay distribution of the paths other than the critical paths based on an average delay value of each of the critical paths. A second calculating unit calculates a probability density distribution of the critical paths, and a third calculating unit calculates a probability density distribution of all of the paths based on the average delay distribution. A fourth calculating unit calculates difference between a statistical delay value of the critical paths and a statistical delay value of all of the paths based on the probability density distribution of the critical paths and the probability density distribution of all of the paths.
摘要翻译：延迟分析装置接收目标电路的定时分析结果，并根据检测单元的定时分析结果从目标电路中的路径检测关键路径。第一计算单元基于每个关键路径的平均延迟值来计算除了关键路径之外的路径的平均延迟分布。第二计算单元计算关键路径的概率密度分布，第三计算单元基于平均延迟分布来计算所有路径的概率密度分布。第四计算单元基于关键路径的概率密度分布和所有路径的概率密度分布来计算关键路径的统计延迟值与所有路径的统计延迟值之间的差异。

3. 发明授权

US07320118B2 Delay analysis device, delay analysis method, and computer product 有权
标题翻译：延迟分析装置，延迟分析方法和计算机产品
公开(公告)号：US07320118B2
公开(公告)日：2008-01-15
申请号：US11315173
申请日：2005-12-23
申请人： Katsumi Homma , Toshiyuki Shibuya , Hidetoshi Matsuoka , Izumi Nitta
发明人： Katsumi Homma , Toshiyuki Shibuya , Hidetoshi Matsuoka , Izumi Nitta
IPC分类号： G06F17/50
CPC分类号： G06F17/504 , G06F2217/84
摘要： A delay analysis device includes a receiving unit that receives a result of a timing analysis of a target circuit to be analyzed, a detecting unit that detects critical paths having delays within a predetermined range, a statistical-delay computing unit that computes a statistical delay of the target circuit based on a cumulative probability distribution of the delays of the critical paths, and a probability-density-distribution computing unit that computes a probability density distribution of delay of a critical path that has the greatest delay in the result. The detecting unit detects x number of critical paths having cumulative delays within computed probability density distribution.
摘要翻译：延迟分析装置包括：接收单元，其接收要分析的目标电路的定时分析的结果;检测单元，其检测具有在预定范围内的延迟的关键路径;计算统计延迟的统计延迟计算单元，基于关键路径的延迟的累积概率分布的目标电路，以及计算结果中具有最大延迟的关键路径的延迟的概率密度分布的概率密度分布计算单元。检测单元检测在计算的概率密度分布内具有累积延迟的x个关键路径。

4. 发明授权

US07681161B2 Circuit delay analyzer, circuit delay analyzing method, and computer product 有权
标题翻译：电路延迟分析仪，电路延迟分析方法和电脑产品
公开(公告)号：US07681161B2
公开(公告)日：2010-03-16
申请号：US11902489
申请日：2007-09-21
申请人： Katsumi Homma , Hidetoshi Matsuoka , Izumi Nitta , Toshiyuki Shibuya
发明人： Katsumi Homma , Hidetoshi Matsuoka , Izumi Nitta , Toshiyuki Shibuya
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F2217/10 , G06F2217/84
摘要： Delay analysis performed on a circuit having multiple parallel partial circuits (paths) involves recursively integrating two paths of the circuit using an all-element delay distribution that indicates delay based on performance of all circuit elements in a path and a correlation delay distribution that indicates delay based on correlation between circuit elements in the path. An all-element delay distribution is calculated for the integrated path using the all-element delay distributions of the two paths to be integrated. The all-element delay distributions and the correlation delay distributions of two paths to be integrated are used to calculate a total delay distribution for the integrated path. The total delay distribution is used with the all-element delay distribution for the integrated path to calculate a correlation delay distribution for the integrated path. Through recursive calculation, a delay distribution of the circuit is estimated.
摘要翻译：对具有多个并行部分电路（路径）的电路进行延迟分析涉及使用基于路径中的所有电路元件的性能的指示延迟的全元延迟分布递归地积分电路的两个路径，以及指示延迟的相关延迟分布基于路径中的电路元件之间的相关性。使用要集成的两个路径的全元素延迟分布，针对集成路径计算全元素延迟分布。要整合的两个路径的全元素延迟分布和相关延迟分布用于计算集成路径的总延迟分布。总延迟分布与集成路径的全元素延迟分布一起使用，以计算集成路径的相关延迟分布。通过递归计算，估计电路的延迟分布。

5. 发明授权

US07653889B2 Method and apparatus for repeat execution of delay analysis in circuit design 失效
标题翻译：在电路设计中重复执行延迟分析的方法和装置
公开(公告)号：US07653889B2
公开(公告)日：2010-01-26
申请号：US11524342
申请日：2006-09-20
申请人： Izumi Nitta , Toshiyuki Shibuya , Katsumi Homma , Hidetoshi Matsuoka
发明人： Izumi Nitta , Toshiyuki Shibuya , Katsumi Homma , Hidetoshi Matsuoka
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5031
摘要： An apparatus includes: a detecting unit that detects a target path from among a plurality of paths in a target circuit based on a result of a delay analysis of the target circuit, wherein the result of the delay analysis includes delay data of a first circuit component of the target path; an extracting unit that extracts delay data of a second circuit component having an identical type to that of the first circuit component; and a generating unit that generates a directive for replacing the first circuit component with the second circuit component.
摘要翻译：一种装置包括：检测单元，基于目标电路的延迟分析结果，从目标电路中的多个路径中检测目标路径，其中延迟分析的结果包括第一电路部件的延迟数据的目标路径; 提取单元，其提取具有与所述第一电路部件相同类型的第二电路部件的延迟数据; 以及生成单元，其生成用于用第二电路部件替换第一电路部件的指令。

6. 发明申请

US20070204248A1 Delay analyzing method, delay analyzing apparatus, and computer product 有权
标题翻译：延迟分析方法，延迟分析仪器和计算机产品
公开(公告)号：US20070204248A1
公开(公告)日：2007-08-30
申请号：US11521138
申请日：2006-09-14
申请人： Katsumi Homma , Toshiyuki Shibuya , Hidetoshi Matsuoka , Izumi Nitta
发明人： Katsumi Homma , Toshiyuki Shibuya , Hidetoshi Matsuoka , Izumi Nitta
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A delay analyzing apparatus receives a result of timing analysis of a target circuit, and detects, from paths in the target circuit, critical paths based on the result of the timing analysis with a detecting unit. A first calculating unit calculates an average delay distribution of the paths other than the critical paths based on an average delay value of each of the critical paths. A second calculating unit calculates a probability density distribution of the critical paths, and a third calculating unit calculates a probability density distribution of all of the paths based on the average delay distribution. A fourth calculating unit calculates difference between a statistical delay value of the critical paths and a statistical delay value of all of the paths based on the probability density distribution of the critical paths and the probability density distribution of all of the paths.
摘要翻译：延迟分析装置接收目标电路的定时分析结果，并根据检测单元的定时分析结果从目标电路中的路径检测关键路径。第一计算单元基于每个关键路径的平均延迟值来计算除了关键路径之外的路径的平均延迟分布。第二计算单元计算关键路径的概率密度分布，第三计算单元基于平均延迟分布来计算所有路径的概率密度分布。第四计算单元基于关键路径的概率密度分布和所有路径的概率密度分布来计算关键路径的统计延迟值与所有路径的统计延迟值之间的差异。

7. 发明申请

US20070074138A1 Delay analysis device, delay analysis method, and computer product 有权
标题翻译：延迟分析装置，延迟分析方法和计算机产品
公开(公告)号：US20070074138A1
公开(公告)日：2007-03-29
申请号：US11315173
申请日：2005-12-23
申请人： Katsumi Homma , Toshiyuki Shibuya , Hidetoshi Matsuoka , Izumi Nitta
发明人： Katsumi Homma , Toshiyuki Shibuya , Hidetoshi Matsuoka , Izumi Nitta
IPC分类号： G06F17/50
CPC分类号： G06F17/504 , G06F2217/84
摘要： A delay analysis device includes a receiving unit that receives a result of a timing analysis of a target circuit to be analyzed, a detecting unit that detects critical paths having delays within a predetermined range, a statistical-delay computing unit that computes a statistical delay of the target circuit based on a cumulative probability distribution of the delays of the critical paths, and a probability-density-distribution computing unit that computes a probability density distribution of delay of a critical path that has the greatest delay in the result. The detecting unit detects x number of critical paths having cumulative delays within computed probability density distribution.
摘要翻译：延迟分析装置包括：接收单元，其接收要分析的目标电路的定时分析的结果;检测单元，其检测具有在预定范围内的延迟的关键路径;计算统计延迟的统计延迟计算单元，基于关键路径的延迟的累积概率分布的目标电路，以及计算结果中具有最大延迟的关键路径的延迟的概率密度分布的概率密度分布计算单元。检测单元检测在计算的概率密度分布内具有累积延迟的x个关键路径。

8. 发明申请

US20080148205A1 Circuit delay analyzer, circuit delay analyzing method, and computer product 有权
标题翻译：电路延迟分析仪，电路延迟分析方法和电脑产品
公开(公告)号：US20080148205A1
公开(公告)日：2008-06-19
申请号：US11902489
申请日：2007-09-21
申请人： Katsumi Homma , Hidetoshi Matsuoka , Izumi Nitta , Toshiyuki Shibuya
发明人： Katsumi Homma , Hidetoshi Matsuoka , Izumi Nitta , Toshiyuki Shibuya
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F2217/10 , G06F2217/84
摘要： Delay analysis performed on a circuit having multiple parallel partial circuits (paths) involves recursively integrating two paths of the circuit using an all-element delay distribution that indicates delay based on performance of all circuit elements in a path and a correlation delay distribution that indicates delay based on correlation between circuit elements in the path. An all-element delay distribution is calculated for the integrated path using the all-element delay distributions of the two paths to be integrated. The all-element delay distributions and the correlation delay distributions of two paths to be integrated are used to calculate a total delay distribution for the integrated path. The total delay distribution is used with the all-element delay distribution for the integrated path to calculate a correlation delay distribution for the integrated path. Through recursive calculation, a delay distribution of the circuit is estimated.
摘要翻译：对具有多个并行部分电路（路径）的电路进行延迟分析涉及使用基于路径中的所有电路元件的性能的指示延迟的全元延迟分布递归地积分电路的两个路径，以及指示延迟的相关延迟分布基于路径中的电路元件之间的相关性。使用要集成的两个路径的全元素延迟分布，针对集成路径计算全元素延迟分布。要整合的两个路径的全元素延迟分布和相关延迟分布用于计算集成路径的总延迟分布。总延迟分布与集成路径的全元素延迟分布一起使用，以计算集成路径的相关延迟分布。通过递归计算，估计电路的延迟分布。

9. 发明授权

US07870533B2 Delay analysis apparatus, delay analysis method and computer product 有权
标题翻译：延迟分析装置，延迟分析方法和计算机产品
公开(公告)号：US07870533B2
公开(公告)日：2011-01-11
申请号：US12073039
申请日：2008-02-28
申请人： Katsumi Homma , Izumi Nitta , Toshiyuki Shibuya
发明人： Katsumi Homma , Izumi Nitta , Toshiyuki Shibuya
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/5036 , G06F2217/10
摘要： Within-die delay distributions and die-to-die delay distributions of two arbitrary paths in an analysis target circuit are extracted from a delay distribution library, and an effect index indicative of a relative error of an overall path delay distribution of one path and an overall path delay distribution when the two paths are integrated as one path is calculated based on the within-die delay distributions and the die-to-die delay distributions of the two paths. When the effect index is determined to be equal to or above a threshold, the overall path delay distribution of the two paths integrated as one path is calculated. Hence, a path that affects an analysis result alone is selected to execute a statistical Max operation, thereby increasing a speed of delay analysis processing.
摘要翻译：在延迟分布库中提取分析目标电路中的两个任意路径的管芯内延迟分布和管芯到管芯延迟分布，以及表示一条路径和一条路径的总路径延迟分布的相对误差的效应指标基于芯片间延迟分布和两条路径的管芯到管芯延迟分布，计算两条路径被集成为一条路径时的总路径延迟分布。当效果指标确定为等于或大于阈值时，计算集成为一条路径的两条路径的总体路径延迟分布。因此，选择仅影响分析结果的路径来执行统计最大运算，从而提高延迟分析处理的速度。

10. 发明授权

US07934182B2 Method and apparatus for supporting delay analysis, and computer product 有权
标题翻译：支持延迟分析的方法和装置，以及计算机产品
公开(公告)号：US07934182B2
公开(公告)日：2011-04-26
申请号：US12193431
申请日：2008-08-18
申请人： Izumi Nitta , Katsumi Homma , Toshiyuki Shibuya
发明人： Izumi Nitta , Katsumi Homma , Toshiyuki Shibuya
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A delay distribution of a partial path that passes through a node to which a plurality of signals is input and for which an estimation in a statistical MAX is predicted to be large, that is present on a critical path having large influence on a circuit delay, and that has high possibility of improving the circuit delay, among nodes in a circuit graph is calculated by the Monte Carlo simulation instead of the block based simulation, thereby increasing speed and accuracy of delay analysis.
摘要翻译：通过输入多个信号的节点并且预测统计MAX中的估计为大的部分路径的延迟分布，其存在于对电路延迟有很大影响的关键路径上，并且具有改善电路延迟的可能性很高，通过蒙特卡罗模拟而不是基于块的仿真来计算电路图中的节点，从而提高延迟分析的速度和精度。

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