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1. 发明授权

US07516432B2 Circuit delay analyzing method, circuit delay analyzing apparatus, and computer product 有权
标题翻译：电路延迟分析方法，电路延迟分析装置和计算机产品
公开(公告)号：US07516432B2
公开(公告)日：2009-04-07
申请号：US11521138
申请日：2006-09-14
申请人： Katsumi Homma , Toshiyuki Shibuya , Hidetoshi Matsuoka , Izumi Nitta
发明人： Katsumi Homma , Toshiyuki Shibuya , Hidetoshi Matsuoka , Izumi Nitta
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A delay analyzing apparatus receives a result of timing analysis of a target circuit, and detects, from paths in the target circuit, critical paths based on the result of the timing analysis with a detecting unit. A first calculating unit calculates an average delay distribution of the paths other than the critical paths based on an average delay value of each of the critical paths. A second calculating unit calculates a probability density distribution of the critical paths, and a third calculating unit calculates a probability density distribution of all of the paths based on the average delay distribution. A fourth calculating unit calculates difference between a statistical delay value of the critical paths and a statistical delay value of all of the paths based on the probability density distribution of the critical paths and the probability density distribution of all of the paths.
摘要翻译：延迟分析装置接收目标电路的定时分析结果，并根据检测单元的定时分析结果从目标电路中的路径检测关键路径。第一计算单元基于每个关键路径的平均延迟值来计算除了关键路径之外的路径的平均延迟分布。第二计算单元计算关键路径的概率密度分布，第三计算单元基于平均延迟分布来计算所有路径的概率密度分布。第四计算单元基于关键路径的概率密度分布和所有路径的概率密度分布来计算关键路径的统计延迟值与所有路径的统计延迟值之间的差异。

2. 发明授权

US07320118B2 Delay analysis device, delay analysis method, and computer product 有权
标题翻译：延迟分析装置，延迟分析方法和计算机产品
公开(公告)号：US07320118B2
公开(公告)日：2008-01-15
申请号：US11315173
申请日：2005-12-23
申请人： Katsumi Homma , Toshiyuki Shibuya , Hidetoshi Matsuoka , Izumi Nitta
发明人： Katsumi Homma , Toshiyuki Shibuya , Hidetoshi Matsuoka , Izumi Nitta
IPC分类号： G06F17/50
CPC分类号： G06F17/504 , G06F2217/84
摘要： A delay analysis device includes a receiving unit that receives a result of a timing analysis of a target circuit to be analyzed, a detecting unit that detects critical paths having delays within a predetermined range, a statistical-delay computing unit that computes a statistical delay of the target circuit based on a cumulative probability distribution of the delays of the critical paths, and a probability-density-distribution computing unit that computes a probability density distribution of delay of a critical path that has the greatest delay in the result. The detecting unit detects x number of critical paths having cumulative delays within computed probability density distribution.
摘要翻译：延迟分析装置包括：接收单元，其接收要分析的目标电路的定时分析的结果;检测单元，其检测具有在预定范围内的延迟的关键路径;计算统计延迟的统计延迟计算单元，基于关键路径的延迟的累积概率分布的目标电路，以及计算结果中具有最大延迟的关键路径的延迟的概率密度分布的概率密度分布计算单元。检测单元检测在计算的概率密度分布内具有累积延迟的x个关键路径。

3. 发明申请

US20080148205A1 Circuit delay analyzer, circuit delay analyzing method, and computer product 有权
标题翻译：电路延迟分析仪，电路延迟分析方法和电脑产品
公开(公告)号：US20080148205A1
公开(公告)日：2008-06-19
申请号：US11902489
申请日：2007-09-21
申请人： Katsumi Homma , Hidetoshi Matsuoka , Izumi Nitta , Toshiyuki Shibuya
发明人： Katsumi Homma , Hidetoshi Matsuoka , Izumi Nitta , Toshiyuki Shibuya
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F2217/10 , G06F2217/84
摘要： Delay analysis performed on a circuit having multiple parallel partial circuits (paths) involves recursively integrating two paths of the circuit using an all-element delay distribution that indicates delay based on performance of all circuit elements in a path and a correlation delay distribution that indicates delay based on correlation between circuit elements in the path. An all-element delay distribution is calculated for the integrated path using the all-element delay distributions of the two paths to be integrated. The all-element delay distributions and the correlation delay distributions of two paths to be integrated are used to calculate a total delay distribution for the integrated path. The total delay distribution is used with the all-element delay distribution for the integrated path to calculate a correlation delay distribution for the integrated path. Through recursive calculation, a delay distribution of the circuit is estimated.
摘要翻译：对具有多个并行部分电路（路径）的电路进行延迟分析涉及使用基于路径中的所有电路元件的性能的指示延迟的全元延迟分布递归地积分电路的两个路径，以及指示延迟的相关延迟分布基于路径中的电路元件之间的相关性。使用要集成的两个路径的全元素延迟分布，针对集成路径计算全元素延迟分布。要整合的两个路径的全元素延迟分布和相关延迟分布用于计算集成路径的总延迟分布。总延迟分布与集成路径的全元素延迟分布一起使用，以计算集成路径的相关延迟分布。通过递归计算，估计电路的延迟分布。

4. 发明授权

US07681161B2 Circuit delay analyzer, circuit delay analyzing method, and computer product 有权
标题翻译：电路延迟分析仪，电路延迟分析方法和电脑产品
公开(公告)号：US07681161B2
公开(公告)日：2010-03-16
申请号：US11902489
申请日：2007-09-21
申请人： Katsumi Homma , Hidetoshi Matsuoka , Izumi Nitta , Toshiyuki Shibuya
发明人： Katsumi Homma , Hidetoshi Matsuoka , Izumi Nitta , Toshiyuki Shibuya
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F2217/10 , G06F2217/84
摘要： Delay analysis performed on a circuit having multiple parallel partial circuits (paths) involves recursively integrating two paths of the circuit using an all-element delay distribution that indicates delay based on performance of all circuit elements in a path and a correlation delay distribution that indicates delay based on correlation between circuit elements in the path. An all-element delay distribution is calculated for the integrated path using the all-element delay distributions of the two paths to be integrated. The all-element delay distributions and the correlation delay distributions of two paths to be integrated are used to calculate a total delay distribution for the integrated path. The total delay distribution is used with the all-element delay distribution for the integrated path to calculate a correlation delay distribution for the integrated path. Through recursive calculation, a delay distribution of the circuit is estimated.
摘要翻译：对具有多个并行部分电路（路径）的电路进行延迟分析涉及使用基于路径中的所有电路元件的性能的指示延迟的全元延迟分布递归地积分电路的两个路径，以及指示延迟的相关延迟分布基于路径中的电路元件之间的相关性。使用要集成的两个路径的全元素延迟分布，针对集成路径计算全元素延迟分布。要整合的两个路径的全元素延迟分布和相关延迟分布用于计算集成路径的总延迟分布。总延迟分布与集成路径的全元素延迟分布一起使用，以计算集成路径的相关延迟分布。通过递归计算，估计电路的延迟分布。

5. 发明授权

US07653889B2 Method and apparatus for repeat execution of delay analysis in circuit design 失效
标题翻译：在电路设计中重复执行延迟分析的方法和装置
公开(公告)号：US07653889B2
公开(公告)日：2010-01-26
申请号：US11524342
申请日：2006-09-20
申请人： Izumi Nitta , Toshiyuki Shibuya , Katsumi Homma , Hidetoshi Matsuoka
发明人： Izumi Nitta , Toshiyuki Shibuya , Katsumi Homma , Hidetoshi Matsuoka
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5031
摘要： An apparatus includes: a detecting unit that detects a target path from among a plurality of paths in a target circuit based on a result of a delay analysis of the target circuit, wherein the result of the delay analysis includes delay data of a first circuit component of the target path; an extracting unit that extracts delay data of a second circuit component having an identical type to that of the first circuit component; and a generating unit that generates a directive for replacing the first circuit component with the second circuit component.
摘要翻译：一种装置包括：检测单元，基于目标电路的延迟分析结果，从目标电路中的多个路径中检测目标路径，其中延迟分析的结果包括第一电路部件的延迟数据的目标路径; 提取单元，其提取具有与所述第一电路部件相同类型的第二电路部件的延迟数据; 以及生成单元，其生成用于用第二电路部件替换第一电路部件的指令。

6. 发明申请

US20070204248A1 Delay analyzing method, delay analyzing apparatus, and computer product 有权
标题翻译：延迟分析方法，延迟分析仪器和计算机产品
公开(公告)号：US20070204248A1
公开(公告)日：2007-08-30
申请号：US11521138
申请日：2006-09-14
申请人： Katsumi Homma , Toshiyuki Shibuya , Hidetoshi Matsuoka , Izumi Nitta
发明人： Katsumi Homma , Toshiyuki Shibuya , Hidetoshi Matsuoka , Izumi Nitta
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A delay analyzing apparatus receives a result of timing analysis of a target circuit, and detects, from paths in the target circuit, critical paths based on the result of the timing analysis with a detecting unit. A first calculating unit calculates an average delay distribution of the paths other than the critical paths based on an average delay value of each of the critical paths. A second calculating unit calculates a probability density distribution of the critical paths, and a third calculating unit calculates a probability density distribution of all of the paths based on the average delay distribution. A fourth calculating unit calculates difference between a statistical delay value of the critical paths and a statistical delay value of all of the paths based on the probability density distribution of the critical paths and the probability density distribution of all of the paths.
摘要翻译：延迟分析装置接收目标电路的定时分析结果，并根据检测单元的定时分析结果从目标电路中的路径检测关键路径。第一计算单元基于每个关键路径的平均延迟值来计算除了关键路径之外的路径的平均延迟分布。第二计算单元计算关键路径的概率密度分布，第三计算单元基于平均延迟分布来计算所有路径的概率密度分布。第四计算单元基于关键路径的概率密度分布和所有路径的概率密度分布来计算关键路径的统计延迟值与所有路径的统计延迟值之间的差异。

7. 发明申请

US20070074138A1 Delay analysis device, delay analysis method, and computer product 有权
标题翻译：延迟分析装置，延迟分析方法和计算机产品
公开(公告)号：US20070074138A1
公开(公告)日：2007-03-29
申请号：US11315173
申请日：2005-12-23
申请人： Katsumi Homma , Toshiyuki Shibuya , Hidetoshi Matsuoka , Izumi Nitta
发明人： Katsumi Homma , Toshiyuki Shibuya , Hidetoshi Matsuoka , Izumi Nitta
IPC分类号： G06F17/50
CPC分类号： G06F17/504 , G06F2217/84
摘要： A delay analysis device includes a receiving unit that receives a result of a timing analysis of a target circuit to be analyzed, a detecting unit that detects critical paths having delays within a predetermined range, a statistical-delay computing unit that computes a statistical delay of the target circuit based on a cumulative probability distribution of the delays of the critical paths, and a probability-density-distribution computing unit that computes a probability density distribution of delay of a critical path that has the greatest delay in the result. The detecting unit detects x number of critical paths having cumulative delays within computed probability density distribution.
摘要翻译：延迟分析装置包括：接收单元，其接收要分析的目标电路的定时分析的结果;检测单元，其检测具有在预定范围内的延迟的关键路径;计算统计延迟的统计延迟计算单元，基于关键路径的延迟的累积概率分布的目标电路，以及计算结果中具有最大延迟的关键路径的延迟的概率密度分布的概率密度分布计算单元。检测单元检测在计算的概率密度分布内具有累积延迟的x个关键路径。

8. 发明申请

US20070226669A1 Method and apparatus for repeat execution of delay analysis in circuit design 失效
标题翻译：在电路设计中重复执行延迟分析的方法和装置
公开(公告)号：US20070226669A1
公开(公告)日：2007-09-27
申请号：US11524342
申请日：2006-09-20
申请人： Izumi Nitta , Toshiyuki Shibuya , Katsumi Homma , Hidetoshi Matsuoka
发明人： Izumi Nitta , Toshiyuki Shibuya , Katsumi Homma , Hidetoshi Matsuoka
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： An apparatus includes: a detecting unit that detects a target path from among a plurality of paths in a target circuit based on a result of a delay analysis of the target circuit, wherein the result of the delay analysis includes delay data of a first circuit component of the target path; an extracting unit that extracts delay data of a second circuit component having an identical type to that of the first circuit component; and a generating unit that generates a directive for replacing the first circuit component with the second circuit component.
摘要翻译：一种装置包括：检测单元，基于目标电路的延迟分析结果，从目标电路中的多个路径中检测目标路径，其中延迟分析的结果包括第一电路部件的延迟数据的目标路径; 提取单元，其提取具有与所述第一电路部件相同类型的第二电路部件的延迟数据; 以及生成单元，其生成用于用第二电路部件替换第一电路部件的指令。

9. 发明授权

US06415427B2 Method and apparatus for global routing, and storage medium having global routing program stored therein 有权
标题翻译：用于全局路由的方法和装置，以及存储有全局路由程序的存储介质
公开(公告)号：US06415427B2
公开(公告)日：2002-07-02
申请号：US09800490
申请日：2001-03-08
申请人： Izumi Nitta , Hidetoshi Matsuoka
发明人： Izumi Nitta , Hidetoshi Matsuoka
IPC分类号： G06F1750
CPC分类号： G06F17/5077
摘要： A global routing method acquiring global routing between net terminals of cells placed on a VLSI chip. First, a Steiner tree is generated without any of constraints such as layers, prohibition and a wiring capacity as an initial solution. Then, partial correction of the Steiner tree is repeated so as not to increase a line length as far as possible in consideration of constraints such as a prohibiting region, a wiring capacity and layers based on the initial solution of the Steiner tree to obtain the global routing. The Steiner tree is corrected generating a path collection obtained by dividing the Steiner tree into a plurality of paths each having at least a Steiner point, as a value, being an intersection of 3 or more branches.
摘要翻译：全局路由方法获取放置在VLSI芯片上的单元的网络终端之间的全局路由。首先，生成Steiner树，没有任何限制，如层，禁止和布线容量作为初始解决方案。然后，重复Steiner树的部分校正，以便考虑到诸如禁止区域，布线容量和基于Steiner树的初始解决方案的层的约束来尽可能不增加线路长度以获得全局路由。对斯坦纳树进行校正，生成通过将斯坦纳树划分为多个路径而获得的路径集合，每条路径至少具有斯坦纳点，作为3个或更多个分支的交叉点的值。

10. 发明授权

US08732643B2 Support method, design support apparatus, computer product using combination pattern is prepared in advance 有权
标题翻译：设计支持方法，设计支持设备，计算机产品使用组合模式提前准备
公开(公告)号：US08732643B2
公开(公告)日：2014-05-20
申请号：US12817619
申请日：2010-06-17
申请人： Hidetoshi Matsuoka
发明人： Hidetoshi Matsuoka
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A design support apparatus includes a detecting unit, a determining unit, and an inserting unit. The detecting unit detects a via that connects wirings in a circuit to be designed that is expressed by layout information. The determining unit determines the connection position of a dummy via that does not connect wirings, to be on at least one of wirings connected to the via detected by the detecting unit. The inserting unit inserts the dummy via at the connection position determined by the determining unit.
摘要翻译：设计支持装置包括检测单元，确定单元和插入单元。检测单元检测连接由布局信息表示的要设计的电路中的布线的通孔。确定单元确定不连接布线的虚拟通孔的连接位置，以连接到由检测单元检测到的通孔中的至少一个布线。插入单元将伪通孔插入由确定单元确定的连接位置。

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