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1. 发明申请

US20130332918A1 DEVICE AND METHOD FOR TIME NOTIFICATION FOR UPDATING SOFTWARE 有权
标题翻译：用于更新软件的时间通知的设备和方法
公开(公告)号：US20130332918A1
公开(公告)日：2013-12-12
申请号：US13493692
申请日：2012-06-11
申请人： Katsumi Aoyagi , Miki Suzuki , Yasuyuki Hirao , Hidefumi Kaneko , Takeshi Kanemoto , Tomohiro Ichikawa
发明人： Katsumi Aoyagi , Miki Suzuki , Yasuyuki Hirao , Hidefumi Kaneko , Takeshi Kanemoto , Tomohiro Ichikawa
IPC分类号： G06F9/44
CPC分类号： G06F8/65
摘要： A terminal device may include: a communication interface to receive, from a server via a network, a file for updating software in a memory device coupled with the terminal device, and a software update table that includes data regarding one or more performance values and one or more time values indicative of one or more lengths of time taken to update the software using the file; a processor to obtain data regarding a performance value of the memory device, select, from the software update table, one of the one or more performance values based on the performance value of the memory device, and obtain, from the software update table, a time value associated with the selected performance value; and an output device to provide an output corresponding to the obtained time value. Each performance value is associated with one of the one or more time values, respectively.
摘要翻译：终端设备可以包括：通信接口，用于经由网络从服务器接收用于更新与终端设备耦合的存储设备中的软件的文件，以及软件更新表，其包括关于一个或多个性能值的数据和一个或更多的时间值指示使用该文件更新软件所需的一个或多个时间长度; 获取关于存储器件的性能值的数据的处理器，从软件更新表中选择基于存储器件的性能值的一个或多个性能值之一，并从软件更新表中获得与所选性能值相关联的时间值; 以及输出装置，用于提供对应于所获得的时间值的输出。每个性能值分别与一个或多个时间值之一相关联。

2. 发明授权

US08819662B2 Device and method for time notification for updating software 有权
标题翻译：用于更新软件的时间通知的设备和方法
公开(公告)号：US08819662B2
公开(公告)日：2014-08-26
申请号：US13493692
申请日：2012-06-11
申请人： Katsumi Aoyagi , Miki Suzuki , Yasuyuki Hirao , Hidefumi Kaneko , Takeshi Kanemoto , Tomohiro Ichikawa
发明人： Katsumi Aoyagi , Miki Suzuki , Yasuyuki Hirao , Hidefumi Kaneko , Takeshi Kanemoto , Tomohiro Ichikawa
IPC分类号： G06F9/44
CPC分类号： G06F8/65
摘要： A terminal device may include: a communication interface to receive, from a server via a network, a file for updating software in a memory device coupled with the terminal device, and a software update table that includes data regarding one or more performance values and one or more time values indicative of one or more lengths of time taken to update the software using the file; a processor to obtain data regarding a performance value of the memory device, select, from the software update table, one of the one or more performance values based on the performance value of the memory device, and obtain, from the software update table, a time value associated with the selected performance value; and an output device to provide an output corresponding to the obtained time value. Each performance value is associated with one of the one or more time values, respectively.
摘要翻译：终端设备可以包括：通信接口，用于经由网络从服务器接收用于更新与终端设备耦合的存储设备中的软件的文件，以及软件更新表，其包括关于一个或多个性能值的数据和一个或更多的时间值指示使用该文件更新软件所需的一个或多个时间长度; 获取关于存储器件的性能值的数据的处理器，从软件更新表中选择基于存储器件的性能值的一个或多个性能值之一，并从软件更新表中获得与所选性能值相关联的时间值; 以及输出装置，用于提供对应于所获得的时间值的输出。每个性能值分别与一个或多个时间值之一相关联。

3. 发明申请

US20130009247A1 Method for Manufacturing Semiconductor Device 有权
标题翻译：半导体器件制造方法
公开(公告)号：US20130009247A1
公开(公告)日：2013-01-10
申请号：US13547393
申请日：2012-07-12
申请人： Kazuya Hanaoka , Miki Suzuki
发明人： Kazuya Hanaoka , Miki Suzuki
IPC分类号： H01L27/12
CPC分类号： H01L21/76823 , H01L21/76825 , H01L25/0657 , H01L27/124 , H01L2225/06513 , H01L2225/06541 , H01L2924/0002 , H01L2924/00
摘要： It is an object to form a conductive region in an insulating film without forming contact holes in the insulating film. A method is provided, in which an insulating film is formed over a first electrode over a substrate, a first region having many defects is formed at a first depth in the insulating film by adding first ions into the insulating film at a first accelerating voltage; a second region having many defects is formed at a second depth which is different from the first depth in the insulating film by adding second ions into the insulating film at a second accelerating voltage, a conductive material containing a metal element is formed over the first and second regions; and a conductive region which electrically connects the first electrode and the conductive material is formed in the insulating film by diffusing the metal element into the first and second regions.
摘要翻译：其目的是在绝缘膜中形成导电区域，而不在绝缘膜中形成接触孔。提供了一种方法，其中在衬底上方的第一电极上形成绝缘膜，通过以第一加速电压将绝缘膜中加入第一离子，在绝缘膜的第一深度处形成具有许多缺陷的第一区域; 通过在第二加速电压下将第二离子加入到绝缘膜中，在第二深度上形成具有许多缺陷的第二区域，该第二深度与绝缘膜中的第一深度不同，在第一深度上形成包含金属元素的导电材料，第二区; 并且通过将金属元素扩散到第一和第二区域中，在绝缘膜中形成电连接第一电极和导电材料的导电区域。

4. 发明申请

US20140221363A1 COMPOSITION AND METHOD FOR CONTROLLING HARMFUL ARTHROPODS 审中-公开
标题翻译：用于控制有害牙垢的组合物和方法
公开(公告)号：US20140221363A1
公开(公告)日：2014-08-07
申请号：US14233000
申请日：2012-07-20
申请人： Atsushi Iwata , Chie Shimizu , Miki Suzuki
发明人： Atsushi Iwata , Chie Shimizu , Miki Suzuki
IPC分类号： A01N37/30 , A01N43/08 , A01N43/88 , A01N43/40 , A01N43/50 , A01N43/78
CPC分类号： A01N43/40 , A01N25/00 , A01N37/30 , A01N43/08 , A01N43/50 , A01N43/78 , A01N43/88 , A01N51/00
摘要： The present invention provides a composition for controlling harmful arthropods having an excellent control efficacy on harmful arthropods. A composition for controlling harmful arthropods comprising an amide compound represented by a formula (I); wherein each of symbols are the same as defined in the Description; or salts thereof, and at least one kind of neonicotinoid compounds selected from the group (A) consisting of imidacloprid, clothianidin, thiamethoxiam, dinotefuran, acetamiprid, thiacloprid and nitenpyram, shows an excellent controlling efficacy on harmful arthropods.
摘要翻译：本发明提供了一种用于控制对有害节肢动物具有优异控制功效的有害节肢动物的组合物。一种用于控制有害节肢动物的组合物，其包含由式（I）表示的酰胺化合物; 其中每个符号与描述中定义的相同; 或其盐，以及选自吡虫啉，噻虫胺，噻虫胺，呋虫胺，啶虫脒，噻虫啉，烯尼龙等组合的至少一种新烟碱类化合物，对有害节肢动物显示出优异的防治效果。

5. 发明申请

US20140179692A1 COMPOSITION AND METHOD FOR CONTROLLING HARMFUL ARTHROPODS 审中-公开
公开(公告)号：US20140179692A1
公开(公告)日：2014-06-26
申请号：US14233264
申请日：2012-07-20
申请人： Atsushi Iwata , Chie Shimizu , Miki Suzuki
发明人： Atsushi Iwata , Chie Shimizu , Miki Suzuki
IPC分类号： A01N37/30 , A01N43/88 , A01N43/38 , A01N43/08 , A01N43/40 , A01N43/50 , A01N43/78
CPC分类号： A01N37/30 , A01N43/08 , A01N43/38 , A01N43/40 , A01N43/50 , A01N43/78 , A01N43/88 , A01N47/40 , A01N51/00
摘要： The present invention provides a composition for controlling harmful arthropods having an excellent control efficacy on harmful arthropods. A composition for controlling harmful arthropods comprising an amide compound represented by a formula (I); wherein each of symbols are the same as defined in the Description; or salts thereof and at least one kind of neonicotinoid compounds selected from the group (A) consisting of imidacloprid, clothianidin, thiamethoxiam, dinotefuran, acetamiprid, thiacloprid and nitenpyram, shows an excellent controlling efficacy on harmful arthropods.

6. 发明授权

US08530973B2 Method for manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08530973B2
公开(公告)日：2013-09-10
申请号：US13547393
申请日：2012-07-12
申请人： Kazuya Hanaoka , Miki Suzuki
发明人： Kazuya Hanaoka , Miki Suzuki
IPC分类号： H01L29/786
CPC分类号： H01L21/76823 , H01L21/76825 , H01L25/0657 , H01L27/124 , H01L2225/06513 , H01L2225/06541 , H01L2924/0002 , H01L2924/00
摘要： It is an object to form a conductive region in an insulating film without forming contact holes in the insulating film. A method is provided, in which an insulating film is formed over a first electrode over a substrate, a first region having many defects is formed at a first depth in the insulating film by adding first ions into the insulating film at a first accelerating voltage; a second region having many defects is formed at a second depth which is different from the first depth in the insulating film by adding second ions into the insulating film at a second accelerating voltage, a conductive material containing a metal element is formed over the first and second regions; and a conductive region which electrically connects the first electrode and the conductive material is formed in the insulating film by diffusing the metal element into the first and second regions.
摘要翻译：其目的是在绝缘膜中形成导电区域，而不在绝缘膜中形成接触孔。提供了一种方法，其中在衬底上方的第一电极上形成绝缘膜，通过以第一加速电压将绝缘膜中加入第一离子，在绝缘膜的第一深度处形成具有许多缺陷的第一区域; 通过在第二加速电压下将第二离子加入到绝缘膜中，在第二深度上形成具有许多缺陷的第二区域，该第二深度与绝缘膜中的第一深度不同，在第一深度上形成包含金属元素的导电材料，第二区; 并且通过将金属元素扩散到第一和第二区域中，在绝缘膜中形成电连接第一电极和导电材料的导电区域。

7. 发明授权

US07554305B2 Linear regulator with discharging gate driver 有权
标题翻译：带放电栅极驱动器的线性稳压器
公开(公告)号：US07554305B2
公开(公告)日：2009-06-30
申请号：US10985905
申请日：2004-11-12
申请人： Hideo Nunokawa , Tatsuo Kato , Miki Suzuki , Tomonari Morishita
发明人： Hideo Nunokawa , Tatsuo Kato , Miki Suzuki , Tomonari Morishita
IPC分类号： G05F1/56
CPC分类号： G05F1/575
摘要： Even when, for example, electric charge is injected into the output transistor due to external factor such as a noise from the outside, to prevent the step-down voltage from rising, the step-down circuit is comprised of an N channel type output transistor which controls the voltage at the control end, a booster, which is connected to the control end of the output transistor and raises the voltage at the control end and a discharge circuit, which discharges the electric charge at the control end of the output transistor so that the power supply voltage inputted from the input end is stepped down to a desired step-down voltage and outputted from the output end.
摘要翻译：即使例如，由于诸如来自外部的噪声等外部因素将电荷注入到输出晶体管中，为了防止降压电压上升，降压电路由N沟道型输出晶体管其控制控制端的电压，升压器，其连接到输出晶体管的控制端并提高控制端的电压，以及放电电路，其在输出晶体管的控制端放电电从输入端输入的电源电压被降低到期望的降压电压并从输出端输出。

8. 发明授权

US08766361B2 Semiconductor device and electronic device 有权
标题翻译：半导体器件和电子器件
公开(公告)号：US08766361B2
公开(公告)日：2014-07-01
申请号：US13315322
申请日：2011-12-09
申请人： Junichi Koezuka , Satoshi Shinohara , Miki Suzuki , Hideto Ohnuma
发明人： Junichi Koezuka , Satoshi Shinohara , Miki Suzuki , Hideto Ohnuma
IPC分类号： H01L27/12
CPC分类号： H01L29/66772 , H01L27/1288 , H01L29/66492 , H01L29/78624
摘要： A semiconductor device is provided, which includes a single crystal semiconductor layer formed over an insulating surface and having a source region, a drain region, and a channel formation region, a gate insulating film covering the single crystal semiconductor layer and a gate electrode overlapping with the channel formation region with the gate insulating film interposed therebetween. In the semiconductor device, at least the drain region of the source and drain regions includes a first impurity region adjacent to the channel formation region and a second impurity region adjacent to the first impurity region. A maximum of an impurity concentration distribution in the first impurity region in a depth direction is closer to the insulating surface than a maximum of an impurity concentration distribution in the second impurity region in a depth direction.
摘要翻译：提供了一种半导体器件，其包括形成在绝缘表面上并具有源极区，漏极区和沟道形成区的单晶半导体层，覆盖单晶半导体层的栅极绝缘膜和与沟道形成区域之间插入栅极绝缘膜。在半导体器件中，源极和漏极区域的至少漏极区域包括与沟道形成区域相邻的第一杂质区域和与第一杂质区域相邻的第二杂质区域。与深度方向上的第二杂质区域的杂质浓度分布的最大值相比，深度方向上的第一杂质区域的杂质浓度分布的最大值比绝缘面更接近。

9. 发明申请

US20060012354A1 Step-down circuit 有权
标题翻译：降压电路
公开(公告)号：US20060012354A1
公开(公告)日：2006-01-19
申请号：US10985905
申请日：2004-11-12
申请人： Hideo Nunokawa , Tatsuo Kato , Miki Suzuki , Tomonari Morishita
发明人： Hideo Nunokawa , Tatsuo Kato , Miki Suzuki , Tomonari Morishita
IPC分类号： G05F1/56
CPC分类号： G05F1/575
摘要： Even when, for example, electric charge is injected into the output transistor due to external factor such as a noise from the outside, to prevent the step-down voltage from rising, the step-down circuit is comprised of an N channel type output transistor which controls the voltage at the control end, a booster, which is connected to the control end of the output transistor and raises the voltage at the control end and a discharge circuit, which discharges the electric charge at the control end of the output transistor so that the power supply voltage inputted from the input end is stepped down to a desired step-down voltage and outputted from the output end.
摘要翻译：即使例如，由于诸如来自外部的噪声等外部因素将电荷注入到输出晶体管中，为了防止降压电压上升，降压电路由N沟道型输出晶体管其控制控制端的电压，升压器，其连接到输出晶体管的控制端并提高控制端的电压，以及放电电路，其在输出晶体管的控制端放电电从输入端输入的电源电压被降低到期望的降压电压并从输出端输出。

10. 外观设计

USD468198S1 Front surface of package 失效
公开(公告)号：USD468198S1
公开(公告)日：2003-01-07
申请号：US29140707
申请日：2001-04-23
申请人： Manami Nakazawa , Miki Suzuki , Megumi Nakamura
设计人： Manami Nakazawa , Miki Suzuki , Megumi Nakamura

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