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1. 发明授权

US07978750B2 Microcontroller 有权
标题翻译：微控制器
公开(公告)号：US07978750B2
公开(公告)日：2011-07-12
申请号：US11168448
申请日：2005-06-29
申请人： Hideo Nunokawa , Miki Suzuki , Hiroyuki Abe , Shinichi Okamoto , Shunichi Ko , Hiroshi Haibara , Nobuhiko Akasaka
发明人： Hideo Nunokawa , Miki Suzuki , Hiroyuki Abe , Shinichi Okamoto , Shunichi Ko , Hiroshi Haibara , Nobuhiko Akasaka
IPC分类号： H04B1/00
CPC分类号： H04B15/04 , H04B1/202
摘要： A microcontroller is disposed on a receiving part of a wireless system in order to process a demodulation signal generated by a receiver circuit, and includes a memory and a CPU. The memory stores a control program of the microcontroller. The control program thereof includes a dual loop routine for an operation in reception standby mode. The dual loop routine has a first loop and a second loop included in the first loop. The CPU has an instruction set consisting of a plurality of instructions, and executes the instructions according to the program stored in the memory. The CPU executes an instruction irrelevant to an operation when the microcontroller is in reception mode during the second loop a number of times. The number of times is at least such that noise caused by the repetition of the second loop is lowered below a desired level.
摘要翻译：微控制器设置在无线系统的接收部分上，以便处理由接收机电路产生的解调信号，并且包括存储器和CPU。存储器存储微控制器的控制程序。其控制程序包括用于接收待机模式下的操作的双循环程序。双循环程序具有包含在第一循环中的第一循环和第二循环。 CPU具有由多个指令组成的指令集，并且根据存储在存储器中的程序执行指令。 CPU执行与微控制器在第二次循环期间处于接收模式时的操作无关的指令。次数至少使得由第二回路的重复引起的噪声降低到期望水平以下。

2. 发明授权

US07915911B2 Input circuit and semiconductor integrated circuit 有权
标题翻译：输入电路和半导体集成电路
公开(公告)号：US07915911B2
公开(公告)日：2011-03-29
申请号：US12724942
申请日：2010-03-16
申请人： Hideo Nunokawa
发明人： Hideo Nunokawa
IPC分类号： H03K19/0175 , H03K5/08 , H02H3/20
CPC分类号： H03K19/003 , H01L27/0255
摘要： An input circuit for receiving an input signal supplied to an input terminal includes a capacitor having one end connected to the input terminal and a capacitor driving circuit for converting the input signal into a signal having positive logic that is the same as logic of the input signal and supplying the converted signal to the other end of the capacitor so as to drive the capacitor.
摘要翻译：用于接收提供给输入端的输入信号的输入电路包括具有连接到输入端的一端的电容器和用于将输入信号转换成具有与输入信号的逻辑相同的正逻辑的信号的电容器驱动电路并将转换的信号提供给电容器的另一端以驱动电容器。

3. 发明申请

US20060223452A1 Microcontroller 有权
标题翻译：微控制器
公开(公告)号：US20060223452A1
公开(公告)日：2006-10-05
申请号：US11168448
申请日：2005-06-29
申请人： Hideo Nunokawa , Miki Suzuki , Hiroyuki Abe , Shinichi Okamoto , Shunichi Ko , Hiroshi Haibara , Nobuhiko Akasaka
发明人： Hideo Nunokawa , Miki Suzuki , Hiroyuki Abe , Shinichi Okamoto , Shunichi Ko , Hiroshi Haibara , Nobuhiko Akasaka
IPC分类号： H04B1/38
CPC分类号： H04B15/04 , H04B1/202
摘要： A microcontroller is disposed on a receiving part of a wireless system in order to process a demodulation signal generated by a receiver circuit, and includes a memory and a CPU. The memory stores a control program of the microcontroller. The control program thereof includes a dual loop routine for an operation in reception standby mode. The dual loop routine has a first loop and a second loop included in the first loop. The CPU has an instruction set consisting of a plurality of instructions, and executes the instructions according to the program stored in the memory. The CPU executes an instruction irrelevant to an operation when the microcontroller is in reception mode during the second loop a number of times. The number of times is at least such that noise caused by the repetition of the second loop is lowered below a desired level.
摘要翻译：微控制器设置在无线系统的接收部分上，以便处理由接收机电路产生的解调信号，并且包括存储器和CPU。存储器存储微控制器的控制程序。其控制程序包括用于接收待机模式下的操作的双循环程序。双循环程序具有包含在第一循环中的第一循环和第二循环。 CPU具有由多个指令组成的指令集，并且根据存储在存储器中的程序执行指令。 CPU执行与微控制器在第二次循环期间处于接收模式时的操作无关的指令。次数至少使得由第二回路的重复引起的噪声降低到期望水平以下。

4. 发明授权

US06842063B2 Analog switch circuit 有权
标题翻译：模拟开关电路
公开(公告)号：US06842063B2
公开(公告)日：2005-01-11
申请号：US10625738
申请日：2003-07-24
申请人： Suguru Tachibana , Tatsuo Kato , Hideo Nunokawa
发明人： Suguru Tachibana , Tatsuo Kato , Hideo Nunokawa
IPC分类号： H03K17/08 , H03K17/06 , H03K17/687 , H03K17/62
CPC分类号： H03K17/6872 , H03K17/063 , H03K17/6874
摘要： An analog switch circuit with superior breakdown voltage characteristics that can operate at a high speed at a low power supply voltage. The analog switch circuit includes a comparator circuit for inputting and comparing an analog input signal input to an analog switch section and a reference signal. If the input potential of the analog input signal is lower than the reference potential of the reference signal, a voltage boost circuit sets a potential of a gate of an n MOS transistor included in the analog switch section to a potential of positive power supply voltage. If the input potential of the analog input signal is higher than the reference potential of the reference signal, the voltage boost circuit boosts the potential of the gate to a potential higher than the potential of power supply voltage.
摘要翻译：具有优异的击穿电压特性的模拟开关电路，可在低电源电压下高速运行。模拟开关电路包括用于输入和比较输入到模拟开关部分的模拟输入信号和参考信号的比较器电路。如果模拟输入信号的输入电位低于参考信号的参考电位，则升压电路将模拟开关部分中包括的n个MOS晶体管的栅极的电位设置为正电源电压的电位。如果模拟输入信号的输入电位高于参考信号的参考电位，则升压电路将栅极的电位升高到高于电源电压的电位。

5. 发明授权

US06714151B2 A/D converter 有权
标题翻译： A / D转换器
公开(公告)号：US06714151B2
公开(公告)日：2004-03-30
申请号：US10465549
申请日：2003-06-20
申请人： Suguru Tachibana , Tatsuo Kato , Hideo Nunokawa
发明人： Suguru Tachibana , Tatsuo Kato , Hideo Nunokawa
IPC分类号： H03M112
CPC分类号： H03M1/68 , H03M1/468 , H03M1/765 , H03M1/804
摘要： An A/D converter includes a capacitor type D/A conversion circuit including a capacitor array constituted of a plurality of capacitors for sampling an input potential and storing electric charge, a first resistor type D/A conversion circuit for generating a desired potential by potential division, a second resistor type D/A conversion circuit for generating a desired potential by potential division, a first signal path for adding an output of the first resistor type D/A conversion circuit to an output of the capacitor type D/A conversion circuit by capacity coupling; a second signal path for adding an output of the second resistor type D/A conversion circuit to an output of the capacitor type D/A conversion circuit by capacity coupling, and a comparing circuit for determining whether an output potential of the capacitor type D/A conversion circuit is higher or lower than an input potential, and thereby the circuit with processing time of A/D conversion being shortened can be provided.
摘要翻译： A / D转换器包括电容器型D / A转换电路，其包括由用于对输入电位进行采样并存储电荷的多个电容器构成的电容器阵列，用于通过电位产生所需电位的第一电阻器D / A转换电路用于通过电势分割产生所需电位的第二电阻器D / A转换电路，用于将第一电阻器型D / A转换电路的输出与电容器类型D / A转换电路的输出相加的第一信号路径通过容量耦合; 第二信号路径，用于通过电容耦合将第二电阻器D / A转换电路的输出加到电容器类型D / A转换电路的输出;以及比较电路，用于确定电容器类型D / A转换电路高于或低于输入电位，从而可以提供A / D转换处理时间缩短的电路。

6. 发明授权

US6084795A Ferroelectric memory device 失效
标题翻译：铁电存储器件
公开(公告)号：US6084795A
公开(公告)日：2000-07-04
申请号：US310922
申请日：1999-05-13
申请人： Hideo Nunokawa
发明人： Hideo Nunokawa
IPC分类号： G11C14/00 , G11C11/22 , G11C11/24 , G11C11/56 , G11C27/00
CPC分类号： G11C11/22 , G11C11/5657
摘要： A ferroelectric memory comprises a DA converter for receiving any one of 3 digital values as write data and for applying a write analog voltage corresponding to the input digital value to a electrode of a ferroelectric capacitor in order to cause the residual dielectric polarization in the ferroelectric capacitor, and an AD conversion circuit for receiving a read analog voltage obtained in accordance with the residual dielectric polarization value of the ferroelectric capacitor and for restoring the read analog voltage to the original digital value. In the ferroelectric capacitor, residual dielectric polarization corresponding to the write analog voltage occurs. The value of the residual dielectric polarization can be set to a plurality of values corresponding to the write analog voltage. Therefore, among 3 or more values of the write data, a predetermined value is stored in the ferroelectric capacitor. The AD conversion circuit receives the residual dielectric polarization value of the ferroelectric capacitor as a read analog voltage, and by restoring the read analog voltage to the original digital value, the written data can be read. Therefore, data of 3 or more values can be stored in one ferroelectric capacitor, and the stored data can be read properly.
摘要翻译：铁电存储器包括：一个DA转换器，用于接收3个数字值中的任何一个作为写入数据，并将与该输入数字值相对应的写入模拟电压施加到一个铁电电容器的一个电极，以便在铁电电容器中产生残留的电介质极化以及AD转换电路，用于接收根据铁电电容器的残留介电极化值获得的读取模拟电压并将读取的模拟电压恢复到原始数字值。在铁电电容器中，发生与写入模拟电压相对应的残余介电极化。残留介电极化的值可以被设定为对应于写入模拟电压的多个值。因此，在写入数据的3个以上的值中，将预定值存储在铁电电容器中。 AD转换电路接收作为读取模拟电压的铁电电容器的残留介电极化值，通过将读取的模拟电压恢复为原始数字值，可以读取写入的数据。因此，可以在一个铁电电容器中存储3个以上的数据，可以正确读取存储的数据。

7. 发明授权

US6060914A Semiconductor device including a boost circuit 有权
标题翻译：包括升压电路的半导体装置
公开(公告)号：US6060914A
公开(公告)日：2000-05-09
申请号：US131778
申请日：1998-08-10
申请人： Hideo Nunokawa
发明人： Hideo Nunokawa
IPC分类号： H01L21/8238 , G05F3/24 , G11C27/02 , H01L27/092 , H03K17/06 , H03M1/12
CPC分类号： G11C27/026 , H03K17/063
摘要： A semiconductor device includes a sample and hold circuit which has an analog switch and a first capacitor and which samples and holds an analog input signal, and a boost circuit which has a boost part which boosts a sampling clock pulse and a clamp part which limits a boosted voltage to a predetermined level. The sample and hold circuit operates a boosted sampling clock pulse. The boost circuit includes a control circuit which operates the clamp part only at the moment the sampling clock pulse changes to a high level.
摘要翻译：半导体器件包括具有模拟开关和第一电容器并且采样并保持模拟输入信号的采样和保持电路，以及升压电路，其具有提升采样时钟脉冲的升压部分和限制采样时钟脉冲的钳位部分升压至预定电平。采样和保持电路操作升压的采样时钟脉冲。升压电路包括仅在采样时钟脉冲变为高电平时操作钳位部分的控制电路。

8. 发明授权

US5811861A Semiconductor device having a power supply voltage step-down circuit 失效
标题翻译：具有电源电压降压电路的半导体装置
公开(公告)号：US5811861A
公开(公告)日：1998-09-22
申请号：US684396
申请日：1996-07-19
申请人： Hideo Nunokawa
发明人： Hideo Nunokawa
IPC分类号： H01L27/04 , G05F1/46 , G05F1/56 , G05F3/24 , G11C11/407 , H01L21/822 , H01L21/8238 , H01L27/092 , H01L29/417 , H01L29/76
CPC分类号： G05F1/468 , H01L29/41758 , Y10T307/625
摘要： A voltage step-down circuit includes a first transistor having an input terminal supplied with a first power supply voltage, an output terminal and a control terminal. A step-down voltage derived from the first power supply voltage is output through the output terminal when a load circuit to be driven by the voltage step-down circuit is in an active mode. The first transistor is OFF when the load circuit is in a standby mode. A first voltage dividing circuit has an input terminal connected to the output terminal of the first transistor, and an output terminal. A first control circuit controls a voltage of the control terminal of the first transistor so that, when the load circuit is in the active mode, a feedback control is performed on the basis of a result of comparing a reference voltage with a voltage of the output terminal of the first voltage dividing circuit, and so that, when the load circuit is in the standby mode, the feedback control is stopped and the first transistor is OFF. A resistance element cooperates with the first voltage dividing circuit so that a second voltage dividing circuit is formed, so as to divide the first power supply voltage when the load circuit is in the standby mode and so that the step-down voltage is applied to the load circuit via the resistance element.
摘要翻译：电压降压电路包括具有提供有第一电源电压的输入端子，输出端子和控制端子的第一晶体管。当由降压电路驱动的负载电路处于活动模式时，通过输出端子输出从第一电源电压得到的降压电压。当负载电路处于待机模式时，第一个晶体管截止。第一分压电路具有连接到第一晶体管的输出端的输入端和输出端。第一控制电路控制第一晶体管的控制端子的电压，使得当负载电路处于活动模式时，基于将参考电压与输出的电压进行比较的结果进行反馈控制端子，并且当负载电路处于待机模式时，反馈控制停止并且第一晶体管截止。电阻元件与第一分压电路配合，形成第二分压电路，以便在负载电路处于待机模式时将第一电源电压分压，并将降压电压施加到负载电路通过电阻元件。

9. 发明授权

US4551634A Multiplexing input circuit 失效
标题翻译：复用输入电路
公开(公告)号：US4551634A
公开(公告)日：1985-11-05
申请号：US480581
申请日：1983-03-30
申请人： Hitoshi Takahashi , Satoru Yamaguchi , Hideo Nunokawa
发明人： Hitoshi Takahashi , Satoru Yamaguchi , Hideo Nunokawa
IPC分类号： G06F3/05 , H03K17/693 , H03K17/60 , H04J3/02
CPC分类号： H03K17/693
摘要： An input circuit having a plurality of channels, each channel includes a conductor line, first and second transistors inserted in series into the conductor line and a third transistor.When a channel is not selected, the first and second transistors are turned off and the third transistor is turned on to clamp the conductor line at a predetermined constant voltage. When a channel is selected, the third transistor is turned off and first and second transistors are turned on to transfer the corresponding information input therethrough.
摘要翻译：一种具有多个通道的输入电路，每个通道包括导体线，串联插入导体线的第一和第二晶体管以及第三晶体管。当未选择通道时，第一和第二晶体管截止，第三晶体管导通，将导体线夹在预定的恒定电压。当选择通道时，第三晶体管截止，第一和第二晶体管导通，以传输从其输入的相应信息。

10. 发明申请

US20060071725A1 Oscillator and semiconductor device 有权
标题翻译：振荡器和半导体器件
公开(公告)号：US20060071725A1
公开(公告)日：2006-04-06
申请号：US11238954
申请日：2005-09-30
申请人： Hideo Nunokawa , Fukuji Kihara , Tomonari Morishita , Shunichi Ko , Hiroshi Ookawa
发明人： Hideo Nunokawa , Fukuji Kihara , Tomonari Morishita , Shunichi Ko , Hiroshi Ookawa
IPC分类号： H03B1/00
CPC分类号： H03B5/32 , H03K3/0307
摘要： An object is not only to contribute to reduction in current consumption but also to advance actuation of a system required in a camera, an on-vehicle electric component, etc. by shortening a waiting time for stabilization of oscillation. An oscillator having an inverting amplifier inverting and amplifying an input signal and outputting it, a resonator connected to between an input and an output terminals of the inverting amplifier, a feedback resistance connected in parallel to the resonator, and an output circuit outputting a first clock signal based on a signal of an on-load parallel resonance frequency or a parallel resonance frequency oscillated by the resonator, the inverting amplifier and the feedback resistance to a function block is provided.
摘要翻译：目的不仅在于减少电流消耗，而且通过缩短振荡的稳定等待时间来提高照相机，车载电气部件等所需的系统的动作。一种具有反相放大器的反相放大器，其反相并放大输入信号并输出;振荡器，连接到反相放大器的输入端和输出端之间，与谐振器并联连接的反馈电阻，以及输出电路，输出第一时钟基于谐振器振荡的负载并联谐振频率或并联谐振频率的信号，提供反相放大器和对功能块的反馈电阻的信号。

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