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1. 发明授权

US5265143A X-ray optical element including a multilayer coating 失效
标题翻译： X射线光学元件包括多层涂层
公开(公告)号：US5265143A
公开(公告)日：1993-11-23
申请号：US857
申请日：1993-01-05
申请人： Kathleen R. Early , Richard E. Howard , Donald M. Tennant , Warren K. Waskiewicz , David L. Windt
发明人： Kathleen R. Early , Richard E. Howard , Donald M. Tennant , Warren K. Waskiewicz , David L. Windt
IPC分类号： G01J1/04 , G02B5/08 , G21K1/06 , H01L21/308 , H01L21/312
CPC分类号： B82Y10/00 , G21K1/062 , G21K2201/061 , G21K2201/067
摘要： In one aspect, the invention involves an optical element in an x-ray imaging system. The element comprises a substrate overlain by a multilayer coating. The multilayer coating comprises plural first and at least second material layers in alternation. This coating is soluble in at least one etchant solution at an etching temperature less than 100.degree. C. The optical element further comprises a barrier layer intermediate the substrate and the multilayer coating. The barrier layer is relatively insoluble in the etchant solution at the etching temperature. In a second aspect of the invention, the optical element comprises a substrate and a multilayer coating as described above, and further comprises a release layer that underlies the multilayer coating. The release layer comprises a material that is relatively soluble in at least one etchant solution at an etching temperature less than 100.degree. C. In contrast to release layers of the prior art, the inventive release layer comprises germanium.
摘要翻译：在一个方面，本发明涉及x射线成像系统中的光学元件。元件包括由多层涂层覆盖的基底。多层涂层交替地包括多个第一和至少第二材料层。该涂层在小于100℃的蚀刻温度下可溶于至少一种蚀刻剂溶液。光学元件还包括位于基底和多层涂层之间的阻挡层。在蚀刻温度下，阻挡层相对不溶于蚀刻剂溶液。在本发明的第二方面，光学元件包括如上所述的基底和多层涂层，并且还包括在多层涂层下面的剥离层。剥离层包括在低于100℃的蚀刻温度下相对可溶于至少一种蚀刻剂溶液的材料。与现有技术的剥离层相反，本发明的剥离层包括锗。

2. 发明授权

US5356662A Method for repairing an optical element which includes a multilayer coating 失效
标题翻译：修复包括多层涂层的光学元件的方法
公开(公告)号：US5356662A
公开(公告)日：1994-10-18
申请号：US856
申请日：1993-01-05
申请人： Kathleen R. Early , Donald M. Tennant , Warren K. Waskiewicz , David L. Windt
发明人： Kathleen R. Early , Donald M. Tennant , Warren K. Waskiewicz , David L. Windt
IPC分类号： G02B5/08 , G03F1/24 , G03F1/72 , G21K1/06 , H01L21/308 , H01L21/312 , B32B35/00 , B05D5/06
CPC分类号： B82Y10/00 , B82Y40/00 , G03F1/24 , G03F1/72 , G21K1/062 , G21K2201/061 , G21K2201/067
摘要： The invention in one aspect involves a method for repairing an optical system. The optical system includes at least one optical element which comprises, in turn, a substrate having a principal surface, and a multilayer coating overlying the principal surface. The substrate comprises a first material, and the multilayer coating comprises plural second and at least third material layers in alternation. The method includes the steps of removing the multilayer coating from the substrate, and redepositing a new multilayer coating on the substrate. The old multilayer coating is removed in a single etching step while preserving the quality of the principal surface to such an extent that the peak reflectivity of the new multilayer coating is at least 80% the reflectivity of the old multilayer coating.In a second aspect, the invention involves a method for repairing an optical system of the kind described above, in which the optical element comprises a substrate having a principal surface, a layer of chromium overlying the principal surface, and a first layer of iridium overlying the chromium layer. The method comprises the steps of removing the first iridium layer from the substrate; and forming a second iridium coating on the substrate. The iridium layer is removed by exposing the iridium and chromium layers to an aqueous solution comprising potassium ferricyanide and sodium hydroxide, resulting in substantial dissolution of the chromium layer.
摘要翻译：本发明在一个方面涉及一种用于修复光学系统的方法。该光学系统包括至少一个光学元件，该光学元件又包括具有主表面的基底和覆盖在主表面上的多层涂层。所述基板包括第一材料，并且所述多层涂层交替地包括多个第二和至少第三材料层。该方法包括从衬底上去除多层涂层并将新的多层涂层重新沉积在衬底上的步骤。在单个蚀刻步骤中除去旧的多层涂层，同时保持主表面的质量，使得新的多层涂层的峰值反射率为旧多层涂层的反射率的至少80％。在第二方面，本发明涉及一种用于修复上述类型的光学系统的方法，其中光学元件包括具有主表面的基底，覆盖在主表面上的铬层和第一层铱覆盖层铬层。该方法包括从基板去除第一铱层的步骤; 以及在所述基底上形成第二铱涂层。通过将铱和铬层暴露于含有铁氰化钾和氢氧化钠的水溶液中来除去铱层，导致铬层的实质溶解。

3. 发明授权

US5978441A Extreme ultraviolet lithography mask blank and manufacturing method therefor 失效
公开(公告)号：US5978441A
公开(公告)日：1999-11-02
申请号：US980554
申请日：1997-12-01
申请人： Kathleen R. Early
发明人： Kathleen R. Early
IPC分类号： G03F1/00 , G03F1/24 , G03F1/60 , G03F7/20 , G21K1/06
CPC分类号： B82Y40/00 , B82Y10/00 , G03F1/24 , G03F1/60 , G03F7/2047 , G21K2201/067
摘要： A reflective element for extreme ultraviolet semiconductor lithography systems substantially minimizes the phase transitions of reflected extreme ultraviolet light by a reflective multilayer coating on an extremely planar surface which is parallel to a family of (111) crystallographic planes of a single crystal silicon wafer. The extremely planar surface is made by using three of the families of (111) crystallographic planes of the single crystal silicon as etch barriers for anisotropic etchants.

4. 发明授权

US06291137B1 Sidewall formation for sidewall patterning of sub 100 nm structures 失效
标题翻译：侧壁形成用于侧向图案化的亚100nm结构
公开(公告)号：US06291137B1
公开(公告)日：2001-09-18
申请号：US09234380
申请日：1999-01-20
申请人： Christopher F. Lyons , Michael K. Templeton , Kathleen R. Early
发明人： Christopher F. Lyons , Michael K. Templeton , Kathleen R. Early
IPC分类号： G03C500
CPC分类号： H01L21/76885 , H01L21/28132 , H01L21/32136 , H01L21/32137 , H01L21/32139
摘要： In one embodiment, the present invention relates to a method of forming a conductive structure having a width of about 100 nm or less, involving the steps of providing a substrate having a conductive film; patterning a sidewall template over a first portion of the conductive film wherein a second portion of the conductive film is exposed, the sidewall template having at least one sidewall over the conductive film; depositing a sidewall film over the conductive film and the sidewall template, the sidewall film having a vertical portion adjacent the sidewall of the sidewall template and a horizontal portion in areas not adjacent the sidewall of the sidewall template; removing the horizontal portion of the sidewall film exposing a third portion of the conductive film; removing the sidewall template exposing a fourth portion of the conductive film; and etching the third portion and the fourth portion of the conductive film thereby providing the conductive structure having a width of about 100 nm or less underlying the vertical portion of the sidewall film.
摘要翻译：在一个实施例中，本发明涉及一种形成宽度为约100nm或更小的导电结构的方法，包括提供具有导电膜的基板的步骤; 在所述导电膜的第一部分上图案化侧壁模板，其中所述导电膜的第二部分被暴露，所述侧壁模板在所述导电膜上具有至少一个侧壁; 在所述导电膜和所述侧壁模板上沉积侧壁膜，所述侧壁膜具有邻近所述侧壁模板的侧壁的垂直部分和在不邻近所述侧壁模板的侧壁的区域中的水平部分; 去除暴露导电膜的第三部分的侧壁膜的水平部分; 去除暴露导电膜的第四部分的侧壁模板; 并且蚀刻导电膜的第三部分和第四部分，从而提供具有约100nm或更小的宽度在该侧壁膜的垂直部分下方的导电结构。

5. 发明授权

US06269322B1 System and method for wafer alignment which mitigates effects of reticle rotation and magnification on overlay 有权
标题翻译：用于晶片对准的系统和方法，其减轻掩模旋转和放大对覆盖物的影响
公开(公告)号：US06269322B1
公开(公告)日：2001-07-31
申请号：US09266361
申请日：1999-03-11
申请人： Michael K. Templeton , Bharath Rangarajan , Kathleen R. Early , Terry Manchester
发明人： Michael K. Templeton , Bharath Rangarajan , Kathleen R. Early , Terry Manchester
IPC分类号： G03B2742
CPC分类号： G03F9/70
摘要： The present invention relates to wafer alignment. A reticle is employed which includes, a design and first and second alignment marks. The second alignment mark is symmetric to the first alignment mark such that a reticle center point is a midpoint of the first and second alignment marks. The first alignment mark is printed on a surface layer of the wafer. The second alignment mark is printed on the surface layer at an offset from the first alignment mark. A virtual alignment mark is determined, the virtual alignment mark being a midpoint of the printed first and second alignment marks. The virtual alignment mark is employed to facilitate aligning the wafer. The symmetric relationship between the first and second alignment mark results in the negation of print errors of the marks due to reticle rotation and/or lens magnification with respect to the virtual alignment mark. The employment of the virtual alignment mark in wafer alignment substantially facilitates mitigation of overlay error.
摘要翻译：本发明涉及晶圆对准。使用掩模版，其包括设计和第一和第二对准标记。第二对准标记与第一对准标记对称，使得标线片中心点是第一和第二对准标记的中点。将第一对准标记印刷在晶片的表面层上。第二对准标记以与第一对准标记偏移的方式印刷在表面层上。确定虚拟对准标记，虚拟对准标记是打印的第一和第二对准标记的中点。采用虚拟对准标记以便于对准晶片。第一和第二对准标记之间的对称关系导致相对于虚拟对准标记由于标线旋转和/或透镜放大而导致的标记的打印错误的否定。在晶片对准中使用虚拟对准标记基本上有助于减轻重叠误差。

6. 发明授权

US06232002B1 Bilayer anti-reflective coating and etch hard mask 有权
标题翻译：双层抗反射涂层和蚀刻硬掩模
公开(公告)号：US06232002B1
公开(公告)日：2001-05-15
申请号：US09186920
申请日：1998-11-06
申请人： Kathleen R. Early , Suzette K. Pangrle , Maria C. Chan , Lewis Shen
发明人： Kathleen R. Early , Suzette K. Pangrle , Maria C. Chan , Lewis Shen
IPC分类号： B32B1800
CPC分类号： H01L21/32139 , H01L21/3081 , H01L21/3143 , H01L21/31612 , Y10T428/259
摘要： In the manufacture of sub 0.35 micron semiconductors using deep ultraviolet lithography, a bilayer of silicon dioxide on top of silicon oxynitride is used as bottom anti-reflective coating and an etch hard mask for photolithographic resist. Since the silicon dioxide is optically transparent at the deep ultraviolet wavelengths being used (248 nm), its thickness in combination with a preselected reflective silicon oxynitride thickness satisfies the zero reflectivity goal and, at the same time, is adequately thick to serve as a hard mask for self-aligned etch and self-aligned-source etch.
摘要翻译：在使用深紫外光刻技术的0.35微米半导体的制造中，使用氮氧化硅顶部的二氧化硅双层作为底部抗反射涂层和用于光刻抗蚀剂的蚀刻硬掩模。由于二氧化硅在使用的深紫外波长（248nm）下是光学透明的，其厚度与预选的反射氮氧化硅厚度相结合，满足零反射率目标，并且同时足够厚以用作硬掩模，用于自对准蚀刻和自对准源蚀刻。

7. 发明授权

US6110833A Elimination of oxynitride (ONO) etch residue and polysilicon stringers through isolation of floating gates on adjacent bitlines by polysilicon oxidation 失效
标题翻译：通过多晶硅氧化隔离相邻位线上的浮栅，消除氧氮化物（ONO）蚀刻残渣和多晶硅桁架
公开(公告)号：US6110833A
公开(公告)日：2000-08-29
申请号：US33836
申请日：1998-03-03
申请人： Kathleen R. Early , Michael K. Templeton , Nicholas H. Tripsas , Maria C. Chan
发明人： Kathleen R. Early , Michael K. Templeton , Nicholas H. Tripsas , Maria C. Chan
IPC分类号： A61K38/00 , A61K38/30 , H01L21/8247 , H01L21/70
CPC分类号： H01L27/11521 , A61K38/30
摘要： A method for fabricating a first memory cell and a second memory cell electrically isolated from each other is provided. A first polysilicon (poly I) layer is formed on an oxide coated substrate. Then, a sacrificial oxide layer and nitride layer are formed for masking the poly I layer. At least a portion of the masking layer is etched to pattern the first memory cell and the second memory cell and an unmasked portion therebetween. The unmasked portion of the poly I layer is transformed into an insulator via thermal oxidation such that the insulator separates a floating gate of the first memory cell from a floating gate of the second memory cell. The insulator is etched so as to form a gap having gradually sloping sidewalls between a floating gate of the first memory cell and a floating gate of the second memory cell, the gap isolating the floating gate of the first memory cell from the floating gate of the second memory cell. Thereafter, an interpoly dielectric layer and a second polysilicon (poly II) layer are formed substantially free of abrupt changes in step height.
摘要翻译：提供了一种用于制造彼此电隔离的第一存储单元和第二存储单元的方法。在氧化物涂覆的基底上形成第一多晶硅（poly I）层。然后，形成用于掩蔽多晶硅层的牺牲氧化物层和氮化物层。蚀刻掩模层的至少一部分以对第一存储单元和第二存储单元进行图案化，并且在其间形成未屏蔽部分。多层I层的未屏蔽部分通过热氧化转变为绝缘体，使得绝缘体将第一存储器单元的浮置栅极与第二存储单元的浮置栅极分开。绝缘体被蚀刻以形成在第一存储单元的浮动栅极和第二存储单元的浮置栅极之间具有逐渐倾斜的侧壁的间隙，将第一存储单元的浮置栅极与第一存储单元的浮动栅极隔离的间隙第二存储单元。此后，形成基本上不具有台阶高度突然变化的互聚电介质层和第二多晶硅（poly II）层。

8. 发明授权

US6043120A Elimination of oxynitride (ONO) etch residue and polysilicon stringers through isolation of floating gates on adjacent bitlines by polysilicon oxidation 失效
标题翻译：通过多晶硅氧化隔离相邻位线上的浮栅，消除氧氮化物（ONO）蚀刻残渣和多晶硅桁架
公开(公告)号：US6043120A
公开(公告)日：2000-03-28
申请号：US33723
申请日：1998-03-03
申请人： Kathleen R. Early , Michael K. Templeton , Nicholas H. Tripsas , Maria C. Chan
发明人： Kathleen R. Early , Michael K. Templeton , Nicholas H. Tripsas , Maria C. Chan
IPC分类号： H01L21/8247
CPC分类号： H01L27/11521
摘要： A method for fabricating a first memory cell and a second memory cell electrically isolated from each other. A first polysilicon (poly I) layer is formed on an oxide coated substrate. A masking layer is deposited or grown on the poly I layer, and at least a portion of the masking layer is etched so as to pattern the first memory cell and the second memory cell and an unmasked portion therebetween. The unmasked portion of the poly I layer is transformed into an insulator via thermal oxidation such that the insulator electrically isolates a floating gate of the first memory cell from a floating gate of the second memory cell. An interpoly dielectric layer and a second polysilicon (poly II) layer is formed over the poly I layer and insulator substantially free of abrupt changes in step height.
摘要翻译：一种用于制造彼此电隔离的第一存储单元和第二存储单元的方法。在氧化物涂覆的基底上形成第一多晶硅（poly I）层。在多晶硅层上沉积或生长掩模层，并且蚀刻掩模层的至少一部分，以便对第一存储单元和第二存储单元进行图案化，并且在其间形成未屏蔽部分。多层I层的未屏蔽部分通过热氧化转变为绝缘体，使得绝缘体将第一存储器单元的浮置栅极与第二存储单元的浮置栅极电隔离。在多层I层和绝缘体上形成多层介电层和第二多晶硅（poly II）层，绝缘体基本上没有台阶高度的突然变化。

9. 发明授权

US06534243B1 Chemical feature doubling process 有权
标题翻译：化学特征加倍工艺
公开(公告)号：US06534243B1
公开(公告)日：2003-03-18
申请号：US10000493
申请日：2001-10-23
申请人： Michael K. Templeton , Ramkumar Subramanian , Bharath Rangarajan , Kathleen R. Early , Ursula Q. Quinto
发明人： Michael K. Templeton , Ramkumar Subramanian , Bharath Rangarajan , Kathleen R. Early , Ursula Q. Quinto
IPC分类号： G03F7039
CPC分类号： G03F7/405 , G03F7/0035 , G03F7/40
摘要： In one embodiment, the present invention relates to a method of treating a patterned resist involving providing the patterned resist having a first number of structural features, the patterned resist comprising an acid catalyzed polymer; contacting a coating containing a coating material, at least one basic compound, a photoacid generator, and a dye with the patterned resist; irradiating the coated patterned resist; permitting a deprotection region to form within an inner portion of the patterned resist; and removing the coating and the deprotection region to provide a second number of patterned resist structural features, wherein the first number is smaller than the second number.
摘要翻译：在一个实施方案中，本发明涉及一种处理图案化抗蚀剂的方法，包括提供具有第一数目的结构特征的图案化抗蚀剂，所述图案化抗蚀剂包含酸催化聚合物; 使含有涂层材料的涂层，至少一种碱性化合物，光致酸发生剂和染料与图案化的抗蚀剂接触; 照射经涂覆的图案化抗蚀剂; 允许在图案化抗蚀剂的内部部分内形成去保护区; 并且去除涂层和去保护区域以提供第二数量的图案化抗蚀剂结构特征，其中第一数目小于第二数量。

10. 发明授权

US06352930B1 Bilayer anti-reflective coating and etch hard mask 有权
标题翻译：双层抗反射涂层和蚀刻硬掩模
公开(公告)号：US06352930B1
公开(公告)日：2002-03-05
申请号：US09814636
申请日：2001-03-22
申请人： Kathleen R. Early , Suzette K. Pangrle , Maria C. Chan , Lewis Shen
发明人： Kathleen R. Early , Suzette K. Pangrle , Maria C. Chan , Lewis Shen
IPC分类号： H01L21302
CPC分类号： H01L21/32139 , H01L21/3081 , H01L21/3143 , H01L21/31612 , Y10T428/259
摘要： In the manufacture of sub-0.35 micron semiconductors using deep ultraviolet lithography, a bilayer of silicon dioxide on top of silicon oxynitride is used as bottom anti-reflective coating and an etch hard mask for photolithographic resist. Since the silicon dioxide is optically transparent at the deep ultraviolet wavelengths being used (248 nm), its thickness in combination with a preselected reflective silicon oxynitride thickness satisfies the zero reflectivity goal and, at the same time, is adequately thick to serve as a hard mask for self-aligned etch and self-aligned-source etch.
摘要翻译：在使用深紫外光刻技术的0.35微米半导体的制造中，使用氮氧化硅顶部的二氧化硅双层作为底部抗反射涂层和用于光刻抗蚀剂的蚀刻硬掩模。由于二氧化硅在使用的深紫外波长（248nm）下是光学透明的，其厚度与预选的反射氮氧化硅厚度相结合，满足零反射率目标，并且同时足够厚以用作硬掩模，用于自对准蚀刻和自对准源蚀刻。

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