专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07419867B2 CMOS gate structure comprising predoped semiconductor gate material with improved uniformity of dopant distribution and method of forming the structure 失效
标题翻译： CMOS栅极结构包括具有改善的掺杂剂分布均匀性的预制半导体栅极材料和形成该结构的方法
公开(公告)号：US07419867B2
公开(公告)日：2008-09-02
申请号：US11154878
申请日：2005-06-16
申请人： Karsten Wieczorek , Manfred Horstmann , Thomas Feudel
发明人： Karsten Wieczorek , Manfred Horstmann , Thomas Feudel
IPC分类号： H01L21/8238
CPC分类号： H01L21/28052 , H01L21/823842 , H01L29/665 , H01L29/6659 , H01L29/7833
摘要： By predoping of a layer of deposited semiconductor gate material by incorporating dopants during the deposition process, a high uniformity of the dopant distribution may be achieved in the gate electrodes of CMOS devices subsequently formed in the layer of gate material. The improved uniformity of the dopant distribution results in reduced gate depletion and reduced threshold voltage shift in the transistors of the CMOS devices.
摘要翻译：通过在沉积工艺期间通过掺入掺杂剂预先淀积沉积的半导体栅极材料，可以在随后在栅极材料层中形成的CMOS器件的栅电极中实现掺杂物分布的高均匀性。掺杂剂分布的改进的均匀性导致CMOS器件的晶体管中栅极耗尽减少和阈值电压偏移降低。

2. 发明授权

US06821887B2 Method of forming a metal silicide gate in a standard MOS process sequence 有权
标题翻译：在标准MOS工艺序列中形成金属硅化物栅的方法
公开(公告)号：US06821887B2
公开(公告)日：2004-11-23
申请号：US10391243
申请日：2003-03-18
申请人： Karsten Wieczorek , Stephan Kruegel , Manfred Horstmann , Thomas Feudel
发明人： Karsten Wieczorek , Stephan Kruegel , Manfred Horstmann , Thomas Feudel
IPC分类号： H01L21302
CPC分类号： H01L21/28194 , H01L21/28097 , H01L29/511 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/665 , H01L29/66507
摘要： The polysilicon gate electrode of a MOS transistor may be substantially completely converted into a metal silicide without sacrificing the drain and source junctions in that a thickness of the polysilicon layer, for forming the gate electrode, is targeted to be substantially converted into metal silicide in a subsequent silicidation process. The gate electrode, substantially comprised of metal silicide, offers high conductivity even at critical dimensions in the deep sub-micron range, while at the same time the effect of polysilicon gate depletion is significantly reduced. Manufacturing of the MOS transistor, having the substantially fully-converted metal silicide gate electrode, is essentially compatible with standard MOS process technology.
摘要翻译： MOS晶体管的多晶硅栅电极可以基本上完全转变为金属硅化物，而不牺牲漏极和源极结，因为用于形成栅电极的多晶硅层的厚度被靶向为基本上转化为金属硅化物随后的硅化工艺。基本上由金属硅化物组成的栅极电极甚至在深亚微米范围内的临界尺寸下也提供高导电性，同时多晶硅栅极耗尽的效果显着降低。具有基本上完全转换的金属硅化物栅电极的MOS晶体管的制造基本上与标准MOS工艺技术相兼容。

3. 发明申请

US20060094183A1 CMOS gate structure comprising predoped semiconductor gate material with improved uniformity of dopant distribution and method of forming the structure 失效
标题翻译： CMOS栅极结构包括具有改善的掺杂剂分布均匀性的预制半导体栅极材料和形成该结构的方法
公开(公告)号：US20060094183A1
公开(公告)日：2006-05-04
申请号：US11154878
申请日：2005-06-16
申请人： Karsten Wieczorek , Manfred Horstmann , Thomas Feudel
发明人： Karsten Wieczorek , Manfred Horstmann , Thomas Feudel
IPC分类号： H01L21/8238
CPC分类号： H01L21/28052 , H01L21/823842 , H01L29/665 , H01L29/6659 , H01L29/7833
摘要： By predoping of a layer of deposited semiconductor gate material by incorporating dopants during the deposition process, a high uniformity of the dopant distribution may be achieved in the gate electrodes of CMOS devices subsequently formed in the layer of gate material. The improved uniformity of the dopant distribution results in reduced gate depletion and reduced threshold voltage shift in the transistors of the CMOS devices.
摘要翻译：通过在沉积工艺期间通过掺入掺杂剂预先淀积沉积的半导体栅极材料，可以在随后在栅极材料层中形成的CMOS器件的栅电极中实现掺杂物分布的高均匀性。掺杂剂分布的改进的均匀性导致CMOS器件的晶体管中栅极耗尽减少和阈值电压偏移降低。

4. 发明授权

US06849516B2 Methods of forming drain/source extension structures of a field effect transistor using a doped high-k dielectric layer 失效
标题翻译：使用掺杂的高k电介质层形成场效应晶体管的漏极/源延伸结构的方法
公开(公告)号：US06849516B2
公开(公告)日：2005-02-01
申请号：US10442745
申请日：2003-05-21
申请人： Thomas Feudel , Manfred Horstmann , Karsten Wieczorek , Stephan Kruegel
发明人： Thomas Feudel , Manfred Horstmann , Karsten Wieczorek , Stephan Kruegel
IPC分类号： H01L21/225 , H01L21/336 , H01L29/78 , H01L21/3205
CPC分类号： H01L29/6659 , H01L21/2253 , H01L29/665 , H01L29/7833
摘要： According to one illustrative embodiment of the present invention, a method of forming a field effect transistor includes the formation of a doped high-k dielectric layer above a substrate including a gate electrode formed over an active region and separated therefrom by a gate insulation layer. A heat treatment is carried out with the substrate to diffuse dopants from the high-k dielectric layer into the active region to form extension regions. The high-k dielectric layer is patterned to form sidewall spacers at sidewalls of the gate electrode and an implantation process is carried out with the sidewall spacers as implantation mask to form source and drain regions.
摘要翻译：根据本发明的一个说明性实施例，形成场效应晶体管的方法包括在包括在有源区上形成并由栅极绝缘层分离的栅电极的衬底上形成掺杂的高k电介质层。用衬底进行热处理以将掺杂剂从高k电介质层扩散到活性区域中以形成延伸区域。图案化高k电介质层以在栅电极的侧壁处形成侧壁间隔物，并且以侧壁间隔物作为注入掩模进行注入工艺以形成源区和漏区。

5. 发明授权

US07955937B2 Method for manufacturing semiconductor device comprising SOI transistors and bulk transistors 有权
标题翻译：包括SOI晶体管和体晶体管的半导体器件的制造方法
公开(公告)号：US07955937B2
公开(公告)日：2011-06-07
申请号：US11560896
申请日：2006-11-17
申请人： Karsten Wieczorek , Manfred Horstmann , Thomas Feudel , Thomas Heller
发明人： Karsten Wieczorek , Manfred Horstmann , Thomas Feudel , Thomas Heller
IPC分类号： H01L21/331
CPC分类号： H01L21/823481 , H01L21/76243 , H01L21/823878 , H01L21/84 , H01L27/0922 , H01L27/1203 , H01L27/1207
摘要： By forming bulk-like transistors in sensitive RAM areas of otherwise SOI-based CMOS circuits, a significant savings in valuable chip area may be achieved since the RAM areas may be formed on the basis of a bulk transistor configuration, thereby eliminating hysteresis effects that may typically be taken into consideration by providing transistors of increased transistor width or by providing body ties. Hence, the benefit of high switching speed may be maintained in speed-critical circuitry, such as CPU cores, while at the same time the RAM circuit may be formed in a highly space-efficient manner.
摘要翻译：通过在其它基于SOI的CMOS电路的敏感RAM区域中形成块状晶体管，可以实现有价值的芯片面积的显着节省，因为可以基于体晶体管配置形成RAM区域，从而消除可能通常通过提供增加的晶体管宽度的晶体管或通过提供身体纽带来考虑。因此，高速切换速度的好处可以保持在诸如CPU内核之类的速度关键电路中，同时可以以高空间效率的方式形成RAM电路。

6. 发明申请

US20070228377A1 SEMICONDUCTOR DEVICE COMPRISING SOI TRANSISTORS AND BULK TRANSISTORS AND A METHOD OF FORMING THE SAME 有权
标题翻译：包含SOI晶体管和块晶体管的半导体器件及其形成方法
公开(公告)号：US20070228377A1
公开(公告)日：2007-10-04
申请号：US11560896
申请日：2006-11-17
申请人： Karsten Wieczorek , Manfred Horstmann , Thomas Feudel , Thomas Heller
发明人： Karsten Wieczorek , Manfred Horstmann , Thomas Feudel , Thomas Heller
IPC分类号： H01L29/76 , H01L21/84
CPC分类号： H01L21/823481 , H01L21/76243 , H01L21/823878 , H01L21/84 , H01L27/0922 , H01L27/1203 , H01L27/1207
摘要： By forming bulk-like transistors in sensitive RAM areas of otherwise SOI-based CMOS circuits, a significant savings in valuable chip area may be achieved since the RAM areas may be formed on the basis of a bulk transistor configuration, thereby eliminating hysteresis effects that may typically be taken into consideration by providing transistors of increased transistor width or by providing body ties. Hence, the benefit of high switching speed may be maintained in speed-critical circuitry, such as CPU cores, while at the same time the RAM circuit may be formed in a highly space-efficient manner.
摘要翻译：通过在其它基于SOI的CMOS电路的敏感RAM区域中形成块状晶体管，可以实现有价值的芯片面积的显着节省，因为可以基于体晶体管配置形成RAM区域，从而消除可能通常通过提供增加的晶体管宽度的晶体管或通过提供身体纽带来考虑。因此，高速切换速度的好处可以保持在诸如CPU内核之类的速度关键电路中，同时可以以高空间效率的方式形成RAM电路。

7. 发明申请

US20050098818A1 Drain/source extension structure of a field effect transistor including doped high-k sidewall spacers 审中-公开
标题翻译：包括掺杂的高k侧壁间隔物的场效应晶体管的漏极/源延伸结构
公开(公告)号：US20050098818A1
公开(公告)日：2005-05-12
申请号：US11015061
申请日：2004-12-17
申请人： Thomas Feudel , Manfred Horstmann , Karsten Wieczorek , Stephan Kruegel
发明人： Thomas Feudel , Manfred Horstmann , Karsten Wieczorek , Stephan Kruegel
IPC分类号： H01L21/225 , H01L21/336 , H01L29/78 , H01L29/76
CPC分类号： H01L29/6659 , H01L21/2253 , H01L29/665 , H01L29/7833
摘要： High-k dielectric spacer elements on the gate electrode of a field effects transistor in combination with an extension region that is formed by dopant diffusion from the high-k spacer elements into the underlying semiconductor region provides for an increased charge carrier density in the extension region. In this way, the limitation of the charge carrier density to approximately the solid solubility of dopants in the extension region may be overcome, thereby allowing extremely shallow extension regions without unduly compromising the transistor performance.
摘要翻译：场效应晶体管的栅极上的高k电介质隔离元件与由高k隔离元件掺入到下面的半导体区域中的掺杂剂扩散形成的延伸区组合提供了延伸区中增加的电荷载流子密度。以这种方式，可以克服电荷载流子密度近似于扩散区域中掺杂剂的固溶度的限制，从而允许非常浅的延伸区域而不会不利地损害晶体管的性能。

8. 发明授权

US06806153B2 Method of manufacturing a field effect transistor 有权
标题翻译：制造场效应晶体管的方法
公开(公告)号：US06806153B2
公开(公告)日：2004-10-19
申请号：US10462893
申请日：2003-06-17
申请人： Karsten Wieczorek , Manfred Horstmann , Thomas Feudel
发明人： Karsten Wieczorek , Manfred Horstmann , Thomas Feudel
IPC分类号： H01L21336
CPC分类号： H01L29/6659 , H01L21/2022 , H01L21/26506 , H01L21/26513
摘要： The present invention allows the manufacturing of field effect transistors with reduced thermal budget. A first amorphized region and a second amorphized region are formed in a substrate adjacent to the gate electrode by implanting ions of a non-doping element, the presence of which does not significantly alter the conductive properties of the substrate. The formation of the amorphized regions may be performed before or after the formation of a source region, a drain region, an extended source region and an extended drain region. The substrate is annealed to achieve solid phase epitaxial regrowth of the amorphized regions and to activate dopants in the source region, the drain region, the extended source region and the extended drain region.
摘要翻译：本发明允许制造具有降低的热预算的场效应晶体管。第一非晶化区域和第二非晶区域通过注入非掺杂元素的离子形成在与栅电极相邻的衬底中，其不存在不会显着地改变衬底的导电性能。非晶化区域的形成可以在形成源极区域，漏极区域，扩展源极区域和延伸的漏极区域之前或之后进行。将衬底退火以实现非晶化区域的固相外延再生长并激活源极区域，漏极区域，扩展源极区域和延伸漏极区域中的掺杂剂。

9. 发明授权

US06410410B1 Method of forming lightly doped regions in a semiconductor device 有权
标题翻译：在半导体器件中形成轻掺杂区域的方法
公开(公告)号：US06410410B1
公开(公告)日：2002-06-25
申请号：US09852535
申请日：2001-05-10
申请人： Thomas Feudel , Manfred Horstmann , Karsten Wieczorek
发明人： Thomas Feudel , Manfred Horstmann , Karsten Wieczorek
IPC分类号： H01L21225
CPC分类号： H01L29/6659 , H01L21/2255 , H01L29/42368 , H01L29/7833
摘要： A method is disclosed in which a lightly doped region in a semiconductor layer is obtained by diffusing dopant atoms of a first and second type into the underlying semiconductor layer. Preferably, the method is applied to the formation of lightly doped source and drain regions in a field effect transistor so as to obtain a required gradual dopant concentration transition from the general region to the drain and source regions for avoiding the hot carrier effect. Advantageously, a diffusion of the dopant atoms is initiated during an oxidizing step in which the thickness of the gate insulation layer is increased at the edge portions thereof.
摘要翻译：公开了一种通过将第一和第二类型的掺杂剂原子扩散到下面的半导体层中而获得半导体层中的轻掺杂区域的方法。优选地，该方法被应用于在场效应晶体管中形成轻掺杂的源极和漏极区域，以便获得从一般区域到漏极和源极区域所需的逐渐掺杂剂浓度跃迁，以避免热载流子效应。有利地，掺杂剂原子的扩散在其栅极绝缘层的厚度在其边缘部分增加的氧化步骤期间开始。

10. 发明授权

US07297994B2 Semiconductor device having a retrograde dopant profile in a channel region 有权
标题翻译：半导体器件在沟道区域具有逆向掺杂物分布
公开(公告)号：US07297994B2
公开(公告)日：2007-11-20
申请号：US11072142
申请日：2005-03-04
申请人： Karsten Wieczorek , Manfred Horstmann , Rolf Stephan
发明人： Karsten Wieczorek , Manfred Horstmann , Rolf Stephan
IPC分类号： H10L29/00 , H01L29/80
CPC分类号： H01L21/823807 , H01L29/1033 , H01L29/105 , H01L29/1054 , H01L29/6659
摘要： An epitaxially grown channel layer is provided on a well structure after ion implantation steps and heat treatment steps are performed to establish a required dopant profile in the well structure. The channel layer may be undoped or slightly doped, as required, so that the finally obtained dopant concentration in the channel layer is significantly reduced compared to a conventional device to thereby provide a retrograde dopant profile in a channel region of a field effect transistor. Additionally, a barrier diffusion layer may be provided between the well structure and the channel layer to reduce up-diffusion during any heat treatments carried out after the formation of the channel layer. The final dopant profile in the channel region may be adjusted by the thickness of the channel layer, the thickness and the composition of the diffusion barrier layer and any additional implantation steps to introduce dopant atoms in the channel layer.
摘要翻译：在离子注入步骤之后在阱结构上提供外延生长的沟道层，并且进行热处理步骤以在阱结构中建立所需的掺杂剂分布。根据需要，沟道层可以是未掺杂的或稍微掺杂的，使得与常规器件相比，沟道层中最终获得的掺杂剂浓度显着降低，从而在场效应晶体管的沟道区域中提供逆向掺杂物分布。此外，可以在阱结构和沟道层之间提供阻挡扩散层，以在形成沟道层之后进行的任何热处理期间减小向上扩散。可以通过沟道层的厚度，扩散阻挡层的厚度和组成以及在沟道层中引入掺杂剂原子的任何额外的注入步骤来调整沟道区中的最终掺杂物分布。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式