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1. 发明授权

US06821887B2 Method of forming a metal silicide gate in a standard MOS process sequence 有权
标题翻译：在标准MOS工艺序列中形成金属硅化物栅的方法
公开(公告)号：US06821887B2
公开(公告)日：2004-11-23
申请号：US10391243
申请日：2003-03-18
申请人： Karsten Wieczorek , Stephan Kruegel , Manfred Horstmann , Thomas Feudel
发明人： Karsten Wieczorek , Stephan Kruegel , Manfred Horstmann , Thomas Feudel
IPC分类号： H01L21302
CPC分类号： H01L21/28194 , H01L21/28097 , H01L29/511 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/665 , H01L29/66507
摘要： The polysilicon gate electrode of a MOS transistor may be substantially completely converted into a metal silicide without sacrificing the drain and source junctions in that a thickness of the polysilicon layer, for forming the gate electrode, is targeted to be substantially converted into metal silicide in a subsequent silicidation process. The gate electrode, substantially comprised of metal silicide, offers high conductivity even at critical dimensions in the deep sub-micron range, while at the same time the effect of polysilicon gate depletion is significantly reduced. Manufacturing of the MOS transistor, having the substantially fully-converted metal silicide gate electrode, is essentially compatible with standard MOS process technology.
摘要翻译： MOS晶体管的多晶硅栅电极可以基本上完全转变为金属硅化物，而不牺牲漏极和源极结，因为用于形成栅电极的多晶硅层的厚度被靶向为基本上转化为金属硅化物随后的硅化工艺。基本上由金属硅化物组成的栅极电极甚至在深亚微米范围内的临界尺寸下也提供高导电性，同时多晶硅栅极耗尽的效果显着降低。具有基本上完全转换的金属硅化物栅电极的MOS晶体管的制造基本上与标准MOS工艺技术相兼容。

2. 发明授权

US06849516B2 Methods of forming drain/source extension structures of a field effect transistor using a doped high-k dielectric layer 失效
标题翻译：使用掺杂的高k电介质层形成场效应晶体管的漏极/源延伸结构的方法
公开(公告)号：US06849516B2
公开(公告)日：2005-02-01
申请号：US10442745
申请日：2003-05-21
申请人： Thomas Feudel , Manfred Horstmann , Karsten Wieczorek , Stephan Kruegel
发明人： Thomas Feudel , Manfred Horstmann , Karsten Wieczorek , Stephan Kruegel
IPC分类号： H01L21/225 , H01L21/336 , H01L29/78 , H01L21/3205
CPC分类号： H01L29/6659 , H01L21/2253 , H01L29/665 , H01L29/7833
摘要： According to one illustrative embodiment of the present invention, a method of forming a field effect transistor includes the formation of a doped high-k dielectric layer above a substrate including a gate electrode formed over an active region and separated therefrom by a gate insulation layer. A heat treatment is carried out with the substrate to diffuse dopants from the high-k dielectric layer into the active region to form extension regions. The high-k dielectric layer is patterned to form sidewall spacers at sidewalls of the gate electrode and an implantation process is carried out with the sidewall spacers as implantation mask to form source and drain regions.
摘要翻译：根据本发明的一个说明性实施例，形成场效应晶体管的方法包括在包括在有源区上形成并由栅极绝缘层分离的栅电极的衬底上形成掺杂的高k电介质层。用衬底进行热处理以将掺杂剂从高k电介质层扩散到活性区域中以形成延伸区域。图案化高k电介质层以在栅电极的侧壁处形成侧壁间隔物，并且以侧壁间隔物作为注入掩模进行注入工艺以形成源区和漏区。

3. 发明申请

US20050098818A1 Drain/source extension structure of a field effect transistor including doped high-k sidewall spacers 审中-公开
标题翻译：包括掺杂的高k侧壁间隔物的场效应晶体管的漏极/源延伸结构
公开(公告)号：US20050098818A1
公开(公告)日：2005-05-12
申请号：US11015061
申请日：2004-12-17
申请人： Thomas Feudel , Manfred Horstmann , Karsten Wieczorek , Stephan Kruegel
发明人： Thomas Feudel , Manfred Horstmann , Karsten Wieczorek , Stephan Kruegel
IPC分类号： H01L21/225 , H01L21/336 , H01L29/78 , H01L29/76
CPC分类号： H01L29/6659 , H01L21/2253 , H01L29/665 , H01L29/7833
摘要： High-k dielectric spacer elements on the gate electrode of a field effects transistor in combination with an extension region that is formed by dopant diffusion from the high-k spacer elements into the underlying semiconductor region provides for an increased charge carrier density in the extension region. In this way, the limitation of the charge carrier density to approximately the solid solubility of dopants in the extension region may be overcome, thereby allowing extremely shallow extension regions without unduly compromising the transistor performance.
摘要翻译：场效应晶体管的栅极上的高k电介质隔离元件与由高k隔离元件掺入到下面的半导体区域中的掺杂剂扩散形成的延伸区组合提供了延伸区中增加的电荷载流子密度。以这种方式，可以克服电荷载流子密度近似于扩散区域中掺杂剂的固溶度的限制，从而允许非常浅的延伸区域而不会不利地损害晶体管的性能。

4. 发明授权

US06566718B2 Field effect transistor with an improved gate contact and method of fabricating the same 有权
公开(公告)号：US06566718B2
公开(公告)日：2003-05-20
申请号：US09848085
申请日：2001-05-03
申请人： Karsten Wieczorek , Rolf Stephan , Manfred Horstmann , Stephan Kruegel
发明人： Karsten Wieczorek , Rolf Stephan , Manfred Horstmann , Stephan Kruegel
IPC分类号： H01L2976
CPC分类号： H01L23/5222 , H01L21/76816 , H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： A field effect transistor comprises a gate electrode contact of a highly conductive material that contacts the gate electrode and extends in the transistor width dimension at least along a portion of the channel. Thus, the gate resistance and the gate signal propagation time for a voltage applied to the gate contact is significantly reduced even for devices with an extremely down scaled gate length. Moreover, a method for fabricating the above FET is disclosed.

5. 发明授权

US06798028B2 Field effect transistor with reduced gate delay and method of fabricating the same 有权
标题翻译：具有减小的栅极延迟的场效应晶体管及其制造方法
公开(公告)号：US06798028B2
公开(公告)日：2004-09-28
申请号：US09847622
申请日：2001-05-02
申请人： Manfred Horstmann , Rolf Stephan , Karsten Wieczorek , Stephan Kruegel
发明人： Manfred Horstmann , Rolf Stephan , Karsten Wieczorek , Stephan Kruegel
IPC分类号： H01L2976
CPC分类号： H01L21/28052 , H01L21/28114 , H01L29/42376 , H01L29/4933
摘要： A transistor formed on a substrate comprises a gate electrode having a lateral extension at the foot of the gate electrode that is less than the average lateral extension of the gate electrode. The increased cross-section of the gate electrode compared to the rectangular cross-sectional shape of a prior art device provides for a significantly reduced gate resistance while the effective gate length, i.e., the lateral extension of the gate electrode at its foot, may be scaled down to a size of 100 nm and beyond. Moreover, a method for forming the field effect transistor described above is disclosed.
摘要翻译：形成在基板上的晶体管包括栅电极，栅电极在栅极的脚处具有小于栅电极的平均横向延伸的横向延伸。与现有技术的器件的矩形横截面形状相比，栅电极的横截面增加提供了显着降低的栅极电阻，而有效栅极长度，即栅电极在其脚处的横向延伸可以是缩小到100nm以上的尺寸。此外，公开了一种用于形成上述场效应晶体管的方法。

6. 发明授权

US07419867B2 CMOS gate structure comprising predoped semiconductor gate material with improved uniformity of dopant distribution and method of forming the structure 失效
标题翻译： CMOS栅极结构包括具有改善的掺杂剂分布均匀性的预制半导体栅极材料和形成该结构的方法
公开(公告)号：US07419867B2
公开(公告)日：2008-09-02
申请号：US11154878
申请日：2005-06-16
申请人： Karsten Wieczorek , Manfred Horstmann , Thomas Feudel
发明人： Karsten Wieczorek , Manfred Horstmann , Thomas Feudel
IPC分类号： H01L21/8238
CPC分类号： H01L21/28052 , H01L21/823842 , H01L29/665 , H01L29/6659 , H01L29/7833
摘要： By predoping of a layer of deposited semiconductor gate material by incorporating dopants during the deposition process, a high uniformity of the dopant distribution may be achieved in the gate electrodes of CMOS devices subsequently formed in the layer of gate material. The improved uniformity of the dopant distribution results in reduced gate depletion and reduced threshold voltage shift in the transistors of the CMOS devices.
摘要翻译：通过在沉积工艺期间通过掺入掺杂剂预先淀积沉积的半导体栅极材料，可以在随后在栅极材料层中形成的CMOS器件的栅电极中实现掺杂物分布的高均匀性。掺杂剂分布的改进的均匀性导致CMOS器件的晶体管中栅极耗尽减少和阈值电压偏移降低。

7. 发明申请

US20060094183A1 CMOS gate structure comprising predoped semiconductor gate material with improved uniformity of dopant distribution and method of forming the structure 失效
标题翻译： CMOS栅极结构包括具有改善的掺杂剂分布均匀性的预制半导体栅极材料和形成该结构的方法
公开(公告)号：US20060094183A1
公开(公告)日：2006-05-04
申请号：US11154878
申请日：2005-06-16
申请人： Karsten Wieczorek , Manfred Horstmann , Thomas Feudel
发明人： Karsten Wieczorek , Manfred Horstmann , Thomas Feudel
IPC分类号： H01L21/8238
CPC分类号： H01L21/28052 , H01L21/823842 , H01L29/665 , H01L29/6659 , H01L29/7833
摘要： By predoping of a layer of deposited semiconductor gate material by incorporating dopants during the deposition process, a high uniformity of the dopant distribution may be achieved in the gate electrodes of CMOS devices subsequently formed in the layer of gate material. The improved uniformity of the dopant distribution results in reduced gate depletion and reduced threshold voltage shift in the transistors of the CMOS devices.
摘要翻译：通过在沉积工艺期间通过掺入掺杂剂预先淀积沉积的半导体栅极材料，可以在随后在栅极材料层中形成的CMOS器件的栅电极中实现掺杂物分布的高均匀性。掺杂剂分布的改进的均匀性导致CMOS器件的晶体管中栅极耗尽减少和阈值电压偏移降低。

8. 发明授权

US07955937B2 Method for manufacturing semiconductor device comprising SOI transistors and bulk transistors 有权
标题翻译：包括SOI晶体管和体晶体管的半导体器件的制造方法
公开(公告)号：US07955937B2
公开(公告)日：2011-06-07
申请号：US11560896
申请日：2006-11-17
申请人： Karsten Wieczorek , Manfred Horstmann , Thomas Feudel , Thomas Heller
发明人： Karsten Wieczorek , Manfred Horstmann , Thomas Feudel , Thomas Heller
IPC分类号： H01L21/331
CPC分类号： H01L21/823481 , H01L21/76243 , H01L21/823878 , H01L21/84 , H01L27/0922 , H01L27/1203 , H01L27/1207
摘要： By forming bulk-like transistors in sensitive RAM areas of otherwise SOI-based CMOS circuits, a significant savings in valuable chip area may be achieved since the RAM areas may be formed on the basis of a bulk transistor configuration, thereby eliminating hysteresis effects that may typically be taken into consideration by providing transistors of increased transistor width or by providing body ties. Hence, the benefit of high switching speed may be maintained in speed-critical circuitry, such as CPU cores, while at the same time the RAM circuit may be formed in a highly space-efficient manner.
摘要翻译：通过在其它基于SOI的CMOS电路的敏感RAM区域中形成块状晶体管，可以实现有价值的芯片面积的显着节省，因为可以基于体晶体管配置形成RAM区域，从而消除可能通常通过提供增加的晶体管宽度的晶体管或通过提供身体纽带来考虑。因此，高速切换速度的好处可以保持在诸如CPU内核之类的速度关键电路中，同时可以以高空间效率的方式形成RAM电路。

9. 发明申请

US20070228377A1 SEMICONDUCTOR DEVICE COMPRISING SOI TRANSISTORS AND BULK TRANSISTORS AND A METHOD OF FORMING THE SAME 有权
标题翻译：包含SOI晶体管和块晶体管的半导体器件及其形成方法
公开(公告)号：US20070228377A1
公开(公告)日：2007-10-04
申请号：US11560896
申请日：2006-11-17
申请人： Karsten Wieczorek , Manfred Horstmann , Thomas Feudel , Thomas Heller
发明人： Karsten Wieczorek , Manfred Horstmann , Thomas Feudel , Thomas Heller
IPC分类号： H01L29/76 , H01L21/84
CPC分类号： H01L21/823481 , H01L21/76243 , H01L21/823878 , H01L21/84 , H01L27/0922 , H01L27/1203 , H01L27/1207
摘要： By forming bulk-like transistors in sensitive RAM areas of otherwise SOI-based CMOS circuits, a significant savings in valuable chip area may be achieved since the RAM areas may be formed on the basis of a bulk transistor configuration, thereby eliminating hysteresis effects that may typically be taken into consideration by providing transistors of increased transistor width or by providing body ties. Hence, the benefit of high switching speed may be maintained in speed-critical circuitry, such as CPU cores, while at the same time the RAM circuit may be formed in a highly space-efficient manner.
摘要翻译：通过在其它基于SOI的CMOS电路的敏感RAM区域中形成块状晶体管，可以实现有价值的芯片面积的显着节省，因为可以基于体晶体管配置形成RAM区域，从而消除可能通常通过提供增加的晶体管宽度的晶体管或通过提供身体纽带来考虑。因此，高速切换速度的好处可以保持在诸如CPU内核之类的速度关键电路中，同时可以以高空间效率的方式形成RAM电路。

10. 发明授权

US06806153B2 Method of manufacturing a field effect transistor 有权
标题翻译：制造场效应晶体管的方法
公开(公告)号：US06806153B2
公开(公告)日：2004-10-19
申请号：US10462893
申请日：2003-06-17
申请人： Karsten Wieczorek , Manfred Horstmann , Thomas Feudel
发明人： Karsten Wieczorek , Manfred Horstmann , Thomas Feudel
IPC分类号： H01L21336
CPC分类号： H01L29/6659 , H01L21/2022 , H01L21/26506 , H01L21/26513
摘要： The present invention allows the manufacturing of field effect transistors with reduced thermal budget. A first amorphized region and a second amorphized region are formed in a substrate adjacent to the gate electrode by implanting ions of a non-doping element, the presence of which does not significantly alter the conductive properties of the substrate. The formation of the amorphized regions may be performed before or after the formation of a source region, a drain region, an extended source region and an extended drain region. The substrate is annealed to achieve solid phase epitaxial regrowth of the amorphized regions and to activate dopants in the source region, the drain region, the extended source region and the extended drain region.
摘要翻译：本发明允许制造具有降低的热预算的场效应晶体管。第一非晶化区域和第二非晶区域通过注入非掺杂元素的离子形成在与栅电极相邻的衬底中，其不存在不会显着地改变衬底的导电性能。非晶化区域的形成可以在形成源极区域，漏极区域，扩展源极区域和延伸的漏极区域之前或之后进行。将衬底退火以实现非晶化区域的固相外延再生长并激活源极区域，漏极区域，扩展源极区域和延伸漏极区域中的掺杂剂。

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