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1. 发明授权

US07801296B2 xDSL-line-interface-circuit 有权
标题翻译： xDSL线路接口电路
公开(公告)号：US07801296B2
公开(公告)日：2010-09-21
申请号：US11044644
申请日：2005-01-27
申请人： Karl Stefan Barkarö , Bo Bokinge , Jörg Hauptmann , Karl-Mikael Johanson , Lars Karlsson , Torbjörn Ivar Randahl
发明人： Karl Stefan Barkarö , Bo Bokinge , Jörg Hauptmann , Karl-Mikael Johanson , Lars Karlsson , Torbjörn Ivar Randahl
IPC分类号： H04M1/00 , H04M9/00
CPC分类号： H04M3/007 , H03F3/217 , H03F3/45475 , H03F2200/78 , H04L27/0002 , H04M3/005 , H04M2201/14
摘要： at least one self oscillating loop circuit which oscillates with a switching frequency (fs), wherein the self oscillating loop circuit (18, 19, 20) comprises an output driver (19) which is switched with said switching frequency and a loop filter (20) which feeds back an amplified loop signal output by said driver (19) to an input of said self oscillating loop and a trimming circuit (21) for trimming the switching frequency (fs) of said self oscillating loop circuit.
摘要翻译：至少一个以开关频率（fs）振荡的自振荡回路电路，其中所述自振荡回路电路（18,19,20）包括用所述开关频率切换的输出驱动器（19）和环路滤波器（20））将由所述驱动器（19）输出的放大环路信号反馈到所述自振荡环路的输入端，以及微调电路（21），用于修整所述自振荡环路电路的开关频率（fs）。

2. 发明授权

US06340945B1 Analog/digital converter 有权
标题翻译：模/数转换器
公开(公告)号：US06340945B1
公开(公告)日：2002-01-22
申请号：US09875971
申请日：2001-06-08
申请人： Jörg Hauptmann , Christian Schranz
发明人： Jörg Hauptmann , Christian Schranz
IPC分类号： H03M112
CPC分类号： H03M3/474
摘要： The present invention is related to an analog/digital converter which includes a multitude of integrating circuits, a 1 bit analog/digital converter and a 1 bit digital/analog converter. The multitude of analog integrating circuits are connected in series and the 1 bit digital/analog converter is connected downstream from the last analog integrating circuit of the series. An output signal of the 1 bit analog/digital converter is transmitted to the 1 bit digital/analog converter, and an output signal of the 1 bit digital/analog converter is subtracted from an input signal of each analog integrating circuit. A multitude of input signals is transmitted via a multiplexer to the first analog integrating circuit of the series-connected analog integrating circuits. Each analog integrating circuit includes a multitude of capacitors which correspond to the multitude of input signals, whereby a capacitor of the multitude of capacitors can be switched each time between an output and an input of the analog integrating circuit. The output signal of the 1 bit digital/analog converter is delayed according to the multitude of input signals.
摘要翻译：本发明涉及一种包括多个积分电路，1位模拟/数字转换器和1位数字/模拟转换器的模拟/数字转换器。多个模拟积分电路串联连接，1位数/模转换器连接在该系列的最后一个模拟积分电路的下游。 1位模拟/数字转换器的输出信号被传送到1位数/模转换器，并从每个模拟积分电路的输入信号中减去1位数/模转换器的输出信号。多个输入信号通过多路复用器传输到串联模拟积分电路的第一模拟积分电路。每个模拟积分电路包括对应于多个输入信号的多个电容器，由此可以每次在模拟积分电路的输出和输入之间切换多个电容器的电容器。 1位数/模转换器的输出信号根据输入信号的大小而被延迟。

3. 发明授权

US07023985B1 Circuit for electronically generating a call impedance 有权
标题翻译：用于电子产生呼叫阻抗的电路
公开(公告)号：US07023985B1
公开(公告)日：2006-04-04
申请号：US09806479
申请日：1999-10-21
申请人： Jörg Hauptmann , Alexander Kahl
发明人： Jörg Hauptmann , Alexander Kahl
IPC分类号： H04M1/76
CPC分类号： H04M1/76 , H04M19/04
摘要： The present invention relates to a circuit for electronically generating a call impedance in telephone terminals, comprising a call alternating voltage that may be tapped between a first and a second input terminal. The inventive circuit has a regulating device with a programmable digital filter for regulating impedance, wherein the transmission function of the regulating device can be adjusted by programming the filter coefficients of the digital filter. The inventive regulating device makes it possible to adapt the call impedance to different country-specific requirements. To this end, the regulating device has a programmable digital filter that may be embodied as a digital signal processor. In an especially preferred embodiment, the digital filter is implemented in the form of a program in the digital signal processor.
摘要翻译：本发明涉及一种用于在电话终端中电子地产生呼叫阻抗的电路，包括可在第一和第二输入端之间被抽头的呼叫交流电压。本发明的电路具有调节装置，其具有用于调节阻抗的可编程数字滤波器，其中可通过对数字滤波器的滤波器系数进行编程来调节调节装置的传输功能。本发明的调节装置使呼叫阻抗适应不同的国家特定要求成为可能。为此，调节装置具有可被实现为数字信号处理器的可编程数字滤波器。在特别优选的实施例中，数字滤波器以数字信号处理器中的程序的形式实现。

4. 发明授权

US06879273B2 Oversampling in analog/digital and digital/analog converters 有权
标题翻译：模拟/数字和数字/模拟转换器中的过采样
公开(公告)号：US06879273B2
公开(公告)日：2005-04-12
申请号：US10669280
申请日：2003-09-23
申请人： Andreas Wiesbauer , Martin Clara , Thomas Pötscher , Hubert Weinberger , Jörg Hauptmann , Thomas Magesacher
发明人： Andreas Wiesbauer , Martin Clara , Thomas Pötscher , Hubert Weinberger , Jörg Hauptmann , Thomas Magesacher
IPC分类号： H03M1/00 , H03M1/20 , H03M1/66 , H03M3/00 , H04B14/04 , H04B14/06
CPC分类号： H03M1/66 , H03M1/201 , H03M3/33 , H03M3/458 , H03M3/50
摘要： The invention creates a method and a device for digitally transmitting analog signals, in which oversampling is performed in analog/digital and digital/analog converters. In this arrangement, a digital/analog conversion is performed which, in particular, is suitable for VDSL systems. A transmitted digital transmission signal (110) is supplied to a mixing unit (201) and in the mixing unit (201), a receive noise signal (211) applied to a receive noise source terminal (209) is superimposed on the digital transmission signal (110). An interpolation filter unit (203), in combination with a subsequent noise shaping device (205), provides an increase in the frequency bandwidth, resulting in suitable oversampling.
摘要翻译：本发明创建了一种用于数字传输模拟信号的方法和装置，其中在模拟/数字和数字/模拟转换器中执行过采样。在这种布置中，执行数字/模拟转换，其特别适用于VDSL系统。传输的数字传输信号（110）被提供给混合单元（201）并且在混合单元（201）中，施加到接收噪声源终端（209）的接收噪声信号（211）被叠加在数字传输信号（110）。与随后的噪声整形装置（205）组合的内插滤波器单元（203）提供频率带宽的增加，从而导致合适的过采样。

5. 发明授权

US07012979B2 Tone signal detection circuit for detecting tone signals 有权
标题翻译：用于检测音调信号的音频信号检测电路
公开(公告)号：US07012979B2
公开(公告)日：2006-03-14
申请号：US09942518
申请日：2001-08-29
申请人： Jörg Hauptmann , Thomas Pötscher , Michael Staber , Dietmar Straeussnigg , Hubert Weinberger
发明人： Jörg Hauptmann , Thomas Pötscher , Michael Staber , Dietmar Straeussnigg , Hubert Weinberger
IPC分类号： H04L7/00
CPC分类号： H04L27/1563 , H04L2027/0083
摘要： Tone signal detection circuit for a receiving circuit for detecting at least one tone signal of predetermined tone signal frequency (fE) which is contained in a received analog input signal, comprising a reference signal generator (41) for generating an analog converter reference signal which consists of a reference DC (VrefDC) and a periodic reference AC (VrefAC) having a variable fundamental frequency (fG), which is superimposed on the reference DC, an analog/digital converter (11) for converting the analog input signal into a digital data stream in dependence on the analog converter reference signal (Vref); and comprising a digital control circuit (20) which adjusts the variable fundamental frequency (fG) of the reference signal (Vref) generated by the reference signal generator (42) in accordance with the predetermined tone signal frequencies (fG) of the tone signals to be detected and evaluates the digital data stream output by the digital analog/digital converter (11) for detecting a data pattern corresponding to the tone signal.
摘要翻译：一种用于检测包含在接收的模拟输入信号中的预定音调信号频率（f SUB）的至少一个音调信号的接收电路的音频信号检测电路，包括：参考信号发生器（41），用于产生一个模拟转换器参考信号，该参考信号由具有可变基频（f SUB）的参考DC（V SUB refDC）和周期性参考AC（V SUB REFAC ），其叠加在参考DC上;模拟/数字转换器（11），用于根据模拟转换器参考信号（V SUB ref ）; 并且包括数字控制电路（20），其调整由参考信号发生器（42）产生的参考信号（V SUB ref）的可变基频（f SUB）根据要检测的音调信号的预定音调信号频率（f SUB）来评估由数字模拟/数字转换器（11）输出的数字数据流，用于检测对应于音调信号。

6. 发明授权

US06594360B1 Circuit configuration for two-wire/four-wire conversion 有权
标题翻译：二线/四线转换电路配置
公开(公告)号：US06594360B1
公开(公告)日：2003-07-15
申请号：US09357249
申请日：1999-07-20
申请人： Lajos Gazsi , Jörg Hauptmann
发明人： Lajos Gazsi , Jörg Hauptmann
IPC分类号： H04M100
CPC分类号： H04L27/0002 , H04B3/23
摘要： The invention relates to a circuit configuration for two-wire/four-wire conversion. The circuit configuration has a receiver which is coupled on an input side to a digital two-wire reception path via which its receives a digital signal. A signal-processor is connected downstream of the receiver and emits a first and second signal. An echo-canceling device receives the first signal and emits a third signal. A digital-to-analog converter is provided which receives the second signal and emits a fourth signal. A hybrid circuit is coupled to an analog four-wire transmission-reception path, receives the fourth signal, and emits a fifth signal. An analog-to-digital converter receives the fifth signal and emits a sixth signal. A transmitter receives the sixth signal and is coupled on an output side to a digital two-wire transmission path and emits a digital transmitted signal to the latter. In the invention, the digital-to-analog converter has a sigma-delta modulator.
摘要翻译：本发明涉及一种用于双线/四线转换的电路结构。该电路配置具有一个接收机，该接收机在输入侧耦合到数字双线接收路径，通过该接收路径接收数字信号。信号处理器连接在接收器的下游并发射第一和第二信号。回波消除装置接收第一信号并发出第三信号。提供了数模转换器，其接收第二信号并发出第四信号。混合电路耦合到模拟四线发送接收路径，接收第四信号，并发出第五信号。模拟 - 数字转换器接收第五信号并发出第六信号。发射机接收第六信号，并且在输出侧耦合到数字双线传输路径，并向后者发射数字发射信号。在本发明中，数模转换器具有Σ-Δ调制器。

7. 发明授权

US06831581B1 Digital-to-analog converter arrangement with an array of unary digital-to-analog converting elements usable for different signal types 有权
标题翻译：具有可用于不同信号类型的一元数模转换元件阵列的数模转换器装置
公开(公告)号：US06831581B1
公开(公告)日：2004-12-14
申请号：US10445255
申请日：2003-05-23
申请人： Martin Clara , Jörg Hauptmann
发明人： Martin Clara , Jörg Hauptmann
IPC分类号： H03M166
CPC分类号： H03M3/392 , H03M1/066 , H03M3/424 , H03M3/502
摘要： A digital-to-analog converter arrangement able to process input signals with different signal bandwidth is provided. The arrangement comprises a first input terminal for receiving a first digital input signal, a second input terminal for receiving a second digital input signal and switching means being coupled to the first and second input terminals and being adapted to select between the first and second digital input signals so as to output an intermediate digital signal corresponding to the selected one of the first and second digital input signals. The intermediate digital signal is received by an array of unary digital-to-analog converting elements, each unary digital-to-analog converting element being adapted so that, as an analog output signal, a sum signal of output signals of the unary digital-to-analog converting elements is output.
摘要翻译：提供了能够处理具有不同信号带宽的输入信号的数模转换器装置。该装置包括用于接收第一数字输入信号的第一输入端，用于接收第二数字输入信号的第二输入端和耦合到第一和第二输入端的开关装置，并适于在第一和第二数字输入之间进行选择信号，以输出对应于所选择的第一和第二数字输入信号之一的中间数字信号。中间数字信号由一对数字 - 模拟转换元件阵列接收，每个一元的数/模转换元件适于使得作为模拟输出信号的一元数字 - 模拟转换元件的输出信号的和信号，输出模拟转换元件。

8. 发明授权

US06570512B1 Circuit configuration for quantization of digital signals and for filtering quantization noise 有权
标题翻译：用于数字信号量化和滤波量化噪声的电路配置
公开(公告)号：US06570512B1
公开(公告)日：2003-05-27
申请号：US09856382
申请日：2001-08-21
申请人： Jörg Hauptmann , Peter Pessl , Dietmar Sträussnigg
发明人： Jörg Hauptmann , Peter Pessl , Dietmar Sträussnigg
IPC分类号： H03M300
CPC分类号： H03M7/3022
摘要： The invention relates to a circuit configuration for quantization of digital signals and for filtering quantization noise. Said circuit configuration comprises a multitude of digital control loops connected in series and having quantizers. The digital signals having a word length of m-bits are fed to a first control loop in the series. The quantization error signal of each quantizer is filtered and fed back to the corresponding digital control loop. It is then fed to a downstream digital control loop. The quantized output signal of the first digital control loop is adapted to a third word length of u-bits which is smaller than the first word length. Except for the quantized output signal of the first digital control loop, the quantized output signals of the digital control loops of the series are respectively filtered by a digital filter. In an adder, said quantized output signals are then added to the first quantized output signal of the first digital control loop of the series to prevent quantization errors. The output signal of the adder has a second word length of n-bits and represents the quantized output signal of the circuit configuration.
摘要翻译：本发明涉及数字信号量化和滤波量化噪声的电路结构。所述电路配置包括串联连接并具有量化器的多个数字控制回路。具有m位的字长的数字信号被馈送到该系列中的第一控制环路。对每个量化器的量化误差信号进行滤波并反馈到相应的数字控制回路。然后将其馈送到下游数字控制回路。第一数字控制环路的量化输出信号适应于小于第一字长的u位的第三字长。除了第一数字控制回路的量化输出信号之外，系列的数字控制回路的量化输出信号分别被数字滤波器滤波。在加法器中，然后将所述量化的输出信号加到串联的第一数字控制环路的第一量化输出信号中，以防止量化误差。加法器的输出信号具有n位的第二字长，表示电路结构的量化输出信号。

9. 发明授权

US06496128B2 Sigma-delta analog-to-digital converter array 有权
公开(公告)号：US06496128B2
公开(公告)日：2002-12-17
申请号：US10001022
申请日：2001-11-02
申请人： Andreas Wiesbauer , Hubert Weinberger , Martin Clara , Jörg Hauptmann
发明人： Andreas Wiesbauer , Hubert Weinberger , Martin Clara , Jörg Hauptmann
IPC分类号： H03M300
CPC分类号： H03M3/416
摘要： A sigma-delta analog-to-digital converter array including two cascaded sigma-delta modulators, the two sigma-delta modulators being multi-bit sigma-delta modulators. The sigma-delta analog-to-digital converter array is preferably a third order device and supplies a digital output signal corresponding to a sigma-delta converter with 7-bit quantization. To this end, a second order sigma-delta modulator with 3-bit quantization and a first order sigma-delta modulator with 5-bit quantization may be used.

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