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    • 1. 发明授权
    • Switchable operational amplifier circuit
    • 可切换运算放大器电路
    • US07183850B2
    • 2007-02-27
    • US10488814
    • 2002-08-26
    • Peter Pessl
    • Peter Pessl
    • H03F3/45
    • H03F3/45659H03F1/0277H03F3/45192H03F3/4565H03F2200/331H03F2203/45396H03F2203/45504H03F2203/45726
    • An amplifier circuit in particular configured as an operational transconductance amplifier has signal paths switched in parallel to the individual transversal branches or signal paths, which can be alternatively activated and deactivated with the aid of suitable switching means (1, 2), so that without essentially changing the dynamic characteristics of the amplifier circuit switching over is possible by activating these parallel-switched additional signal paths or the transistors (M3.2–M12.2) contained in these from normal operation (A) into an operation (B) with, for example, a higher clock frequency in comparison to normal operation or for operating with higher loads in comparison to normal operation.
    • 特别地配置为运算跨导放大器的放大器电路具有与各个横向分支或信号路径平行切换的信号路径,其可以借助于合适的开关装置(1,2)被选择性地激活和去激活,使得基本上 通过将这些并行切换附加信号路径或这些中包含的晶体管(M 3.2 -M 12.2)从正常操作(A)激活到操作(B)中,例如可以改变放大器电路切换的动态特性 与正常操作相比较较高的时钟频率,或者与正常操作相比较较高的负载运行。
    • 4. 发明授权
    • Tuning circuit for a filter
    • 滤波器调谐电路
    • US07002404B2
    • 2006-02-21
    • US10773710
    • 2004-02-06
    • Richard GagglManfred NoppPeter PesslChristian SchranzDietmar Straussnigg
    • Richard GagglManfred NoppPeter PesslChristian SchranzDietmar Straussnigg
    • H03K5/00
    • H03H11/1291H03H19/008H03H2210/021H03H2210/043
    • The invention relates to a tuning circuit for tuning a filter stage, which has an RC element (1) with an RC time constant (τ), with the RC time constant (τ) being the product of the resistance of a resistor (R1) in the RC element (1) and the capacitance of a capacitor (C1), which is connected in series with the resistor (R1), in the RC element (1), having a comparator (10) for comparison of the voltage which is produced at the potential node (4) between the resistor (R1) and the capacitor (C1), with a reference ground voltage; and having a controller (15) which varies the charge on the capacitor (C1) in the RC element (1) until the comparator (10) indicates that the voltage which is produced at the potential node (4) is equal to the reference ground voltage, with the controller (15) switching a capacitor array (26) as a function of the charge variation time, which capacitor array (26) is connected in parallel with the capacitor (C1) in the RC element (1), in order to compensate for any discrepancy between the RC time constant (τ) of the RC element (1) and a nominal value.
    • 本发明涉及一种用于调谐滤波器级的调谐电路,其具有RC时间常数(τ)的RC元件(1),其中RC时间常数(τ)是电阻器(R 1 )和RC元件(1)中与电阻器(R 1)串联连接的电容器(C1)的电容,具有比较器(10),用于比较 在电阻器(R 1)和电容器(C 1)之间的电位节点(4)产生的具有参考接地电压的电压; 并且具有改变RC元件(1)中的电容器(C1)上的电荷的控制器(15),直到比较器(10)指示在电势节点(4)处产生的电压等于参考 接地电压,控制器(15)根据电荷变化时间切换电容器阵列(26),电容器阵列(26)与RC元件(1)中的电容器(C 1)并联连接, 以便补偿RC元件(1)的RC时间常数(τ)与标称值之间的任何差异。
    • 5. 发明授权
    • Programmable echo cancellation filter
    • 可编程回声消除滤波器
    • US06845252B2
    • 2005-01-18
    • US09975768
    • 2001-10-11
    • Antonio DigiandomenicoPeter PesslChristian Fleischhacker
    • Antonio DigiandomenicoPeter PesslChristian Fleischhacker
    • H04B3/23H04M1/00H04B3/20
    • H04B3/23
    • Programmable echo cancellation filter for echo signal cancellation for a transceiver having a signal input (13) for receiving the transmission signal emitted by the transceiver (1), an input resistor (36) connected to the signal input (13), an operational amplifier (39), whose signal input (38) is connected to the input resistor (36) and whose signal output (41) is connected to an output resistor (43), a first programmable resistor circuit (48), which is provided between the signal output (41) of the operational amplifier (39) and the signal input (38) of the operational amplifier, a second programmable resistor circuit (51), which is provided between the output resistor (43) and a signal output (15) of the echo cancellation filter (14), a third programmable resistor circuit (55) which is provided between the first programmable resistor circuit (48) and the signal output (15) of the echo cancellation filter (14), the programmable resistor circuits (48, 51, 55) each having a plurality of resistors (65) which are terminated in parallel and are connected to a first terminal (68) of an associated controllable switch (66), the controllable switches (66) having a second terminal (69) connected to a virtual reference voltage terminal with a very low voltage swing.
    • 用于具有用于接收由收发器(1)发射的传输信号的信号输入(13)的收发器的用于回波信号消除的可编程回声消除滤波器,连接到信号输入端(13)的输入电阻器(36),运算放大器 39),其信号输入(38)连接到输入电阻器(36),并且其信号输出端(41)连接到输出电阻器(43);第一可编程电阻器电路(48) 输出(41)和运算放大器的信号输入(38);第二可编程电阻电路(51),设置在输出电阻器(43)和信号输出端(15)之间,输出电阻器 回波消除滤波器(14),设置在第一可编程电阻电路(48)和回波消除滤波器(14)的信号输出端(15)之间的第三可编程电阻电路(55),可编程电阻电路(48) ,51,55),每个具有多个o f电阻器(65),其并联端接并连接到相关联的可控开关(66)的第一端子(68),所述可控开关(66)具有连接到虚拟参考电压端子的第二端子(69) 一个非常低的电压摆幅。
    • 6. 发明授权
    • Circuit configuration for quantization of digital signals and for filtering quantization noise
    • 用于数字信号量化和滤波量化噪声的电路配置
    • US06570512B1
    • 2003-05-27
    • US09856382
    • 2001-08-21
    • Jörg HauptmannPeter PesslDietmar Sträussnigg
    • Jörg HauptmannPeter PesslDietmar Sträussnigg
    • H03M300
    • H03M7/3022
    • The invention relates to a circuit configuration for quantization of digital signals and for filtering quantization noise. Said circuit configuration comprises a multitude of digital control loops connected in series and having quantizers. The digital signals having a word length of m-bits are fed to a first control loop in the series. The quantization error signal of each quantizer is filtered and fed back to the corresponding digital control loop. It is then fed to a downstream digital control loop. The quantized output signal of the first digital control loop is adapted to a third word length of u-bits which is smaller than the first word length. Except for the quantized output signal of the first digital control loop, the quantized output signals of the digital control loops of the series are respectively filtered by a digital filter. In an adder, said quantized output signals are then added to the first quantized output signal of the first digital control loop of the series to prevent quantization errors. The output signal of the adder has a second word length of n-bits and represents the quantized output signal of the circuit configuration.
    • 本发明涉及数字信号量化和滤波量化噪声的电路结构。 所述电路配置包括串联连接并具有量化器的多个数字控制回路。 具有m位的字长的数字信号被馈送到该系列中的第一控制环路。 对每个量化器的量化误差信号进行滤波并反馈到相应的数字控制回路。 然后将其馈送到下游数字控制回路。 第一数字控制环路的量化输出信号适应于小于第一字长的u位的第三字长。 除了第一数字控制回路的量化输出信号之外,系列的数字控制回路的量化输出信号分别被数字滤波器滤波。 在加法器中,然后将所述量化的输出信号加到串联的第一数字控制环路的第一量化输出信号中,以防止量化误差。 加法器的输出信号具有n位的第二字长,表示电路结构的量化输出信号。