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1. 发明授权

US09715413B2 Execution state analysis for assigning tasks to streaming multiprocessors 有权
公开(公告)号：US09715413B2
公开(公告)日：2017-07-25
申请号：US13353155
申请日：2012-01-18
申请人： Karim M. Abdalla , Lacky V. Shah , Jerome F. Duluk, Jr. , Timothy John Purcell , Tanmoy Mandal , Gentaro Hirota
发明人： Karim M. Abdalla , Lacky V. Shah , Jerome F. Duluk, Jr. , Timothy John Purcell , Tanmoy Mandal , Gentaro Hirota
IPC分类号： G06F9/46 , G06F13/00 , G06F9/50
CPC分类号： G06F9/505 , G06F2209/503
摘要： One embodiment of the present invention sets forth a technique for selecting a first processor included in a plurality of processors to receive work related to a compute task. The technique involves analyzing state data of each processor in the plurality of processors to identify one or more processors that have already been assigned one compute task and are eligible to receive work related to the one compute task, receiving, from each of the one or more processors identified as eligible, an availability value that indicates the capacity of the processor to receive new work, selecting a first processor to receive work related to the one compute task based on the availability values received from the one or more processors, and issuing, to the first processor via a cooperative thread array (CTA), the work related to the one compute task.

2. 发明授权

US09069609B2 Scheduling and execution of compute tasks 有权
标题翻译：计划任务的计划和执行
公开(公告)号：US09069609B2
公开(公告)日：2015-06-30
申请号：US13353150
申请日：2012-01-18
申请人： Karim M. Abdalla , Lacky V. Shah , Jerome F. Duluk, Jr. , Timothy John Purcell , Tanmoy Mandal , Gentaro Hirota
发明人： Karim M. Abdalla , Lacky V. Shah , Jerome F. Duluk, Jr. , Timothy John Purcell , Tanmoy Mandal , Gentaro Hirota
IPC分类号： G06F9/46 , G06F9/48 , G06F9/50
CPC分类号： G06F9/4881 , G06F9/4806 , G06F9/50 , G06F2209/483
摘要： One embodiment of the present invention sets forth a technique for assigning a compute task to a first processor included in a plurality of processors. The technique involves analyzing each compute task in a plurality of compute tasks to identify one or more compute tasks that are eligible for assignment to the first processor, where each compute task is listed in a first table and is associated with a priority value and an allocation order that indicates relative time at which the compute task was added to the first table. The technique further involves selecting a first task compute from the identified one or more compute tasks based on at least one of the priority value and the allocation order, and assigning the first compute task to the first processor for execution.
摘要翻译：本发明的一个实施例提出了一种用于将计算任务分配给包括在多个处理器中的第一处理器的技术。该技术涉及分析多个计算任务中的每个计算任务以识别符合分配给第一处理器的一个或多个计算任务，其中每个计算任务在第一表中列出并且与优先级值和分配指示将计算任务添加到第一个表的相对时间的顺序。该技术还包括基于优先级值和分配顺序中的至少一个从所识别的一个或多个计算任务中选择第一任务计算，以及将第一计算任务分配给第一处理器以供执行。

3. 发明授权

US09507638B2 Compute work distribution reference counters 有权
标题翻译：计算工作分配参考计数器
公开(公告)号：US09507638B2
公开(公告)日：2016-11-29
申请号：US13291369
申请日：2011-11-08
申请人： Philip Alexander Cuadra , Karim M. Abdalla , Jerome F. Duluk, Jr. , Luke Durant , Gerald F. Luiz , Timothy John Purcell , Lacky V. Shah
发明人： Philip Alexander Cuadra , Karim M. Abdalla , Jerome F. Duluk, Jr. , Luke Durant , Gerald F. Luiz , Timothy John Purcell , Lacky V. Shah
IPC分类号： G06F9/455 , G06F9/50
CPC分类号： G06F9/5022
摘要： One embodiment of the present invention sets forth a technique for managing the allocation and release of resources during multi-threaded program execution. Programmable reference counters are initialized to values that limit the amount of resources for allocation to tasks that share the same reference counter. Resource parameters are specified for each task to define the amount of resources allocated for consumption by each array of execution threads that is launched to execute the task. The resource parameters also specify the behavior of the array for acquiring and releasing resources. Finally, during execution of each thread in the array, an exit instruction may be configured to override the release of the resources that were allocated to the array. The resources may then be retained for use by a child task that is generated during execution of a thread.
摘要翻译：本发明的一个实施例提出了一种用于在多线程程序执行期间管理资源的分配和释放的技术。可编程参考计数器被初始化为限制用于分配给共享相同引用计数器的任务的资源量的值。为每个任务指定资源参数，以定义为执行任务启动的每个执行线程数组分配的消耗资源量。资源参数还指定数组用于获取和释放资源的行为。最后，在执行阵列中的每个线程时，可以将退出指令配置为覆盖分配给阵列的资源的释放。然后可以保留资源以供执行线程期间生成的子任务使用。

4. 发明授权

US08984183B2 Signaling, ordering, and execution of dynamically generated tasks in a processing system 有权
标题翻译：在处理系统中信令，排序和执行动态生成的任务
公开(公告)号：US08984183B2
公开(公告)日：2015-03-17
申请号：US13329169
申请日：2011-12-16
申请人： Timothy John Purcell , Lacky V. Shah , Jerome F. Duluk, Jr. , Sean J. Treichler , Karim M. Abdalla , Philip Alexander Cuadra , Brian Pharris
发明人： Timothy John Purcell , Lacky V. Shah , Jerome F. Duluk, Jr. , Sean J. Treichler , Karim M. Abdalla , Philip Alexander Cuadra , Brian Pharris
IPC分类号： G06F3/00 , G06F9/46 , G06F9/48
CPC分类号： G06F9/4843
摘要： One embodiment of the present invention sets forth a technique for enabling the insertion of generated tasks into a scheduling pipeline of a multiple processor system allows a compute task that is being executed to dynamically generate a dynamic task and notify a scheduling unit of the multiple processor system without intervention by a CPU. A reflected notification signal is generated in response to a write request when data for the dynamic task is written to a queue. Additional reflected notification signals are generated for other events that occur during execution of a compute task, e.g., to invalidate cache entries storing data for the compute task and to enable scheduling of another compute task.
摘要翻译：本发明的一个实施例提出了一种用于使所生成的任务能够插入到多处理器系统的调度流水线中的技术，允许正在执行的计算任务动态生成动态任务并通知多处理器系统的调度单元没有CPU的干预。当将动态任务的数据写入队列时，响应于写入请求产生反映的通知信号。为在执行计算任务期间发生的其他事件生成附加的反映的通知信号，例如，使存储用于计算任务的数据的高速缓存条目无效并启用其他计算任务的调度。

5. 发明授权

US09442759B2 Concurrent execution of independent streams in multi-channel time slice groups 有权
标题翻译：在多通道时间片组中并发执行独立流
公开(公告)号：US09442759B2
公开(公告)日：2016-09-13
申请号：US13316334
申请日：2011-12-09
申请人： Samuel H. Duncan , Lacky V. Shah , Sean J. Treichler , Daniel Elliot Wexler , Jerome F. Duluk, Jr. , Philip Browning Johnson , Jonathon Stuart Ramsay Evans
发明人： Samuel H. Duncan , Lacky V. Shah , Sean J. Treichler , Daniel Elliot Wexler , Jerome F. Duluk, Jr. , Philip Browning Johnson , Jonathon Stuart Ramsay Evans
IPC分类号： G06F9/46 , G06F13/00 , G06F9/48 , G06F9/38
CPC分类号： G06F9/4881 , G06F9/3851 , G06F9/461
摘要： A time slice group (TSG) is a grouping of different streams of work (referred to herein as “channels”) that share the same context information. The set of channels belonging to a TSG are processed in a pre-determined order. However, when a channel stalls while processing, the next channel with independent work can be switched to fully load the parallel processing unit. Importantly, because each channel in the TSG shares the same context information, a context switch operation is not needed when the processing of a particular channel in the TSG stops and the processing of a next channel in the TSG begins. Therefore, multiple independent streams of work are allowed to run concurrently within a single context increasing utilization of parallel processing units.
摘要翻译：时间片组（TSG）是共享相同上下文信息的不同工作流（本文称为“信道”）的分组。属于TSG的信道集合以预定的顺序被处理。然而，当通道在处理过程中停顿时，可以切换具有独立工作的下一个通道来完全加载并行处理单元。重要的是，由于TSG中的每个信道共享相同的上下文信息，当TSG中的特定信道的处理停止并且TSG中的下一个信道的处理开始时，不需要上下文切换操作。因此，允许多个独立的工作流在单个上下文中同时运行，增加并行处理单元的利用率。

6. 发明授权

US10795722B2 Compute task state encapsulation 有权
公开(公告)号：US10795722B2
公开(公告)日：2020-10-06
申请号：US13292951
申请日：2011-11-09
申请人： Jerome F. Duluk, Jr. , Lacky V. Shah , Sean J. Treichler
发明人： Jerome F. Duluk, Jr. , Lacky V. Shah , Sean J. Treichler
IPC分类号： G06F9/48 , G06F9/46 , G06F9/50
摘要： One embodiment of the present invention sets forth a technique for encapsulating compute task state that enables out-of-order scheduling and execution of the compute tasks. The scheduling circuitry organizes the compute tasks into groups based on priority levels. The compute tasks may then be selected for execution using different scheduling schemes. Each group is maintained as a linked list of pointers to compute tasks that are encoded as task metadata (TMD) stored in memory. A TMD encapsulates the state and parameters needed to initialize, schedule, and execute a compute task.

7. 发明授权

US09513975B2 Technique for computational nested parallelism 有权
标题翻译：计算嵌套并行性技术
公开(公告)号：US09513975B2
公开(公告)日：2016-12-06
申请号：US13462649
申请日：2012-05-02
申请人： Stephen Jones , Philip Alexander Cuadra , Daniel Elliot Wexler , Ignacio Llamas , Lacky V. Shah , Jerome F. Duluk, Jr. , Christopher Lamb
发明人： Stephen Jones , Philip Alexander Cuadra , Daniel Elliot Wexler , Ignacio Llamas , Lacky V. Shah , Jerome F. Duluk, Jr. , Christopher Lamb
IPC分类号： G06F9/46 , G06F9/52 , G06T1/20
CPC分类号： G06F9/5027 , G06F9/522 , G06F2209/483 , G06T1/20
摘要： One embodiment of the present invention sets forth a technique for performing nested kernel execution within a parallel processing subsystem. The technique involves enabling a parent thread to launch a nested child grid on the parallel processing subsystem, and enabling the parent thread to perform a thread synchronization barrier on the child grid for proper execution semantics between the parent thread and the child grid. This technique advantageously enables the parallel processing subsystem to perform a richer set of programming constructs, such as conditionally executed and nested operations and externally defined library functions without the additional complexity of CPU involvement.
摘要翻译：本发明的一个实施例提出了一种用于在并行处理子系统内执行嵌套的内核执行的技术。该技术涉及使父线程启动并行处理子系统上的嵌套子网格，并使父线程能够在子网格上执行线程同步屏障，以在父线程和子网格之间实现正确的执行语义。该技术有利地使得并行处理子系统能够执行更丰富的编程结构集合，诸如条件执行和嵌套操作以及外部定义的库函数，而不会增加CPU参与的复杂性。

8. 发明授权

US09710306B2 Methods and apparatus for auto-throttling encapsulated compute tasks 有权
公开(公告)号：US09710306B2
公开(公告)日：2017-07-18
申请号：US13442730
申请日：2012-04-09
申请人： Jerome F. Duluk, Jr. , Jesse David Hall , Philip Alexander Cuadra , Karim M. Abdalla
发明人： Jerome F. Duluk, Jr. , Jesse David Hall , Philip Alexander Cuadra , Karim M. Abdalla
IPC分类号： G06F9/46 , G06F9/48 , G06F9/50
CPC分类号： G06F9/4881 , G06F9/5016 , G06F2209/483
摘要： Systems and methods for auto-throttling encapsulated compute tasks. A device driver may configure a parallel processor to execute compute tasks in a number of discrete throttled modes. The device driver may also allocate memory to a plurality of different processing units in a non-throttled mode. The device driver may also allocate memory to a subset of the plurality of processing units in each of the throttling modes. Data structures defined for each task include a flag that instructs the processing unit whether the task may be executed in the non-throttled mode or in the throttled mode. A work distribution unit monitors each of the tasks scheduled to run on the plurality of processing units and determines whether the processor should be configured to run in the throttled mode or in the non-throttled mode.

9. 发明授权

US09965321B2 Error checking in out-of-order task scheduling 有权
公开(公告)号：US09965321B2
公开(公告)日：2018-05-08
申请号：US13316344
申请日：2011-12-09
申请人： Jerome F. Duluk, Jr. , Timothy John Purcell , Jesse David Hall , Philip Alexander Cuadra
发明人： Jerome F. Duluk, Jr. , Timothy John Purcell , Jesse David Hall , Philip Alexander Cuadra
IPC分类号： G06F9/46 , G06F9/48
CPC分类号： G06F9/4843
摘要： One embodiment of the present invention sets forth a technique for error-checking a compute task. The technique involves receiving a pointer to a compute task, storing the pointer in a scheduling queue, determining that the compute task should be executed, retrieving the pointer from the scheduling queue, determining via an error-check procedure that the compute task is eligible for execution, and executing the compute task.

10. 发明授权

US08619087B2 Inter-shader attribute buffer optimization 有权
标题翻译：内部着色器属性缓冲区优化
公开(公告)号：US08619087B2
公开(公告)日：2013-12-31
申请号：US12895579
申请日：2010-09-30
申请人： Jerome F. Duluk, Jr. , Gernot Schaufler
发明人： Jerome F. Duluk, Jr. , Gernot Schaufler
IPC分类号： G06T1/20
CPC分类号： G06T1/20 , G06F9/3851 , G06F9/3887 , G06T15/005 , G06T2210/04 , G06T2210/52
摘要： One embodiment of the present invention sets forth a technique for reducing the amount of memory required to store vertex data processed within a processing pipeline that includes a plurality of shading engines. The method includes determining a first active shading engine and a second active shading engine included within the processing pipeline, wherein the second active shading engine receives vertex data output by the first active shading engine. An output map is received and indicates one or more attributes that are included in the vertex data and output by the first active shading engine. An input map is received and indicates one or more attributes that are included in the vertex data and received by the second active shading engine from the first active shading engine. Then, a buffer map is generated based on the input map, the output map, and a pre-defined set of rules that includes rule data associated with both the first shading engine and the second shading engine, wherein the buffer map indicates one or more attributes that are included in the vertex data and stored in a memory that is accessible by both the first active shading engine and the second active shading engine.
摘要翻译：本发明的一个实施例提出了一种用于减少存储在包括多个着色引擎的处理流水线中处理的顶点数据所需的存储量的技术。该方法包括确定包括在处理流水线内的第一主动着色引擎和第二主动着色引擎，其中第二主动着色引擎接收由第一主动着色引擎输出的顶点数据。接收输出图，并指示包含在顶点数据中并由第一主动着色引擎输出的一个或多个属性。接收输入图，并且指示包括在顶点数据中并由第二主动着色引擎从第一主动着色引擎接收的一个或多个属性。然后，基于输入映射，输出映射和包括与第一着色引擎和第二着色引擎相关联的规则数据的预定义的规则集合生成缓冲器映射，其中缓冲器映射指示一个或多个包括在顶点数据中并存储在可由第一主动着色引擎和第二主动着色引擎访问的存储器中的属性。

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