专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08309447B2 Method for integrating multiple threshold voltage devices for CMOS 有权
标题翻译：用于集成多个CMOS阈值电压器件的方法
公开(公告)号：US08309447B2
公开(公告)日：2012-11-13
申请号：US12855273
申请日：2010-08-12
申请人： Kangguo Cheng , Bruce B. Doris , Lisa F. Edge , Balasubramanian S. Haran , Hemanth Jagannathan , Ali Khakifirooz , Vamsi K. Paruchuri
发明人： Kangguo Cheng , Bruce B. Doris , Lisa F. Edge , Balasubramanian S. Haran , Hemanth Jagannathan , Ali Khakifirooz , Vamsi K. Paruchuri
IPC分类号： H01L21/3205 , H01L21/4763
CPC分类号： H01L21/823857 , H01L21/823462 , H01L21/823481 , H01L21/823878
摘要： A method to achieve multiple threshold voltage (Vt) devices on the same semiconductor chip is disclosed. The method provides different threshold voltage devices using threshold voltage adjusting materials and a subsequent drive in anneal instead of directly doping the channel. As such, the method of the present disclosure avoids short channel penalties. Additionally, no ground plane/back gates are utilized in the present application thereby the method of the present disclosure can be easily integrated into current complementary metal oxide semiconductor (CMOS) processing technology.
摘要翻译：公开了在同一半导体芯片上实现多个阈值电压（Vt）器件的方法。该方法提供使用阈值电压调节材料的不同阈值电压器件，以及随后的退火驱动而不是直接掺杂通道。因此，本公开的方法避免了短信道惩罚。此外，在本申请中没有使用接地平面/后门，因此本公开的方法可以容易地集成到电流互补金属氧化物半导体（CMOS）处理技术中。

2. 发明申请

US20120040522A1 METHOD FOR INTEGRATING MULTIPLE THRESHOLD VOLTAGE DEVICES FOR CMOS 有权
标题翻译：用于集成用于CMOS的多个阈值电压器件的方法
公开(公告)号：US20120040522A1
公开(公告)日：2012-02-16
申请号：US12855273
申请日：2010-08-12
申请人： Kangguo Cheng , Bruce B. Doris , Lisa F. Edge , Balasubramanian S. Haran , Hemanth Jagannathan , Ali Khakifirooz , Vamsi K. Paruchuri
发明人： Kangguo Cheng , Bruce B. Doris , Lisa F. Edge , Balasubramanian S. Haran , Hemanth Jagannathan , Ali Khakifirooz , Vamsi K. Paruchuri
IPC分类号： H01L21/8238
CPC分类号： H01L21/823857 , H01L21/823462 , H01L21/823481 , H01L21/823878
摘要： A method to achieve multiple threshold voltage (Vt) devices on the same semiconductor chip is disclosed. The method provides different threshold voltage devices using threshold voltage adjusting materials and a subsequent drive in anneal instead of directly doping the channel. As such, the method of the present disclosure avoids short channel penalties. Additionally, no ground plane/back gates are utilized in the present application thereby the method of the present disclosure can be easily integrated into current complementary metal oxide semiconductor (CMOS) processing technology.
摘要翻译：公开了在同一半导体芯片上实现多个阈值电压（Vt）器件的方法。该方法提供使用阈值电压调节材料的不同阈值电压器件，以及随后的退火驱动而不是直接掺杂通道。因此，本公开的方法避免了短信道惩罚。此外，在本申请中没有使用接地平面/后门，因此本公开的方法可以容易地集成到电流互补金属氧化物半导体（CMOS）处理技术中。

3. 发明申请

US20130005156A1 STRUCTURE AND METHOD TO OBTAIN EOT SCALED DIELECTRIC STACKS 有权
公开(公告)号：US20130005156A1
公开(公告)日：2013-01-03
申请号：US13602118
申请日：2012-09-01
申请人： Hemanth Jagannathan , Takashi Ando , Lisa F. Edge , Sufi Zafar , Changhwan Choi , Paul C. Jamison , Vamsi K. Paruchuri , Vijay Narayanan
发明人： Hemanth Jagannathan , Takashi Ando , Lisa F. Edge , Sufi Zafar , Changhwan Choi , Paul C. Jamison , Vamsi K. Paruchuri , Vijay Narayanan
IPC分类号： H01L21/324
CPC分类号： H01L29/42364 , H01L21/225 , H01L21/28088 , H01L21/28176 , H01L21/28185 , H01L21/324 , H01L21/477 , H01L21/823462 , H01L21/823835 , H01L21/823842 , H01L21/823857 , H01L29/1054 , H01L29/401 , H01L29/4958 , H01L29/4966 , H01L29/51 , H01L29/513 , H01L29/517
摘要： Equivalent oxide thickness (EOT) scaled high k/metal gate stacks are provided in which the capacitance bottleneck of the interfacial layer is substantially eliminated, with minimal compromise on the mobility of carriers in the channel of the device. In one embodiment, the aforementioned EOT scaled high k/metal gate stacks are achieved by increasing the dielectric constant of the interfacial layer to a value that is greater than the originally formed interfacial layer, i.e., the interfacial layer prior to diffusion of a high k material dopant element therein. In another embodiment, the aforementioned scaled high k/metal gate stacks are achieved by eliminating the interfacial layer from the structure. In yet another embodiment, the aforementioned high k/metal gate stacks are achieved by both increasing the dielectric constant of the interfacial layer and reducing/eliminating the interfacial layer.

4. 发明授权

US09059314B2 Structure and method to obtain EOT scaled dielectric stacks 有权
标题翻译：获得EOT缩放电介质叠层的结构和方法
公开(公告)号：US09059314B2
公开(公告)日：2015-06-16
申请号：US13602118
申请日：2012-09-01
申请人： Hemanth Jagannathan , Takashi Ando , Lisa F. Edge , Sufi Zafar , Changhwan Choi , Paul C. Jamison , Vamsi K. Paruchuri , Vijay Narayanan
发明人： Hemanth Jagannathan , Takashi Ando , Lisa F. Edge , Sufi Zafar , Changhwan Choi , Paul C. Jamison , Vamsi K. Paruchuri , Vijay Narayanan
IPC分类号： H01L21/00 , H01L21/8238 , H01L21/28 , H01L29/49 , H01L29/51
CPC分类号： H01L29/42364 , H01L21/225 , H01L21/28088 , H01L21/28176 , H01L21/28185 , H01L21/324 , H01L21/477 , H01L21/823462 , H01L21/823835 , H01L21/823842 , H01L21/823857 , H01L29/1054 , H01L29/401 , H01L29/4958 , H01L29/4966 , H01L29/51 , H01L29/513 , H01L29/517
摘要： Equivalent oxide thickness (EOT) scaled high k/metal gate stacks are provided in which the capacitance bottleneck of the interfacial layer is substantially eliminated, with minimal compromise on the mobility of carriers in the channel of the device. In one embodiment, the aforementioned EOT scaled high k/metal gate stacks are achieved by increasing the dielectric constant of the interfacial layer to a value that is greater than the originally formed interfacial layer, i.e., the interfacial layer prior to diffusion of a high k material dopant element therein. In another embodiment, the aforementioned scaled high k/metal gate stacks are achieved by eliminating the interfacial layer from the structure. In yet another embodiment, the aforementioned high k/metal gate stacks are achieved by both increasing the dielectric constant of the interfacial layer and reducing/eliminating the interfacial layer.
摘要翻译：提供了相当于氧化物厚度（EOT）的高k /金属栅极叠层，其中基本上消除了界面层的电容瓶颈，对器件沟道中载流子的迁移率的影响最小。在一个实施例中，通过将界面层的介电常数提高到大于原始形成的界面层的值，即高k扩散之前的界面层，可实现上述EOT缩放的高k /金属栅极堆叠材料掺杂元素。在另一个实施例中，通过从结构中消除界面层来实现上述缩放的高k /金属栅极堆叠。在另一个实施方案中，上述高k /金属栅极堆叠是通过增加界面层的介电常数和减少/消除界面层来实现的。

5. 发明授权

US08304836B2 Structure and method to obtain EOT scaled dielectric stacks 有权
标题翻译：获得EOT缩放电介质堆叠的结构和方法
公开(公告)号：US08304836B2
公开(公告)日：2012-11-06
申请号：US12620234
申请日：2009-11-17
申请人： Hemanth Jagannathan , Takashi Ando , Lisa F. Edge , Sufi Zafar , Changhwan Choi , Paul C. Jamison , Vamsi K. Paruchuri , Vijay Narayanan
发明人： Hemanth Jagannathan , Takashi Ando , Lisa F. Edge , Sufi Zafar , Changhwan Choi , Paul C. Jamison , Vamsi K. Paruchuri , Vijay Narayanan
IPC分类号： H01L21/70
CPC分类号： H01L29/42364 , H01L21/225 , H01L21/28088 , H01L21/28176 , H01L21/28185 , H01L21/324 , H01L21/477 , H01L21/823462 , H01L21/823835 , H01L21/823842 , H01L21/823857 , H01L29/1054 , H01L29/401 , H01L29/4958 , H01L29/4966 , H01L29/51 , H01L29/513 , H01L29/517
摘要： Equivalent oxide thickness (EOT) scaled high k/metal gate stacks are provided in which the capacitance bottleneck of the interfacial layer is substantially eliminated, with minimal compromise on the mobility of carriers in the channel of the device. In one embodiment, the aforementioned EOT scaled high k/metal gate stacks are achieved by increasing the dielectric constant of the interfacial layer to a value that is greater than the originally formed interfacial layer, i.e., the interfacial layer prior to diffusion of a high k material dopant element therein. In another embodiment, the aforementioned scaled high k/metal gate stacks are achieved by eliminating the interfacial layer from the structure. In yet another embodiment, the aforementioned high k/metal gate stacks are achieved by both increasing the dielectric constant of the interfacial layer and reducing/eliminating the interfacial layer.
摘要翻译：提供了相当于氧化物厚度（EOT）的高k /金属栅极叠层，其中基本上消除了界面层的电容瓶颈，对器件沟道中载流子的迁移率的影响最小。在一个实施例中，通过将界面层的介电常数提高到大于原始形成的界面层的值，即高k扩散之前的界面层，可实现上述EOT缩放的高k /金属栅极堆叠材料掺杂元素。在另一个实施例中，通过从结构中消除界面层来实现上述缩放的高k /金属栅极堆叠。在另一个实施方案中，上述高k /金属栅极堆叠是通过增加界面层的介电常数和减少/消除界面层来实现的。

6. 发明申请

US20110115027A1 STRUCTURE AND METHOD TO OBTAIN EOT SCALED DIELECTRIC STACKS 有权
标题翻译：结构和方法来获取电子尺寸的电介质堆叠
公开(公告)号：US20110115027A1
公开(公告)日：2011-05-19
申请号：US12620234
申请日：2009-11-17
申请人： Hemanth Jagannathan , Takashi Ando , Lisa F. Edge , Sufi Zafar , Changhwan Choi , Paul C. Jamison , Vamsi K. Paruchuri , Vijay Narayanan
发明人： Hemanth Jagannathan , Takashi Ando , Lisa F. Edge , Sufi Zafar , Changhwan Choi , Paul C. Jamison , Vamsi K. Paruchuri , Vijay Narayanan
IPC分类号： H01L27/092 , H01L29/78 , H01L21/8238 , H01L21/263
CPC分类号： H01L29/42364 , H01L21/225 , H01L21/28088 , H01L21/28176 , H01L21/28185 , H01L21/324 , H01L21/477 , H01L21/823462 , H01L21/823835 , H01L21/823842 , H01L21/823857 , H01L29/1054 , H01L29/401 , H01L29/4958 , H01L29/4966 , H01L29/51 , H01L29/513 , H01L29/517
摘要： Equivalent oxide thickness (EOT) scaled high k/metal gate stacks are provided in which the capacitance bottleneck of the interfacial layer is substantially eliminated, with minimal compromise on the mobility of carriers in the channel of the device. In one embodiment, the aforementioned EOT scaled high k/metal gate stacks are achieved by increasing the dielectric constant of the interfacial layer to a value that is greater than the originally formed interfacial layer, i.e., the interfacial layer prior to diffusion of a high k material dopant element therein. In another embodiment, the aforementioned scaled high k/metal gate stacks are achieved by eliminating the interfacial layer from the structure. In yet another embodiment, the aforementioned high k/metal gate stacks are achieved by both increasing the dielectric constant of the interfacial layer and reducing/eliminating the interfacial layer.
摘要翻译：提供了相当于氧化物厚度（EOT）的高k /金属栅极叠层，其中基本上消除了界面层的电容瓶颈，对器件沟道中载流子的迁移率的影响最小。在一个实施例中，通过将界面层的介电常数提高到大于原始形成的界面层的值，即高k扩散之前的界面层，可实现上述EOT缩放的高k /金属栅极堆叠材料掺杂元素。在另一个实施例中，通过从结构中消除界面层来实现上述缩放的高k /金属栅极堆叠。在另一个实施方案中，上述高k /金属栅极堆叠是通过增加界面层的介电常数和减少/消除界面层来实现的。

7. 发明授权

US09202698B2 Replacement gate electrode with multi-thickness conductive metallic nitride layers 有权
标题翻译：具有多层导电金属氮化物层的替代栅电极
公开(公告)号：US09202698B2
公开(公告)日：2015-12-01
申请号：US13406784
申请日：2012-02-28
申请人： Hemanth Jagannathan , Vamsi K. Paruchuri
发明人： Hemanth Jagannathan , Vamsi K. Paruchuri
IPC分类号： H01L29/78 , H01L21/28 , H01L21/8238 , H01L27/092 , H01L23/485 , H01L29/51 , H01L21/84
CPC分类号： H01L21/28229 , H01L21/823842 , H01L21/823871 , H01L21/845 , H01L23/485 , H01L27/092 , H01L29/518 , H01L2924/0002 , H01L2924/00
摘要： Gate electrodes having different work functions can be provided by providing conductive metallic nitride layers having different thicknesses in a replacement gate scheme. Upon removal of disposable gate structures and formation of a gate dielectric layer, at least one incremental thickness conductive metallic nitride layer is added within some gate cavities, while not being added in some other gate cavities. A minimum thickness conductive metallic nitride layer is subsequently added as a contiguous layer. Conductive metallic nitride layers thus formed have different thicknesses across different gate cavities. A gate fill conductive material layer is deposited, and planarization is performed to provide multiple gate electrode having different conductive metallic nitride layer thicknesses. The different thicknesses of the conductive metallic nitride layers can provide different work functions having a range of about 400 mV.
摘要翻译：可以通过在替代栅极方案中提供具有不同厚度的导电金属氮化物层来提供具有不同功函数的栅电极。在去除一次性栅极结构和形成栅极电介质层时，至少一个增量厚度的导电金属氮化物层被添加到一些栅极空腔内，而不被添加到一些其它栅极腔中。随后添加最小厚度的导电金属氮化物层作为连续层。如此形成的导电金属氮化物层在不同的栅腔上具有不同的厚度。沉积栅极填充导电材料层，并执行平面化以提供具有不同导电金属氮化物层厚度的多个栅电极。导电金属氮化物层的不同厚度可以提供具有约400mV范围的不同功函数。

8. 发明申请

US20130217220A1 REPLACEMENT GATE ELECTRODE WITH A TANTALUM ALLOY METAL LAYER 审中-公开
公开(公告)号：US20130217220A1
公开(公告)日：2013-08-22
申请号：US13608310
申请日：2012-09-10
申请人： Hemanth Jagannathan , Vamsi K. Paruchuri
发明人： Hemanth Jagannathan , Vamsi K. Paruchuri
IPC分类号： H01L21/283
CPC分类号： H01L21/823821 , H01L21/823842 , H01L21/84 , H01L27/0924 , H01L27/1203 , H01L29/4966 , H01L29/517 , H01L29/518 , H01L29/66545
摘要： A tantalum alloy layer is employed as a work function metal for field effect transistors. The tantalum alloy layer can be selected from TaC, TaAl, and TaAlC. When used in combination with a metallic nitride layer, the tantalum alloy layer and the metallic nitride layer provides two work function values that differ by 300 mV˜500 mV, thereby enabling multiple field effect transistors having different threshold voltages. The tantalum alloy layer can be in contact with a first gate dielectric in a first gate, and the metallic nitride layer can be in contact with a second gate dielectric having a same composition and thickness as the first gate dielectric and located in a second gate.

9. 发明授权

US08741757B2 Replacement gate electrode with multi-thickness conductive metallic nitride layers 有权
标题翻译：具有多层导电金属氮化物层的替代栅电极
公开(公告)号：US08741757B2
公开(公告)日：2014-06-03
申请号：US13606702
申请日：2012-09-07
申请人： Hemanth Jagannathan , Vamsi K. Paruchuri
发明人： Hemanth Jagannathan , Vamsi K. Paruchuri
IPC分类号： H01L21/336
CPC分类号： H01L21/28229 , H01L21/823842 , H01L21/823871 , H01L21/845 , H01L23/485 , H01L27/092 , H01L29/518 , H01L2924/0002 , H01L2924/00
摘要： Gate electrodes having different work functions can be provided by providing conductive metallic nitride layers having different thicknesses in a replacement gate scheme. Upon removal of disposable gate structures and formation of a gate dielectric layer, at least one incremental thickness conductive metallic nitride layer is added within some gate cavities, while not being added in some other gate cavities. A minimum thickness conductive metallic nitride layer is subsequently added as a contiguous layer. Conductive metallic nitride layers thus formed have different thicknesses across different gate cavities. A gate fill conductive material layer is deposited, and planarization is performed to provide multiple gate electrode having different conductive metallic nitride layer thicknesses. The different thicknesses of the conductive metallic nitride layers can provide different work functions having a range of about 400 mV.
摘要翻译：可以通过在替代栅极方案中提供具有不同厚度的导电金属氮化物层来提供具有不同功函数的栅电极。在去除一次性栅极结构和形成栅极电介质层时，至少一个增量厚度的导电金属氮化物层被添加到一些栅极空腔内，而不被添加到一些其它栅极腔中。随后添加最小厚度的导电金属氮化物层作为连续层。如此形成的导电金属氮化物层在不同的栅腔上具有不同的厚度。沉积栅极填充导电材料层，并执行平面化以提供具有不同导电金属氮化物层厚度的多个栅电极。导电金属氮化物层的不同厚度可以提供具有约400mV范围的不同功函数。

10. 发明申请

US20100320545A1 PLANAR AND NON-PLANAR CMOS DEVICES WITH MULTIPLE TUNED THRESHOLD VOLTAGES 有权
标题翻译：具有多个调谐阈值电压的平面和非平面CMOS器件
公开(公告)号：US20100320545A1
公开(公告)日：2010-12-23
申请号：US12487202
申请日：2009-06-18
申请人： Hemanth Jagannathan , Vijay Narayanan , Vamsi K. Paruchuri
发明人： Hemanth Jagannathan , Vijay Narayanan , Vamsi K. Paruchuri
IPC分类号： H01L27/088 , H01L21/8236
CPC分类号： H01L21/823462 , H01L21/823431 , H01L21/823821 , H01L21/823857 , H01L29/51 , H01L29/513 , H01L29/517 , H01L29/785
摘要： A semiconductor structure is provided that includes a first device region including a first threshold voltage adjusting layer located atop a semiconductor substrate, a gate dielectric located atop the first threshold voltage adjusting layer, and a gate conductor located atop the gate dielectric. The structure further includes a second device region including a gate dielectric located atop the semiconductor substrate, and a gate conductor located atop the gate dielectric; and a third device region including a gate dielectric located atop the semiconductor substrate, a second threshold voltage adjusting layer located atop the gate dielectric, and a gate conductor located atop the second threshold voltage adjusting layer. In the inventive structure the first threshold voltage adjusting layer includes one of an nFET threshold voltage adjusting material or a pFET threshold voltage adjusting material and the second threshold voltage adjusting layer is the other of the nFET threshold voltage adjusting material or the pFET threshold voltage adjusting material.
摘要翻译：提供一种半导体结构，其包括第一器件区域，该第一器件区域包括位于半导体衬底顶部的第一阈值电压调节层，位于第一阈值电压调整层顶部的栅极电介质和位于栅极电介质顶部的栅极导体。该结构还包括第二器件区域，其包括位于半导体衬底顶部的栅极电介质和位于栅极电介质顶部的栅极导体; 以及第三器件区域，包括位于半导体衬底顶部的栅极电介质，位于栅极电介质顶部的第二阈值电压调节层和位于第二阈值电压调节层顶部的栅极导体。在本发明的结构中，第一阈值电压调节层包括nFET阈值电压调节材料或pFET阈值电压调节材料之一，第二阈值电压调节层是nFET阈值电压调节材料或pFET阈值电压调节材料中的另一个。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式