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1. 发明申请

US20130146959A1 Method and Structure For Forming On-Chip High Quality Capacitors With ETSOI Transistors 有权
标题翻译：用ETSOI晶体管形成片上高品质电容器的方法和结构
公开(公告)号：US20130146959A1
公开(公告)日：2013-06-13
申请号：US13316635
申请日：2011-12-12
申请人： Kangguo Cheng , Bruce Doris , Ali Khakifirooz , Ghavam Shahidi
发明人： Kangguo Cheng , Bruce Doris , Ali Khakifirooz , Ghavam Shahidi
IPC分类号： H01L27/06 , H01L21/02
CPC分类号： H01L27/1203 , H01L27/0629 , H01L27/105 , H01L27/10805 , H01L28/40 , H01L29/66181 , H01L29/94
摘要： An ETSOI transistor and a capacitor are formed respectively in a transistor and capacitor region thereof by etching through an ETSOI and thin BOX layers in a replacement gate HK/MG flow. The capacitor formation is compatible with an ETSOI replacement gate CMOS flow. A low resistance capacitor electrode makes it possible to obtain a high quality capacitor or varactor. The lack of topography during dummy gate patterning are achieved by lithography in combination accompanied with appropriate etch.
摘要翻译：通过在替换栅极HK / MG流中通过ETSOI和薄BOX层蚀刻，分别在其晶体管和电容器区域中形成ETSOI晶体管和电容器。电容器形成与ETSOI替代栅极CMOS流相兼容。低电阻电容器电极可以获得高质量的电容器或变容二极管。虚拟栅极图案化期间缺乏形貌通过光刻结合并伴随着适当的蚀刻来实现。

2. 发明申请

US20110254090A1 RAISED SOURCE/DRAIN STRUCTURE FOR ENHANCED STRAIN COUPLING FROM STRESS LINER 有权
标题翻译：从应力衬里增强应变耦合的提高源/排水结构
公开(公告)号：US20110254090A1
公开(公告)日：2011-10-20
申请号：US12760250
申请日：2010-04-14
申请人： Kangguo Cheng , Bruce Doris , Ali Khakifirooz , Pranita Kulkarni , Ghavam Shahidi
发明人： Kangguo Cheng , Bruce Doris , Ali Khakifirooz , Pranita Kulkarni , Ghavam Shahidi
IPC分类号： H01L29/06 , H01L21/762
CPC分类号： H01L29/78654 , H01L21/76283 , H01L29/66772 , H01L29/78618
摘要： A transistor is provided that includes a buried oxide layer above a substrate. A silicon layer is above the buried oxide layer. A gate stack is on the silicon layer, the gate stack including a high-k oxide layer on the silicon layer and a metal gate on the high-k oxide layer. A nitride liner is adjacent to the gate stack. An oxide liner is adjacent to the nitride liner. A set of faceted raised source/drain regions having a part including a portion of the silicon layer. The set of faceted raised source/drain regions also include a first faceted side portion and a second faceted side portion.
摘要翻译：提供一种晶体管，其包括衬底上方的掩埋氧化物层。硅层在掩埋氧化物层之上。栅极堆叠在硅层上，栅极堆叠包括硅层上的高k氧化物层和高k氧化物层上的金属栅极。氮化物衬垫与栅堆叠相邻。氧化物衬垫与氮化物衬垫相邻。一组具有包括硅层的一部分的部分的凸起的源/漏区。所述一组切面隆起的源极/漏极区域还包括第一分面侧部分和第二分面侧部分。

3. 发明授权

US08338260B2 Raised source/drain structure for enhanced strain coupling from stress liner 有权
标题翻译：用于增强应力衬垫的应变耦合的源/漏结构
公开(公告)号：US08338260B2
公开(公告)日：2012-12-25
申请号：US12760250
申请日：2010-04-14
申请人： Kangguo Cheng , Bruce Doris , Ali Khakifirooz , Pranita Kulkarni , Ghavam Shahidi
发明人： Kangguo Cheng , Bruce Doris , Ali Khakifirooz , Pranita Kulkarni , Ghavam Shahidi
IPC分类号： H01L21/336
CPC分类号： H01L29/78654 , H01L21/76283 , H01L29/66772 , H01L29/78618
摘要： A transistor is provided that includes a buried oxide layer above a substrate. A silicon layer is above the buried oxide layer. A gate stack is on the silicon layer, the gate stack including a high-k oxide layer on the silicon layer and a metal gate on the high-k oxide layer. A nitride liner is adjacent to the gate stack. An oxide liner is adjacent to the nitride liner. A set of faceted raised source/drain regions having a part including a portion of the silicon layer. The set of faceted raised source/drain regions also include a first faceted side portion and a second faceted side portion.
摘要翻译：提供一种晶体管，其包括衬底上方的掩埋氧化物层。硅层在掩埋氧化物层之上。栅极堆叠在硅层上，栅极堆叠包括硅层上的高k氧化物层和高k氧化物层上的金属栅极。氮化物衬垫与栅堆叠相邻。氧化物衬垫与氮化物衬垫相邻。一组具有包括硅层的一部分的部分的凸起的源/漏区。所述一组切面隆起的源极/漏极区域还包括第一分面侧部分和第二分面侧部分。

4. 发明授权

US08890245B2 Raised source/drain structure for enhanced strain coupling from stress liner 有权
标题翻译：用于增强应力衬垫的应变耦合的源/漏结构
公开(公告)号：US08890245B2
公开(公告)日：2014-11-18
申请号：US13570833
申请日：2012-08-09
申请人： Kangguo Cheng , Bruce Doris , Ali Khakifirooz , Pranita Kulkarni , Ghavam Shahidi
发明人： Kangguo Cheng , Bruce Doris , Ali Khakifirooz , Pranita Kulkarni , Ghavam Shahidi
IPC分类号： H01L29/78 , H01L29/786 , H01L29/66 , H01L21/762
CPC分类号： H01L29/78654 , H01L21/76283 , H01L29/66772 , H01L29/78618
摘要： A transistor is provided that includes a buried oxide layer above a substrate. A silicon layer is above the buried oxide layer. A gate stack is on the silicon layer, the gate stack including a high-k oxide layer on the silicon layer and a metal gate on the high-k oxide layer. A nitride liner is adjacent to the gate stack. An oxide liner is adjacent to the nitride liner. A set of faceted raised source/drain regions having a part including a portion of the silicon layer. The set of faceted raised source/drain regions also include a first faceted side portion and a second faceted side portion.
摘要翻译：提供一种晶体管，其包括衬底上方的掩埋氧化物层。硅层在掩埋氧化物层之上。栅极堆叠在硅层上，栅极堆叠包括硅层上的高k氧化物层和高k氧化物层上的金属栅极。氮化物衬垫与栅堆叠相邻。氧化物衬垫与氮化物衬垫相邻。一组具有包括硅层的一部分的部分的凸起的源/漏区。所述一组切面隆起的源极/漏极区域还包括第一分面侧部分和第二分面侧部分。

5. 发明授权

US08853038B2 Raised source/drain structure for enhanced strain coupling from stress liner 有权
标题翻译：用于增强应力衬垫的应变耦合的源/漏结构
公开(公告)号：US08853038B2
公开(公告)日：2014-10-07
申请号：US13614572
申请日：2012-09-13
申请人： Kangguo Cheng , Bruce Doris , Ali Khakifirooz , Pranita Kulkarni , Ghavam Shahidi
发明人： Kangguo Cheng , Bruce Doris , Ali Khakifirooz , Pranita Kulkarni , Ghavam Shahidi
IPC分类号： H01L21/336 , H01L29/66 , H01L29/786 , H01L21/762
CPC分类号： H01L29/78654 , H01L21/76283 , H01L29/66772 , H01L29/78618
摘要： A gate stack is formed on a silicon layer that is above a buried oxide layer. The gate stack comprises a high-k oxide layer on the silicon layer and a metal gate on the high-k oxide layer. A first nitride layer is formed on the silicon layer and the gate stack. An oxide layer is formed on the first nitride layer. A second nitride layer is formed on the oxide layer. The first nitride layer and the oxide layer are etched so as to form a nitride liner and an oxide liner adjacent to the gate stack. The second nitride layer is etched so as to form a first nitride spacer adjacent to the oxide liner. A faceted raised source/drain region is epitaxially formed adjacent to the nitride liner, the oxide liner, and first nitride spacer. Ions are implanted into the faceted raised source/drain region using the first nitride spacer.
摘要翻译：栅极堆叠形成在掩埋氧化物层上方的硅层上。栅极堆叠包括在硅层上的高k氧化物层和在高k氧化物层上的金属栅极。在硅层和栅叠层上形成第一氮化物层。在第一氮化物层上形成氧化物层。在氧化物层上形成第二氮化物层。蚀刻第一氮化物层和氧化物层，以便形成氮化物衬垫和邻近栅叠层的氧化物衬垫。蚀刻第二氮化物层以形成邻近氧化物衬垫的第一氮化物间隔物。与氮化物衬垫，氧化物衬垫和第一氮化物间隔物相邻地外延形成刻面隆起的源极/漏极区。使用第一氮化物间隔物将离子植入到刻面隆起的源极/漏极区域中。

6. 发明授权

US08455308B2 Fully-depleted SON 失效
标题翻译：完全耗尽的SON
公开(公告)号：US08455308B2
公开(公告)日：2013-06-04
申请号：US13048977
申请日：2011-03-16
申请人： Kangguo Cheng , Bruce Doris , Pranita Kulkarni , Ghavam Shahidi
发明人： Kangguo Cheng , Bruce Doris , Pranita Kulkarni , Ghavam Shahidi
IPC分类号： H01L21/00 , H01L21/76
CPC分类号： H01L29/786 , H01L29/66772 , H01L29/78654 , H01L29/78696
摘要： A semiconductor device and a method of fabricating a semiconductor device. The semiconductor device includes a semiconductor substrate, an insulating layer, a first semiconductor layer, a dielectric layer, a second semiconductor layer, a source and drain junction, a gate, and a spacer. The method includes the steps of forming a semiconductor substrate, forming a shallow trench isolation layer, growing a first epitaxial layer, growing a second epitaxial layer, forming a gate, forming a spacer, performing a reactive ion etching, removing a portion of the first epitaxial layer, filling the void with a dielectric, etching back a portion of the dielectric, growing a silicon layer, implanting a source and drain junction, and forming an extension.
摘要翻译：半导体器件和半导体器件的制造方法。半导体器件包括半导体衬底，绝缘层，第一半导体层，电介质层，第二半导体层，源极和漏极结，栅极和间隔物。该方法包括以下步骤：形成半导体衬底，形成浅沟槽隔离层，生长第一外延层，生长第二外延层，形成栅极，形成间隔物，执行反应离子蚀刻，去除第一外延层，用电介质填充空隙，蚀刻电介质的一部分，生长硅层，注入源极和漏极结，以及形成延伸。

7. 发明申请

US20120235238A1 FULLY-DEPLETED SON 失效
标题翻译：充分的SON
公开(公告)号：US20120235238A1
公开(公告)日：2012-09-20
申请号：US13048977
申请日：2011-03-16
申请人： Kangguo Cheng , Bruce Doris , Pranita Kulkarni , Ghavam Shahidi
发明人： Kangguo Cheng , Bruce Doris , Pranita Kulkarni , Ghavam Shahidi
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L29/786 , H01L29/66772 , H01L29/78654 , H01L29/78696
摘要： A semiconductor device and a method of fabricating a semiconductor device. The semiconductor device includes a semiconductor substrate, an insulating layer, a first semiconductor layer, a dielectric layer, a second semiconductor layer, a source and drain junction, a gate, and a spacer. The method includes the steps of forming a semiconductor substrate, forming a shallow trench isolation layer, growing a first epitaxial layer, growing a second epitaxial layer, forming a gate, forming a spacer, performing a reactive ion etching, removing a portion of the first epitaxial layer, filling the void with a dielectric, etching back a portion of the dielectric, growing a silicon layer, implanting a source and drain junction, and forming an extension.
摘要翻译：半导体器件和半导体器件的制造方法。半导体器件包括半导体衬底，绝缘层，第一半导体层，电介质层，第二半导体层，源极和漏极结，栅极和间隔物。该方法包括以下步骤：形成半导体衬底，形成浅沟槽隔离层，生长第一外延层，生长第二外延层，形成栅极，形成间隔物，执行反应离子蚀刻，去除第一外延层，用电介质填充空隙，蚀刻电介质的一部分，生长硅层，注入源极和漏极结，以及形成延伸。

8. 发明申请

US20110316083A1 FET with Self-Aligned Back Gate 有权
标题翻译：具有自对准后门的FET
公开(公告)号：US20110316083A1
公开(公告)日：2011-12-29
申请号：US12823798
申请日：2010-06-25
申请人： Kangguo Cheng , Bruce Doris , Ali Khakifirooz , Pranita Kulkarni
发明人： Kangguo Cheng , Bruce Doris , Ali Khakifirooz , Pranita Kulkarni
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66545 , H01L29/78648
摘要： A back-gated field effect transistor (FET) includes a substrate, the substrate comprising top semiconductor layer on top of a buried dielectric layer on top of a bottom semiconductor layer; a front gate located on the top semiconductor layer; a channel region located in the top semiconductor layer under the front gate; a source region located in the top semiconductor layer on a side of the channel region, and a drain region located in the top semiconductor layer on the side of the channel region opposite the source regions; and a back gate located in the bottom semiconductor layer, the back gate configured such that the back gate abuts the buried dielectric layer underneath the channel region, and is separated from the buried dielectric layer by a separation distance underneath the source region and the drain region.
摘要翻译：背栅式场效应晶体管（FET）包括衬底，该衬底包括位于底部半导体层顶部的掩埋电介质层顶部的顶部半导体层; 位于顶部半导体层上的前门; 位于前门下的顶部半导体层中的沟道区; 位于沟道区一侧的顶部半导体层中的源极区域和位于与源极区域相反的沟道区域侧的顶部半导体层中的漏极区域; 以及位于底部半导体层中的背栅，后栅配置成使得后栅极邻接沟道区下方的掩埋介电层，并且在源极区和漏极区之下与掩埋介电层分离距离。

9. 发明授权

US08652898B2 Integrated circuit with a thin body field effect transistor and capacitor 失效
标题翻译：具有薄体场效应晶体管和电容器的集成电路
公开(公告)号：US08652898B2
公开(公告)日：2014-02-18
申请号：US13614908
申请日：2012-09-13
申请人： Kangguo Cheng , Bruce Doris , Ali Khakifirooz , Ghavam G. Shahidi
发明人： Kangguo Cheng , Bruce Doris , Ali Khakifirooz , Ghavam G. Shahidi
IPC分类号： H01L21/77
CPC分类号： H01L21/84 , H01L21/32053 , H01L21/823814 , H01L27/0629 , H01L27/1203 , H01L29/41783
摘要： A transistor region of a first semiconductor layer and a capacitor region in the first semiconductor layer are isolated. A dummy gate structure is formed on the first semiconductor layer in the transistor region. A second semiconductor layer is formed on the first semiconductor layer. First and second portions of the second semiconductor layer are located in the transistor region, and a third portion of the second semiconductor layer is located in the capacitor region. First, second, and third silicide regions are formed on the first, second, and third portions of the second semiconductor layer, respectively. After forming a dielectric layer, the dummy gate structure is removed forming a first cavity. At least a portion of the dielectric layer located above the third silicide region is removed forming a second cavity. A gate dielectric is formed in the first cavity and a capacitor dielectric in the second cavity.
摘要翻译：隔离第一半导体层中的第一半导体层和电容器区域的晶体管区域。在晶体管区域的第一半导体层上形成虚拟栅极结构。在第一半导体层上形成第二半导体层。第二半导体层的第一和第二部分位于晶体管区域中，第二半导体层的第三部分位于电容器区域中。第一，第二和第三硅化物区分别形成在第二半导体层的第一，第二和第三部分上。在形成电介质层之后，去除伪栅极结构形成第一腔。位于第三硅化物区域上方的电介质层的至少一部分被去除，形成第二腔。在第一腔中形成栅极电介质，在第二腔中形成电容器电介质。

10. 发明授权

US08575698B2 MOSFET with thin semiconductor channel and embedded stressor with enhanced junction isolation 有权
标题翻译：具有薄半导体通道的MOSFET和具有增强的结隔离的嵌入式应力源
公开(公告)号：US08575698B2
公开(公告)日：2013-11-05
申请号：US13283308
申请日：2011-10-27
申请人： Kangguo Cheng , Bruce Doris , Ali Khakifirooz , Pranita Kulkarni
发明人： Kangguo Cheng , Bruce Doris , Ali Khakifirooz , Pranita Kulkarni
IPC分类号： H01L27/12
CPC分类号： H01L29/66636 , H01L29/7848 , H01L29/78654
摘要： A field effect transistor structure that uses thin semiconductor on insulator channel to control the electrostatic integrity of the device. Embedded stressors are epitaxially grown in the source/drain area from a template in the silicon substrate through an opening made in the buried oxide in the source/drain region. In addition, a dielectric layer is formed between the embedded stressor and the semiconductor region under the buried oxide layer, which is located directly beneath the channel to suppress junction capacitance and leakage.
摘要翻译：场效应晶体管结构，其使用薄绝缘体上半导体通道来控制器件的静电完整性。嵌入的应力源在源极/漏极区域中从硅衬底中的模板通过在源极/漏极区域中的掩埋氧化物中形成的开口外延生长。此外，在嵌入式应力器和位于沟道正下方的掩埋氧化物层下面的半导体区域之间形成介电层，以抑制结电容和漏电。

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