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1. 发明授权

US08724409B2 Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：US08724409B2
公开(公告)日：2014-05-13
申请号：US12947441
申请日：2010-11-16
申请人： Kang Seol Lee , Jae Hyuk Im
发明人： Kang Seol Lee , Jae Hyuk Im
IPC分类号： G11C7/00 , G11C29/00 , G05F3/16 , G05F3/20
CPC分类号： H03K19/00384
摘要： A semiconductor integrated circuit includes an internal reference voltage generation unit configured to generate an internal reference voltage; a high voltage generation unit configured to pump an external driving voltage based on the internal reference voltage applied from the internal reference voltage generation unit, and generate a high voltage having a specified level; and a reference voltage transfer unit configured to generate a test reference voltage from a reference voltage in a package test mode to correspond to a change in a driving operation of the external driving voltage applied from outside, and monitor and force the internal reference voltage.
摘要翻译：半导体集成电路包括：内部参考电压生成单元，被配置为产生内部参考电压; 高电压产生单元，被配置为基于从内部参考电压产生单元施加的内部参考电压来泵浦外部驱动电压，并产生具有指定电平的高电压; 以及参考电压传送单元，被配置为在封装测试模式下从参考电压产生测试参考电压，以对应于从外部施加的外部驱动电压的驱动操作的变化，并监视和强制内部参考电压。

2. 发明授权

US07379371B2 Method for controlling precharge timing of memory device and apparatus thereof 有权
标题翻译：用于控制存储器件的预充电定时的方法及其装置
公开(公告)号：US07379371B2
公开(公告)日：2008-05-27
申请号：US11834136
申请日：2007-08-06
申请人： Jae Hyuk Im , Kang Seol Lee
发明人： Jae Hyuk Im , Kang Seol Lee
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G11C11/4094 , G11C2211/4065
摘要： A method for controlling a precharge timing of a memory device is disclosed. The method includes making timing of generation of a signal for determining a precharge timing in a normal operation and a signal for determining a precharge timing in a refresh operation different from each other by making timing of generation of a signal for controlling the normal operation and a signal for controlling the refresh operation different from each other.
摘要翻译：公开了一种用于控制存储器件的预充电定时的方法。该方法包括：通过产生用于控制正常操作的信号的定时，产生用于确定正常操作中的预充电定时的信号的定时和用于确定彼此不同的刷新操作中的预充电定时的信号，以及用于控制刷新操作的信号彼此不同。

3. 发明授权

US07310273B2 Method for controlling precharge timing of memory device and apparatus thereof 有权
标题翻译：用于控制存储器件的预充电定时的方法及其装置
公开(公告)号：US07310273B2
公开(公告)日：2007-12-18
申请号：US11108494
申请日：2005-04-18
申请人： Jae Hyuk Im , Kang Seol Lee
发明人： Jae Hyuk Im , Kang Seol Lee
IPC分类号： G11C11/34
CPC分类号： G11C11/406 , G11C11/4094 , G11C2211/4065
摘要： A method for controlling a precharge timing of a memory device is disclosed. The method includes making timing of generation of a signal for determining a precharge timing in a normal operation and a signal for determining a precharge timing in a refresh operation different from each other by making timing of generation of a signal for controlling the normal operation and a signal for controlling the refresh operation different from each other.
摘要翻译：公开了一种用于控制存储器件的预充电定时的方法。该方法包括：通过产生用于控制正常操作的信号的定时，产生用于确定正常操作中的预充电定时的信号的定时和用于确定彼此不同的刷新操作中的预充电定时的信号，以及用于控制刷新操作的信号彼此不同。

4. 发明授权

US08659333B2 Voltage generation circuit of semiconductor memory apparatus 有权
标题翻译：半导体存储装置的电压产生电路
公开(公告)号：US08659333B2
公开(公告)日：2014-02-25
申请号：US13602270
申请日：2012-09-03
申请人： Kang Seol Lee , Jae Hyuk Im
发明人： Kang Seol Lee , Jae Hyuk Im
IPC分类号： H03L7/06
CPC分类号： G11C5/14 , G11C5/145 , G11C11/4074 , H03L5/00
摘要： A voltage generation circuit of a semiconductor memory apparatus includes a plurality of pumping units configured to provide voltages to an output node; a sensing unit configured to sense a voltage level of the output node and generate a pumping enable signal; an oscillator configured to generate an oscillator signal in response to the pumping enable signal; and a control unit configured to selectively output the oscillator signal to the plurality of pumping units in response to an active signal, a power-up signal and a mode register set signal.
摘要翻译：半导体存储装置的电压产生电路包括被配置为向输出节点提供电压的多个泵送单元; 感测单元，被配置为感测所述输出节点的电压电平并产生泵送使能信号; 配置为响应于所述泵浦使能信号产生振荡器信号的振荡器; 以及控制单元，被配置为响应于有效信号，上电信号和模式寄存器设置信号而选择性地将振荡器信号输出到多个泵浦单元。

5. 发明申请

US20110291639A1 SEMICONDUCTOR INTEGRATED CIRCUIT 有权
标题翻译：半导体集成电路
公开(公告)号：US20110291639A1
公开(公告)日：2011-12-01
申请号：US12947441
申请日：2010-11-16
申请人： Kang Seol LEE , Jae Hyuk Im
发明人： Kang Seol LEE , Jae Hyuk Im
IPC分类号： G05F3/16
CPC分类号： H03K19/00384
摘要： A semiconductor integrated circuit includes an internal reference voltage generation unit configured to generate an internal reference voltage; a high voltage generation unit configured to pump an external driving voltage based on the internal reference voltage applied from the internal reference voltage generation unit, and generate a high voltage having a specified level; and a reference voltage transfer unit configured to generate a test reference voltage from a reference voltage in a package test mode to correspond to a change in a driving operation of the external driving voltage applied from outside, and monitor and force the internal reference voltage.
摘要翻译：半导体集成电路包括：内部参考电压生成单元，被配置为产生内部参考电压; 高电压产生单元，被配置为基于从内部参考电压产生单元施加的内部参考电压来泵浦外部驱动电压，并产生具有指定电平的高电压; 以及参考电压传送单元，被配置为在封装测试模式下从参考电压产生测试参考电压，以对应于从外部施加的外部驱动电压的驱动操作的变化，并监视和强制内部参考电压。

6. 发明申请

US20080304341A1 REDUNDANCY CIRCUIT 失效
标题翻译：冗余电路
公开(公告)号：US20080304341A1
公开(公告)日：2008-12-11
申请号：US11958320
申请日：2007-12-17
申请人： Jae Hyuk Im , Yong Ju Chon
发明人： Jae Hyuk Im , Yong Ju Chon
IPC分类号： G11C7/00
CPC分类号： G11C29/785 , G11C2229/763 , G11C2229/766
摘要： A redundancy circuit can include a first fuse set that is configured to receive an address signal and an initializing signal activated when power is up, and to output a first redundancy signal, the first redundancy signal being used to repair a defective cell by using a laser beam radiating method, a second fuse set that is configured to receive the initializing signal, a specific address signal, a test mode signal that is activated when a defective cell exists, and the address signal, and to output a second redundancy signal, the second redundancy signal being used to repair the defective cell by using an electrical fusing method, a first memory cell array that is controlled by the first redundancy signal, and a second memory cell array that is controlled by the second redundancy signal.
摘要翻译：冗余电路可以包括：第一熔丝组，其被配置为接收地址信号;以及在上电时激活的初始化信号;以及输出第一冗余信号，所述第一冗余信号用于通过使用激光器来修复有缺陷的单元波束辐射方法，被配置为接收初始化信号的第二熔丝组，特定地址信号，当存在缺陷单元时被激活的测试模式信号和地址信号，并输出第二冗余信号，第二熔丝组冗余信号用于通过使用电熔接方法修复故障单元，由第一冗余信号控制的第一存储单元阵列和由第二冗余信号控制的第二存储单元阵列。

7. 发明授权

US07468628B2 Internal voltage generators for semiconductor memory device 失效
标题翻译：用于半导体存储器件的内部电压发生器
公开(公告)号：US07468628B2
公开(公告)日：2008-12-23
申请号：US11623396
申请日：2007-01-16
申请人： Jae Hyuk Im , Jae Jin Lee
发明人： Jae Hyuk Im , Jae Jin Lee
IPC分类号： G05F1/00 , H03B5/24
CPC分类号： H02M3/073 , H02M2001/0041
摘要： An internal voltage generator capable of reducing the variation width in the level of an internal voltage VPP, by performing charge pumping only a predetermined number of times in a period where an oscillator driving signal is at a logic HIGH level, and then stopping the charge pumping operation. The oscillator controller generates an oscillation control signal for stopping an oscillation operation of a ring oscillator by using an output signal of a level detector and an output signal of the ring oscillator. The ring oscillator does not generate an oscillation signal at a predetermined time point where an output signal of the level detector is at a HIGH level in response to the oscillation control signal. The charge pump circuit generates an internal voltage by performing a charge pumping operation only predetermined times in response to the oscillation signal, and then stopping the charge pumping operation.
摘要翻译：内部电压发生器能够通过在振荡器驱动信号处于逻辑高电平的时段内仅进行预定次数的电荷泵浦来减小内部电压VPP的电平的变化宽度，然后停止电荷泵送操作。振荡器控制器通过使用电平检测器的输出信号和环形振荡器的输出信号产生用于停止环形振荡器的振荡操作的振荡控制信号。响应于振荡控制信号，在电平检测器的输出信号处于高电平的预定时间点，环形振荡器不产生振荡信号。电荷泵电路通过响应于振荡信号仅进行预定次数的电荷泵送操作来产生内部电压，然后停止电荷泵送操作。

8. 发明申请

US20080159020A1 Word line driving circuit and semiconductor device using the same 有权
标题翻译：字线驱动电路和使用相同的半导体器件
公开(公告)号：US20080159020A1
公开(公告)日：2008-07-03
申请号：US11822000
申请日：2007-06-25
申请人： Jae Hyuk Im
发明人： Jae Hyuk Im
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C11/4085 , G11C8/08 , G11C8/14
摘要： A word line driving circuit and a semiconductor device using the same are disclosed. The word line driving circuit includes a second pad separated from a first pad, the first pad being applied with a first ground voltage, the second pad being applied with a second ground voltage, and a word line driver supplied with the second ground voltage, the word line driver driving word lines.
摘要翻译：公开了一种字线驱动电路和使用该字线驱动电路的半导体器件。字线驱动电路包括与第一焊盘分离的第二焊盘，第一焊盘施加第一接地电压，第二焊盘施加第二接地电压，以及提供有第二接地电压的字线驱动器，字线驱动字线驱动。

9. 发明授权

US08638006B2 Semiconductor apparatus and method of trimming voltage 有权
标题翻译：半导体装置及修整电压的方法
公开(公告)号：US08638006B2
公开(公告)日：2014-01-28
申请号：US12966706
申请日：2010-12-13
申请人： Jae Hyuk Im
发明人： Jae Hyuk Im
IPC分类号： H02J1/10
CPC分类号： G05F1/56 , H01C17/22 , Y10T307/305
摘要： A semiconductor apparatus includes: a master chip and at least one slave chip configured to be stacked one on top of another; and a through-silicon via (TSV) configured to penetrate and electrically couple the master chip and the at least one slave chip, wherein the at least one slave chip receives a reference voltage generated from the master chip via the TSV and independently trims the reference voltage and then generates an internal voltage with the trimmed reference voltage.
摘要翻译：半导体装置包括：主芯片和至少一个从属芯片，其被配置为一个在另一个的顶部上堆叠; 和贯穿硅通孔（TSV），其被配置为穿透并电耦合所述主芯片和所述至少一个从芯片，其中所述至少一个从芯片经由所述TSV接收从所述主芯片产生的参考电压，并且独立地修整所述参考电压，然后产生具有修整的参考电压的内部电压。

10. 发明授权

US08598943B2 Semiconductor integrated circuit with stable rupture voltage fuse 有权
标题翻译：半导体集成电路具有稳定的断裂电压保险丝
公开(公告)号：US08598943B2
公开(公告)日：2013-12-03
申请号：US13219636
申请日：2011-08-27
申请人： Sang Mook Oh , Jae Hyuk Im
发明人： Sang Mook Oh , Jae Hyuk Im
IPC分类号： H01H37/76
CPC分类号： G11C17/16 , G11C29/785 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor integrated circuit includes a fuse set; a terminal assigned to be applied with a first external signal in a normal operation; and a control unit configured to receive a second external signal through the terminal and apply the received second external signal to the fuse set in a fuse control operation.
摘要翻译：半导体集成电路包括保险丝组; 被分配为在正常操作中被施加第一外部信号的终端; 以及控制单元，被配置为通过所述终端接收第二外部信号，并且在所述熔丝控制操作中将所接收的第二外部信号施加到所述熔丝组。

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