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1. 发明授权

US08964449B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08964449B2
公开(公告)日：2015-02-24
申请号：US13355781
申请日：2012-01-23
申请人： Tae Sik Yun , Kang Seol Lee
发明人： Tae Sik Yun , Kang Seol Lee
IPC分类号： G11C11/24 , G11C11/4076 , G11C11/4091 , G11C11/4099
CPC分类号： G11C11/4076 , G11C11/4091 , G11C11/4099
摘要： A semiconductor memory device selects one of a plurality of memory cells as a dummy memory cell. The dummy memory cell is connected to a bit line that is complementary to a bit line connected to a selected memory cell. This technique advantageously compensates capacitance of the bit line. The semiconductor memory device comprises a selected memory cell connected to a first bit line and a first word line, a dummy memory cell connected to a second bit line complementary to the first bit line and a second word line, and a sense amplifier connected to the first and second bit lines and configured to read data stored in the selected memory cell by simultaneously enablement of the first and second word lines.
摘要翻译：半导体存储器件选择多个存储单元中的一个作为虚拟存储单元。虚拟存储器单元连接到与连接到所选存储单元的位线互补的位线。该技术有利地补偿位线的电容。半导体存储器件包括连接到第一位线和第一字线的选定存储器单元，连接到与第一位线互补的第二位线和第二字线的虚拟存储器单元，以及连接到第一位线的读出放大器第一和第二位线，并且被配置为通过同时启用第一和第二字线来读取存储在所选存储单元中的数据。

2. 发明授权

US08724409B2 Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：US08724409B2
公开(公告)日：2014-05-13
申请号：US12947441
申请日：2010-11-16
申请人： Kang Seol Lee , Jae Hyuk Im
发明人： Kang Seol Lee , Jae Hyuk Im
IPC分类号： G11C7/00 , G11C29/00 , G05F3/16 , G05F3/20
CPC分类号： H03K19/00384
摘要： A semiconductor integrated circuit includes an internal reference voltage generation unit configured to generate an internal reference voltage; a high voltage generation unit configured to pump an external driving voltage based on the internal reference voltage applied from the internal reference voltage generation unit, and generate a high voltage having a specified level; and a reference voltage transfer unit configured to generate a test reference voltage from a reference voltage in a package test mode to correspond to a change in a driving operation of the external driving voltage applied from outside, and monitor and force the internal reference voltage.
摘要翻译：半导体集成电路包括：内部参考电压生成单元，被配置为产生内部参考电压; 高电压产生单元，被配置为基于从内部参考电压产生单元施加的内部参考电压来泵浦外部驱动电压，并产生具有指定电平的高电压; 以及参考电压传送单元，被配置为在封装测试模式下从参考电压产生测试参考电压，以对应于从外部施加的外部驱动电压的驱动操作的变化，并监视和强制内部参考电压。

3. 发明申请

US20130234765A1 VOLTAGE GENERATION CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS 有权
标题翻译：半导体存储器的电压发生电路
公开(公告)号：US20130234765A1
公开(公告)日：2013-09-12
申请号：US13602270
申请日：2012-09-03
申请人： Kang Seol LEE , Jae Hyuk IM
发明人： Kang Seol LEE , Jae Hyuk IM
IPC分类号： H03L5/00
CPC分类号： G11C5/14 , G11C5/145 , G11C11/4074 , H03L5/00
摘要： A voltage generation circuit of a semiconductor memory apparatus includes a plurality of pumping units configured to provide voltages to an output node; a sensing unit configured to sense a voltage level of the output node and generate a pumping enable signal; an oscillator configured to generate an oscillator signal in response to the pumping enable signal; and a control unit configured to selectively output the oscillator signal to the plurality of pumping units in response to an active signal, a power-up signal and a mode register set signal.
摘要翻译：半导体存储装置的电压产生电路包括被配置为向输出节点提供电压的多个泵送单元; 感测单元，被配置为感测所述输出节点的电压电平并产生泵送使能信号; 配置为响应于所述泵浦使能信号产生振荡器信号的振荡器; 以及控制单元，被配置为响应于有效信号，上电信号和模式寄存器设置信号而选择性地将振荡器信号输出到多个泵浦单元。

4. 发明申请

US20120218019A1 INTERNAL VOLTAGE GENERATING CIRCUIT AND TESTING METHOD OF INTEGRATED CIRCUIT USING THE SAME 审中-公开
标题翻译：内部电压产生电路及其集成电路的测试方法
公开(公告)号：US20120218019A1
公开(公告)日：2012-08-30
申请号：US13117045
申请日：2011-05-26
申请人： Kang-Seol LEE , Sang-Mook Oh
发明人： Kang-Seol LEE , Sang-Mook Oh
IPC分类号： H03L5/00 , H02J1/00
CPC分类号： G11C5/145 , G11C11/40 , G11C29/12005
摘要： An internal voltage generating circuit of a semiconductor device includes a normal reference voltage generating unit configured to generate a normal reference voltage having a constant voltage level without regard to PVT variations, a test reference voltage generating unit configured to generate a test reference voltage by dividing a voltage level between an external power supply voltage and the normal reference voltage at a set ratio, an operation reference voltage generating unit configured to generate an operation reference voltage by selecting one of the normal reference voltage and the test reference voltage in response to a test signal, and an internal voltage generating unit configured to generate an internal voltage whose voltage level is determined based on the level of the operation reference voltage.
摘要翻译：半导体器件的内部电压产生电路包括：正常参考电压生成单元，被配置为在不考虑PVT变化的情况下生成具有恒定电压电平的正常参考电压;测试参考电压产生单元，被配置为通过将操作基准电压产生单元，被配置为通过响应于测试信号选择正常参考电压和测试参考电压中的一个来产生操作参考电压以及内部电压产生单元，被配置为基于所述操作参考电压的电平来产生其电压电平被确定的内部电压。

5. 发明授权

US08050133B2 Word line driver, method for driving the word line driver, and semiconductor memory device having the word line driver 有权
标题翻译：字线驱动器，用于驱动字线驱动器的方法，以及具有字线驱动器的半导体存储器件
公开(公告)号：US08050133B2
公开(公告)日：2011-11-01
申请号：US12327541
申请日：2008-12-03
申请人： Tae-Sik Yun , Kang-Seol Lee
发明人： Tae-Sik Yun , Kang-Seol Lee
IPC分类号： G11C8/00
CPC分类号： G11C8/08 , G11C8/12 , G11C8/14 , G11C8/18
摘要： A word line driver, a method for driving the word line driver, and a semiconductor memory device having the word line driver. The word line driver receives a main word line driving signal and a sub word line driving signal, to drive a word line with a word line driving signal, wherein the word line is driven concurrently with an activation of the main word line driving signal. The word line driver can reduce the unnecessary current consumption.
摘要翻译：字线驱动器，用于驱动字线驱动器的方法，以及具有字线驱动器的半导体存储器件。字线驱动器接收主字线驱动信号和副字线驱动信号，用字线驱动信号驱动字线，其中字线与主字线驱动信号的激活同时被驱动。字线驱动器可以减少不必要的电流消耗。

6. 发明授权

US07978003B2 Internal voltage generating circuit 有权
标题翻译：内部电压发生电路
公开(公告)号：US07978003B2
公开(公告)日：2011-07-12
申请号：US12630657
申请日：2009-12-03
申请人： Kang-Seol Lee , Jae-Hyuk Im
发明人： Kang-Seol Lee , Jae-Hyuk Im
IPC分类号： G05F1/10 , G05F3/02
CPC分类号： G11C5/14
摘要： There is an internal voltage generating circuit for providing a stable high voltage by making a response time short. The internal voltage generating circuit includes a charge pump unit for generate a high voltage being higher than an external voltage in response to pumping control signals and a supply driving control signal; a pumping control signal generating unit for outputting the pumping control signals to the charge pump unit based on a driving signal; and a supply driving control unit for receiving the driving signal to generate the supply driving control signal to the charge pump unit.
摘要翻译：存在内部电压产生电路，用于通过使响应时间短而提供稳定的高电压。内部电压产生电路包括电荷泵单元，用于响应于泵送控制信号和电源驱动控制信号而产生高于外部电压的高电压; 泵送控制信号产生单元，用于基于驱动信号将泵送控制信号输出到电荷泵单元; 以及电源驱动控制单元，用于接收驱动信号以向电荷泵单元产生电源驱动控制信号。

7. 发明申请

US20110158023A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR DRIVING THE SAME 有权
标题翻译：半导体存储器件及其驱动方法
公开(公告)号：US20110158023A1
公开(公告)日：2011-06-30
申请号：US12829987
申请日：2010-07-02
申请人： Tae-Sik Yun , Kang-Seol Lee
发明人： Tae-Sik Yun , Kang-Seol Lee
IPC分类号： G11C7/06
CPC分类号： G11C11/4091 , G11C7/08 , G11C7/1048 , G11C11/4087 , G11C2207/005
摘要： A semiconductor memory device includes a cell block including a first bit line, a sense amplifier unit including a second bit line and configured to amplify a data signal applied to the second bit line, a connection unit configured to selectively connect the first bit line and the second bit line, a connection control unit configured to receive a control signal for driving the sense amplifier unit and a selection signal for selecting the cell block and generate a connection signal for activating the connection unit at a first time, and a sense amplifier driving control unit configured to receive the control signal and generate a sense amplifier driving signal for driving the sense amplifier unit at a second time after the first time.
摘要翻译：半导体存储器件包括：包括第一位线的单元块，包括第二位线的读出放大器单元，用于放大施加到第二位线的数据信号;连接单元，被配置为选择性地将第一位线和第二位线，连接控制单元，被配置为接收用于驱动读出放大器单元的控制信号和用于选择单元块的选择信号，并且在第一时间产生用于激活连接单元的连接信号，以及读出放大器驱动控制被配置为接收控制信号并且在第一次之后的第二时间产生用于驱动读出放大器单元的读出放大器驱动信号。

8. 发明授权

US07936614B2 Semiconductor memory device and driving method thereof 有权
标题翻译：半导体存储器件及其驱动方法
公开(公告)号：US07936614B2
公开(公告)日：2011-05-03
申请号：US12336164
申请日：2008-12-16
申请人： Ki-Ho Kim , Kang-Seol Lee
发明人： Ki-Ho Kim , Kang-Seol Lee
IPC分类号： G11C7/06
CPC分类号： G11C7/1078 , G11C5/143 , G11C7/1051 , G11C7/1057 , G11C7/1066 , G11C7/1084 , G11C11/4074 , G11C11/4093
摘要： A semiconductor memory device includes a data input driver and a data output driver for receiving an external power supply voltage, and for inputting and outputting data, respectively; and a voltage detector for detecting the external power supply voltage to generate a detection signal, wherein a drive current of each of the data input driver and the data output driver is controlled by the detection signal.
摘要翻译：半导体存储器件包括数据输入驱动器和用于接收外部电源电压的数据输出驱动器，并分别用于输入和输出数据; 以及电压检测器，用于检测外部电源电压以产生检测信号，其中数据输入驱动器和数据输出驱动器中的每一个的驱动电流由检测信号控制。

9. 发明申请

US20090323455A1 WORD LINE DRIVER, METHOD FOR DRIVING THE WORD LINE DRIVER, AND SEMICONDUCTOR MEMORY DEVICE HAVING THE WORD LINE DRIVER 有权
标题翻译：字线驱动器，驱动字线驱动器的方法和具有字线驱动器的半导体存储器件
公开(公告)号：US20090323455A1
公开(公告)日：2009-12-31
申请号：US12327541
申请日：2008-12-03
申请人： Tae-Sik YUN , Kang-Seol Lee
发明人： Tae-Sik YUN , Kang-Seol Lee
IPC分类号： G11C8/08
CPC分类号： G11C8/08 , G11C8/12 , G11C8/14 , G11C8/18
摘要： A word line driver, a method for driving the word line driver, and a semiconductor memory device having the word line driver. The word line driver receives a main word line driving signal and a sub word line driving signal, to drive a word line with a word line driving signal, wherein the word line is driven concurrently with an activation of the main word line driving signal. The word line driver can reduce the unnecessary current consumption.
摘要翻译：字线驱动器，用于驱动字线驱动器的方法，以及具有字线驱动器的半导体存储器件。字线驱动器接收主字线驱动信号和副字线驱动信号，用字线驱动信号驱动字线，其中字线与主字线驱动信号的激活同时被驱动。字线驱动器可以减少不必要的电流消耗。

10. 发明申请

US20090323451A1 SEMICONDUCTOR MEMORY DEVICE 失效
标题翻译：半导体存储器件
公开(公告)号：US20090323451A1
公开(公告)日：2009-12-31
申请号：US12323221
申请日：2008-11-25
申请人： Kang-Seol LEE , Seok-Cheol Yoon
发明人： Kang-Seol LEE , Seok-Cheol Yoon
IPC分类号： G11C5/14 , G11C7/00
CPC分类号： G11C5/14 , G11C5/063
摘要： A semiconductor memory device that prevents a power noise generated at a data input/output pad in a read operation from affecting a data strobe signal pad. The semiconductor memory device includes first power supply voltage pads for a data output circuit, a first power mesh, and a second power supply voltage pad for a data strobe signal output circuit. The first power mesh connects first power supply voltage pads to one another. The second power supply voltage pad is electrically separated from the first power mesh.
摘要翻译：一种半导体存储器件，其防止在读取操作中在数据输入/输出焊盘处产生的功率噪声影响数据选通信号焊盘。半导体存储器件包括用于数据输出电路的第一电源电压焊盘，第一电源网和用于数据选通信号输出电路的第二电源电压焊盘。第一个电源网将第一个电源电压焊盘彼此连接。第二电源电压焊盘与第一电源网电隔离。

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