专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20070001298A1 Semiconductor device with built-in capacitor, and method of producing the same 有权
标题翻译：具有内置电容器的半导体器件及其制造方法
公开(公告)号：US20070001298A1
公开(公告)日：2007-01-04
申请号：US11508289
申请日：2006-08-23
申请人： Kaname Ozawa , Mitsutaka Sato , Yoshiyuki Yoneda
发明人： Kaname Ozawa , Mitsutaka Sato , Yoshiyuki Yoneda
IPC分类号： H01L23/34
CPC分类号： H01L24/49 , H01L23/50 , H01L24/48 , H01L24/73 , H01L25/0657 , H01L2224/05554 , H01L2224/16145 , H01L2224/32145 , H01L2224/32225 , H01L2224/45144 , H01L2224/48091 , H01L2224/48095 , H01L2224/48145 , H01L2224/48147 , H01L2224/48227 , H01L2224/48229 , H01L2224/48465 , H01L2224/4903 , H01L2224/4911 , H01L2224/49171 , H01L2224/4945 , H01L2224/73204 , H01L2224/73265 , H01L2224/85191 , H01L2225/06506 , H01L2225/0651 , H01L2225/06572 , H01L2225/06582 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10161 , H01L2924/10253 , H01L2924/14 , H01L2924/15153 , H01L2924/1517 , H01L2924/15311 , H01L2924/15787 , H01L2924/16195 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19103 , H01L2924/19104 , H01L2924/19107 , H01L2924/30105 , H01L2924/3025 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2924/00015
摘要： A semiconductor device of the invention includes a substrate in which a power-supply electrode and a ground electrode are provided. A first semiconductor chip is disposed over the substrate and has a first conductor layer formed on a surface facing a second semiconductor chip. A second conductor layer is disposed over the first semiconductor chip and has a second conductor layer formed on a surface facing the first semiconductor chip. And an adhesive layer is disposed between the first conductor layer and the second conductor layer and bonds together the first semiconductor chip and the second semiconductor chip. In the semiconductor device, the adhesive layer and the first and second conductor layers function as a capacitor.
摘要翻译：本发明的半导体器件包括其中设置有电源电极和接地电极的基板。第一半导体芯片设置在衬底上并且具有形成在面向第二半导体芯片的表面上的第一导体层。第二导体层设置在第一半导体芯片的上方，并且具有形成在面向第一半导体芯片的表面上的第二导体层。并且粘合剂层设置在第一导体层和第二导体层之间并且将第一半导体芯片和第二半导体芯片接合在一起。在半导体器件中，粘合剂层和第一和第二导体层用作电容器。

2. 发明授权

US08097954B2 Adhesive layer forming a capacitor dielectric between semiconductor chips 有权
标题翻译：粘合层在半导体芯片之间形成电容器电介质
公开(公告)号：US08097954B2
公开(公告)日：2012-01-17
申请号：US11508289
申请日：2006-08-23
申请人： Kaname Ozawa , Mitsutaka Sato , Yoshiyuki Yoneda
发明人： Kaname Ozawa , Mitsutaka Sato , Yoshiyuki Yoneda
IPC分类号： H01L23/58
CPC分类号： H01L24/49 , H01L23/50 , H01L24/48 , H01L24/73 , H01L25/0657 , H01L2224/05554 , H01L2224/16145 , H01L2224/32145 , H01L2224/32225 , H01L2224/45144 , H01L2224/48091 , H01L2224/48095 , H01L2224/48145 , H01L2224/48147 , H01L2224/48227 , H01L2224/48229 , H01L2224/48465 , H01L2224/4903 , H01L2224/4911 , H01L2224/49171 , H01L2224/4945 , H01L2224/73204 , H01L2224/73265 , H01L2224/85191 , H01L2225/06506 , H01L2225/0651 , H01L2225/06572 , H01L2225/06582 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10161 , H01L2924/10253 , H01L2924/14 , H01L2924/15153 , H01L2924/1517 , H01L2924/15311 , H01L2924/15787 , H01L2924/16195 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19103 , H01L2924/19104 , H01L2924/19107 , H01L2924/30105 , H01L2924/3025 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2924/00015
摘要： A semiconductor device of the invention includes a substrate in which a power-supply electrode and a ground electrode are provided. A first semiconductor chip is disposed over the substrate and has a first conductor layer formed on a surface facing a second semiconductor chip. A second conductor layer is disposed over the first semiconductor chip and has a second conductor layer formed on a surface facing the first semiconductor chip. And an adhesive layer is disposed between the first conductor layer and the second conductor layer and bonds together the first semiconductor chip and the second semiconductor chip. In the semiconductor device, the adhesive layer and the first and second conductor layers function as a capacitor.
摘要翻译：本发明的半导体器件包括其中设置有电源电极和接地电极的基板。第一半导体芯片设置在衬底上并且具有形成在面向第二半导体芯片的表面上的第一导体层。第二导体层设置在第一半导体芯片的上方，并且具有形成在面向第一半导体芯片的表面上的第二导体层。并且粘合剂层设置在第一导体层和第二导体层之间并且将第一半导体芯片和第二半导体芯片接合在一起。在半导体器件中，粘合剂层和第一和第二导体层用作电容器。

3. 发明申请

US20060040532A1 Method of designing circuit board 失效
标题翻译：电路板设计方法
公开(公告)号：US20060040532A1
公开(公告)日：2006-02-23
申请号：US11019156
申请日：2004-12-23
申请人： Kaname Ozawa , Mitsutaka Sato , Tetsuya Fujisawa , Yoshiyuki Yoneda , Ryuji Nomoto , Yoshitaka Aiba
发明人： Kaname Ozawa , Mitsutaka Sato , Tetsuya Fujisawa , Yoshiyuki Yoneda , Ryuji Nomoto , Yoshitaka Aiba
IPC分类号： H01R13/648
CPC分类号： G06F17/5068 , H05K3/0005
摘要： A method of design of a circuit board enabling high density conductor lines to be drawn efficiently. A rats nest is formed by connecting pads to which terminals of an electronic device are connected and external connection terminals by lines. A region with the highest density of lines of the rats nest is then selected and design rules relating to routes and dimensions of conductor lines are set in the region with the highest density of lines of the rats nest. Conductor lines are then laid at the region with the highest density of lines of the rats nest, and whether or not the conductor lines can be laid at the region with the highest density of lines of the rats nest is confirmed. Setting of the design rules and laying of conductor lines are if the conductor lines cannot be laid, and the conductor lines of the remaining regions are laid by the set design rules if the conductor lines can be laid.
摘要翻译：一种能够高效率地绘制高密度导线的电路板的设计方法。大鼠巢通过连接电子装置的端子的连接垫和通过线路的外部连接端子形成。然后选择大鼠巢线密度最高的区域，并且在具有最大密度的大鼠巢的区域中设置与导线的路线和尺寸相关的设计规则。然后将导体线放置在具有最高密度的大鼠巢的区域，并且确定导线是否可以放置在具有最大密度的大鼠巢的密度的区域。如果导体线不能铺设，则设计规则和布线的设置，如果可以铺设导线，则通过设定的规则布置其余区域的导体线。

4. 发明授权

US07251801B2 Method of designing circuit board 失效
标题翻译：电路板设计方法
公开(公告)号：US07251801B2
公开(公告)日：2007-07-31
申请号：US11019156
申请日：2004-12-23
申请人： Kaname Ozawa , Mitsutaka Sato , Tetsuya Fujisawa , Yoshiyuki Yoneda , Ryuji Nomoto , Yoshitaka Aiba
发明人： Kaname Ozawa , Mitsutaka Sato , Tetsuya Fujisawa , Yoshiyuki Yoneda , Ryuji Nomoto , Yoshitaka Aiba
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , H05K3/0005
摘要： A method of design of a circuit board enabling high density conductor lines to be drawn efficiently. A rats nest is formed by connecting pads to which terminals of an electronic device are connected and external connection terminals by lines. A region with the highest density of lines of the rats nest is then selected and design rules relating to routes and dimensions of conductor lines are set in the region with the highest density of lines of the rats nest. Conductor lines are then laid at the region with the highest density of lines of the rats nest, and whether or not the conductor lines can be laid at the region with the highest density of lines of the rats nest is confirmed. Setting of the design rules and laying of conductor lines are if the conductor lines cannot be laid, and the conductor lines of the remaining regions are laid by the set design rules if the conductor lines can be laid.
摘要翻译：一种能够高效率地绘制高密度导线的电路板的设计方法。大鼠巢通过连接电子装置的端子的连接垫和通过线路的外部连接端子形成。然后选择大鼠巢线密度最高的区域，并且在具有最大密度的大鼠巢的区域中设置与导线的路线和尺寸相关的设计规则。然后将导体线放置在具有最高密度的大鼠巢的区域，并且确定导线是否可以放置在具有最大密度的大鼠巢的密度的区域。如果导体线不能铺设，则设计规则和布线的设置，如果可以铺设导体线，则通过设定的规则布置其余区域的导体线。

5. 发明申请

US20070138616A1 Semiconductor device and manufacturing method of the same 审中-公开
标题翻译：半导体器件及其制造方法相同
公开(公告)号：US20070138616A1
公开(公告)日：2007-06-21
申请号：US11703702
申请日：2007-02-08
申请人： Tetsuya Fujisawa , Kaname Ozawa , Mitsutaka Sato
发明人： Tetsuya Fujisawa , Kaname Ozawa , Mitsutaka Sato
IPC分类号： H01L23/48
CPC分类号： H01L23/49827 , H01L23/13 , H01L23/3128 , H01L23/49816 , H01L23/50 , H01L23/5384 , H01L23/5386 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/81 , H01L24/85 , H01L24/91 , H01L24/97 , H01L25/0652 , H01L25/18 , H01L2224/0401 , H01L2224/05554 , H01L2224/06135 , H01L2224/16145 , H01L2224/16225 , H01L2224/274 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/4824 , H01L2224/48465 , H01L2224/49171 , H01L2224/73204 , H01L2224/73207 , H01L2224/73215 , H01L2224/73265 , H01L2224/81801 , H01L2224/85 , H01L2224/97 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/12041 , H01L2924/15162 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H01L2924/19104 , H01L2924/30105 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor device, includes a supporting board; and a semiconductor element mounted on a first main surface of the supporting board. The supporting board includes a first electrode formed on the first main surface, a second electrode formed on a second main surface, and an opening or notch forming part. A first electrode pad of the semiconductor element faces and is connected to the first electrode of the supporting board. A second electrode pad of the semiconductor element and the second electrode of the supporting board are electrically connected via the opening or notch forming part.
摘要翻译：一种半导体器件，包括支撑板; 以及安装在所述支撑板的第一主表面上的半导体元件。支撑板包括形成在第一主表面上的第一电极，形成在第二主表面上的第二电极和开口或凹口形成部分。半导体元件的第一电极焊盘面对并连接到支撑板的第一电极。半导体元件的第二电极焊盘和支撑板的第二电极经由开口或凹口形成部分电连接。

6. 发明授权

US06316838B1 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US06316838B1
公开(公告)日：2001-11-13
申请号：US09531231
申请日：2000-03-20
申请人： Kaname Ozawa , Hayato Okuda , Tetsuya Hiraoka , Mitsutaka Sato , Yuji Akashi , Akira Okada , Masahiko Harayama
发明人： Kaname Ozawa , Hayato Okuda , Tetsuya Hiraoka , Mitsutaka Sato , Yuji Akashi , Akira Okada , Masahiko Harayama
IPC分类号： H01L2348
CPC分类号： H01L24/85 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/78 , H01L25/0657 , H01L2224/05554 , H01L2224/05568 , H01L2224/05573 , H01L2224/16 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/45015 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48145 , H01L2224/48227 , H01L2224/48247 , H01L2224/48465 , H01L2224/48479 , H01L2224/48599 , H01L2224/48699 , H01L2224/4903 , H01L2224/4911 , H01L2224/49175 , H01L2224/49429 , H01L2224/73265 , H01L2224/78301 , H01L2224/85051 , H01L2224/85181 , H01L2224/85205 , H01L2224/85951 , H01L2225/06506 , H01L2225/0651 , H01L2225/06517 , H01L2225/06527 , H01L2225/06582 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01074 , H01L2924/01075 , H01L2924/01079 , H01L2924/014 , H01L2924/07802 , H01L2924/10161 , H01L2924/15183 , H01L2924/15311 , H01L2924/1532 , H01L2924/181 , H01L2924/20752 , H01L2924/20755 , H01L2924/20756 , H01L2924/20757 , H01L2924/20758 , H01L2924/20759 , H01L2924/2076 , H01L2924/30107 , H01L2224/48471 , H01L2924/00012 , H01L2924/00 , H01L2924/2075 , H01L2924/20754 , H01L2224/05599 , H01L2224/4554
摘要： A semiconductor device includes a substrate provided with a plurality of leads, a face-down semiconductor element provided on one surface of the substrate, a first stacked semiconductor element and a second stacked semiconductor element provided on another surface of the substrate and connected to the substrate by wires, and an extended wiring mechanism for connecting electrodes of the face-down semiconductor element and electrodes of the first and second semiconductor elements. The connected electrodes are equi-electrodes whose electrical characteristics are equal.
摘要翻译：半导体器件包括设置有多个引线的衬底，设置在衬底的一个表面上的面向下半导体元件，设置在衬底的另一个表面上并连接到衬底的第一堆叠半导体元件和第二堆叠半导体元件以及用于连接面朝下半导体元件的电极和第一和第二半导体元件的电极的延长布线机构。连接的电极是电特性相等的等电极。

7. 发明授权

US06696754B2 Semiconductor module including a plurality of semiconductor devices detachably 失效
标题翻译：半导体模块可拆卸地包括多个半导体器件
公开(公告)号：US06696754B2
公开(公告)日：2004-02-24
申请号：US10214306
申请日：2002-08-08
申请人： Mitsutaka Sato , Tetsuya Fujisawa , Shigeyuki Maruyama , Junichi Kasai , Toshimi Kawahara , Toshio Hamano , Yoshihiro Kubota , Mitsunada Osawa , Yoshiyuki Yoneda , Kazuto Tsuji , Hirohisa Matsuki
发明人： Mitsutaka Sato , Tetsuya Fujisawa , Shigeyuki Maruyama , Junichi Kasai , Toshimi Kawahara , Toshio Hamano , Yoshihiro Kubota , Mitsunada Osawa , Yoshiyuki Yoneda , Kazuto Tsuji , Hirohisa Matsuki
IPC分类号： H01L2334
CPC分类号： H01L25/105 , H01L2224/48227 , H01L2225/1023 , H01L2924/09701 , H01L2924/1533 , H01L2924/3025 , H01R12/82 , H05K7/1431 , H01L2924/00
摘要： A semiconductor module includes a plurality of semiconductor devices each including a circuit substrate carrying thereon a single memory semiconductor chip and a socket for holding the semiconductor devices detachably.
摘要翻译：半导体模块包括多个半导体器件，每个半导体器件包括承载有单个存储器半导体芯片的电路衬底和用于可拆卸地保持半导体器件的插座。

8. 发明授权

US06472744B2 Semiconductor module including a plurality of semiconductor devices detachably 失效
标题翻译：半导体模块可拆卸地包括多个半导体器件
公开(公告)号：US06472744B2
公开(公告)日：2002-10-29
申请号：US09084097
申请日：1998-05-26
申请人： Mitsutaka Sato , Tetsuya Fujisawa , Shigeyuki Maruyama , Junichi Kasai , Toshimi Kawahara , Toshio Hamano , Yoshihiro Kubota , Mitsunada Osawa , Yoshiyuki Yoneda , Kazuto Tsuji , Hirohisa Matsuki
发明人： Mitsutaka Sato , Tetsuya Fujisawa , Shigeyuki Maruyama , Junichi Kasai , Toshimi Kawahara , Toshio Hamano , Yoshihiro Kubota , Mitsunada Osawa , Yoshiyuki Yoneda , Kazuto Tsuji , Hirohisa Matsuki
IPC分类号： H01L2500
CPC分类号： H01L25/105 , H01L2224/48227 , H01L2225/1023 , H01L2924/09701 , H01L2924/1533 , H01L2924/3025 , H01R12/82 , H05K7/1431 , H01L2924/00
摘要： A semiconductor module includes a plurality of semiconductor devices each including a circuit substrate carrying thereon a single memory semiconductor chip and a socket for holding the semiconductor devices detachably.
摘要翻译：半导体模块包括多个半导体器件，每个半导体器件包括承载有单个存储器半导体芯片的电路衬底和用于可分离地保持半导体器件的插座。

9. 发明授权

US06905951B2 Method of forming a device substrate and semiconductor package including a pyramid contact 失效
标题翻译：形成器件衬底和包括金字塔接触的半导体封装的方法
公开(公告)号：US06905951B2
公开(公告)日：2005-06-14
申请号：US10862403
申请日：2004-06-08
申请人： Yoshiyuki Yoneda , Masaharu Minamizawa , Eiji Watanabe , Mitsutaka Sato
发明人： Yoshiyuki Yoneda , Masaharu Minamizawa , Eiji Watanabe , Mitsutaka Sato
IPC分类号： H01L23/12 , H01L21/48 , H01L21/56 , H01L21/68 , H01L23/14 , H01L23/31 , H01L23/32 , H01L23/498 , H01L21/44 , H01L21/302 , H01L21/461
CPC分类号： H01L21/6835 , H01L21/4846 , H01L21/563 , H01L23/147 , H01L23/3121 , H01L23/49822 , H01L24/16 , H01L24/45 , H01L24/48 , H01L24/73 , H01L2221/68345 , H01L2224/05568 , H01L2224/05573 , H01L2224/13099 , H01L2224/16 , H01L2224/16225 , H01L2224/32225 , H01L2224/45144 , H01L2224/4809 , H01L2224/48095 , H01L2224/48227 , H01L2224/48465 , H01L2224/73203 , H01L2224/73204 , H01L2224/73265 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/014 , H01L2924/09701 , H01L2924/15311 , H01L2924/15787 , H01L2924/181 , H01L2924/00012 , H01L2924/00 , H01L2224/05599
摘要： A semiconductor device substrate has fine terminals with a small pitch and is able to be easily produced at a low cost without using a special process. A mounting terminal has a pyramidal shape and extending between a front surface and a back surface of a silicon substrate. An end of the mounting terminal protrudes from the back surface of the silicon substrate. A wiring layer is formed on the front surface of the silicon substrate. The wiring layer includes a conductive layer that is electrically connected to the mounting terminal.
摘要翻译：半导体器件基板具有细小的间距的端子，并且能够在不使用特殊工艺的情况下以低成本容易地制造。安装端子具有金字塔形状并且在硅衬底的前表面和后表面之间延伸。安装端子的一端从硅衬底的背面突出。在硅衬底的前表面上形成布线层。布线层包括电连接到安装端子的导电层。

10. 发明授权

US06781224B2 Semiconductor device and package including forming pyramid mount protruding through silicon substrate 有权
标题翻译：包括形成通过硅衬底突出的金字塔安装的半导体器件和封装
公开(公告)号：US06781224B2
公开(公告)日：2004-08-24
申请号：US10262074
申请日：2002-10-02
申请人： Yoshiyuki Yoneda , Masaharu Minamizawa , Eiji Watanabe , Mitsutaka Sato
发明人： Yoshiyuki Yoneda , Masaharu Minamizawa , Eiji Watanabe , Mitsutaka Sato
IPC分类号： H01L2302
CPC分类号： H01L21/6835 , H01L21/4846 , H01L21/563 , H01L23/147 , H01L23/3121 , H01L23/49822 , H01L24/16 , H01L24/45 , H01L24/48 , H01L24/73 , H01L2221/68345 , H01L2224/05568 , H01L2224/05573 , H01L2224/13099 , H01L2224/16 , H01L2224/16225 , H01L2224/32225 , H01L2224/45144 , H01L2224/4809 , H01L2224/48095 , H01L2224/48227 , H01L2224/48465 , H01L2224/73203 , H01L2224/73204 , H01L2224/73265 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/014 , H01L2924/09701 , H01L2924/15311 , H01L2924/15787 , H01L2924/181 , H01L2924/00012 , H01L2924/00 , H01L2224/05599
摘要： A semiconductor device substrate has fine terminals with a small pitch and is able to be easily produced at a low cost without using a special process. A mounting terminal has a pyramidal shape and extending between a front surface and a back surface of a silicon substrate. An end of the mounting terminal protrudes from the back surface of the silicon substrate. A wiring layer is formed on the front surface of the silicon substrate. The wiring layer includes a conductive layer that is electrically connected to the mounting terminal.
摘要翻译：半导体器件基板具有细小的间距的端子，并且能够在不使用特殊工艺的情况下以低成本容易地制造。安装端子具有金字塔形状并且在硅衬底的前表面和后表面之间延伸。安装端子的一端从硅衬底的背面突出。在硅衬底的前表面上形成布线层。布线层包括电连接到安装端子的导电层。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式