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1. 发明授权

US08862426B2 Method and test system for fast determination of parameter variation statistics 有权
标题翻译：方法和测试系统，用于快速确定参数变化统计
公开(公告)号：US08862426B2
公开(公告)日：2014-10-14
申请号：US11961442
申请日：2007-12-20
申请人： Kanak B. Agarwal , Jerry D. Hayes , Sani R. Nassif
发明人： Kanak B. Agarwal , Jerry D. Hayes , Sani R. Nassif
IPC分类号： G01R19/00 , G01R31/00 , G01R31/14 , G01R31/28 , G01R31/3185
CPC分类号： G01R31/2884 , G01R31/2831 , G01R31/318533 , G01R31/318558
摘要： A method and test system for fast determination of parameter variation statistics provides a mechanism for determining process variation and parameter statistics using low computing power and readily available test equipment. A test array having individually selectable devices is stimulated under computer control to select each of the devices sequentially. A test output from the array provides a current or voltage that dependent on a particular device parameter. The sequential selection of the devices produces a voltage or current waveform, characteristics of which are measured using a digital multi-meter that is interfaced to the computer. The rms value of the current or voltage at the test output is an indication of the standard deviation of the parameter variation and the DC value of the current or voltage is an indication of the mean value of the parameter.
摘要翻译：用于快速确定参数变化统计的方法和测试系统提供了使用低计算能力和容易获得的测试设备来确定过程变化和参数统计的机制。在计算机控制下刺激具有可单独选择的装置的测试阵列以依次选择每个装置。阵列的测试输出提供依赖于特定器件参数的电流或电压。器件的顺序选择产生电压或电流波形，其特性使用与计算机连接的数字万用表进行测量。测试输出端的电流或电压的有效值表示参数变化的标准偏差，电流或电压的直流值表示参数的平均值。

2. 发明申请

US20130061185A1 MASK ASSIGNMENT FOR MULTIPLE PATTERNING LITHOGRAPHY 有权
标题翻译：多功能拼图的掩蔽分配
公开(公告)号：US20130061185A1
公开(公告)日：2013-03-07
申请号：US13223706
申请日：2011-09-01
申请人： Rani S. Abou Ghaida , Kanak B. Agarwal , Lars W. Liebmann , Sani R. Nassif
发明人： Rani S. Abou Ghaida , Kanak B. Agarwal , Lars W. Liebmann , Sani R. Nassif
IPC分类号： G06F17/50
CPC分类号： G03F1/70 , G03F7/70466 , G03F7/70475
摘要： A mechanism is provided for mask assignment for triple patterning lithography. The mechanism identifies tip-to-tip (TT), tip-to-side (TS), and side-to-side (SS) conflicting parts by design rule dependent projection. The mechanism finds stitch location for TT, TS, and SS conflicts separately. The mechanism colors TT, TS, and SS conflicting parts with mask0/mask1, mask0/mask2, mask1/mask2 coloring cycle with each type colored separately. The mechanism uses existing infrastructure of two-way coloring. As a first objective, the mechanism attempts to minimize conflicts. As a second objective, the mechanism attempts to minimize the number of stitches by assigning the two sides of stitches to the same mask. Once coloring of all conflicting parts is done, the mechanism colors non-conflicting parts to maximize minimum overlap of exposures and to use both colors if two sides are different colors and one color if both sides are the same color.
摘要翻译：提供了用于三重图案化光刻的掩模分配的机构。该机制通过设计规则相关的投影来识别尖端到尖端（TT），尖端到侧面（TS）以及侧向（SS）冲突部分。该机制分别查找TT，TS和SS冲突的针脚位置。机制颜色TT，TS和SS冲突部分与mask0 / mask1，mask0 / mask2，mask1 / mask2着色循环，每种类型分别着色。该机制使用现有的双向着色基础设施。作为第一个目标，该机制试图尽量减少冲突。作为第二个目的，该机构通过将针脚的两侧分配到相同的面罩来尝试最小化线迹数。一旦完成所有冲突部分的着色，该机制将颜色非冲突部分，以最大化曝光的最小重叠，并且如果双面是不同的颜色，则使用两种颜色，如果两面是相同颜色，则使用一种颜色。

3. 发明授权

US08347240B2 Split-layer design for double patterning lithography 有权
标题翻译：双层图案平版印刷的分层设计
公开(公告)号：US08347240B2
公开(公告)日：2013-01-01
申请号：US12915923
申请日：2010-10-29
申请人： Kanak B. Agarwal , Lars W. Liebmann , Sani R. Nassif
发明人： Kanak B. Agarwal , Lars W. Liebmann , Sani R. Nassif
IPC分类号： G06F17/50 , G06F19/00 , G03F1/00 , G21K5/00
CPC分类号： G03F1/70 , H01L27/0207
摘要： A mechanism is provided for converting a set of single-layer design rules into a set of split-layer design rules for double patterning lithography (DPL). The set of single-layer design rules and minimum lithographic resolution pitch constraints for single exposure are identified. The set of single-layer design rules comprise a first plurality of minimum distances that are required by a set of first shapes in a single-layer design. Each of the first plurality of minimum distances in the set of single-layer design rules are modified with regard to the minimum lithographic resolution pitch constraints for single exposure, thereby forming the set of split-layer design rules. The set of split-layer design rules comprise a second plurality of minimum distances that are required by a set of second shapes and a set of third shapes in a split-layer design. The set of split-layer design rules are then coded into a design rule checker.
摘要翻译：提供了一种用于将一组单层设计规则转换为用于双重图案化光刻（DPL）的一组分裂层设计规则的机制。确定了一套单层设计规则和单次曝光的最小光刻分辨率间距约束。单层设计规则的集合包括单层设计中的一组第一形状所需的第一多个最小距离。关于单次曝光的最小光刻分辨率间距约束修改单层设计规则集合中的第一多个最小距离中的每一个，从而形成分裂层设计规则集合。分裂层设计规则的集合包括一组第二形状所需的第二多个最小距离和分裂层设计中的一组第三形状。然后将该组分裂设计规则编码为设计规则检查器。

4. 发明申请

US20090125258A1 SCANNABLE VIRTUAL RAIL RING OSCILLATOR CIRCUIT AND SYSTEM FOR MEASURING VARIATIONS IN DEVICE CHARACTERISTICS 失效
标题翻译：扫描虚拟铁轨振荡器电路和用于测量设备特性变化的系统
公开(公告)号：US20090125258A1
公开(公告)日：2009-05-14
申请号：US12356145
申请日：2009-01-20
申请人： Kanak B. Agarwal , Sani R. Nassif
发明人： Kanak B. Agarwal , Sani R. Nassif
IPC分类号： G01R31/28 , G01R23/02
CPC分类号： G01R31/2884 , G01R31/318577 , H03K3/0315 , H03K2005/00058 , H03K2005/00234
摘要： A scannable virtual rail ring oscillator circuit and system for measuring variations in device characteristics provides the ability to study random device characteristic variation as well as systematic differences between N-channel and P-channel devices using a ring oscillator frequency measurement. The ring oscillator is operated from at least one virtual power supply rail that is connected to the actual power supply rail by a plurality of transistors controlled by a programmable source. The transistors are physically distributed along the physical distribution of the ring oscillator elements and each can be enabled in turn and the variation in ring oscillator frequency measured. The ring oscillator frequency measurements yield information about the variation between the transistors and N-channel vs. P-channel variation can be studied by employing positive and negative virtual power supply rails with corresponding P-channel and N-channel control transistors.
摘要翻译：用于测量器件特性变化的可扫描虚拟轨道环形振荡器电路和系统提供了使用环形振荡器频率测量来研究随机器件特性变化以及N沟道和P沟道器件之间的系统差异的能力。环形振荡器通过由可编程源控制的多个晶体管连接到实际电源轨的至少一个虚拟电源轨来操作。晶体管沿着环形振荡器元件的物理分布物理分布，并且可以依次启用晶体管，并测量环形振荡器频率的变化。可以通过使用具有相应P沟道和N沟道控制晶体管的正和负虚拟电源轨来研究环形振荡器频率测量产生关于晶体管与N沟道与P沟道变化之间变化的信息。

5. 发明申请

US20080097715A1 Method of separating the process variation in threshold voltage and effective channel length by electrical measurements 失效
标题翻译：通过电气测量分离阈值电压和有效通道长度的工艺变化的方法
公开(公告)号：US20080097715A1
公开(公告)日：2008-04-24
申请号：US11551814
申请日：2006-10-23
申请人： Kanak B. Agarwal , Sani R. Nassif
发明人： Kanak B. Agarwal , Sani R. Nassif
IPC分类号： G06F19/00 , G06F17/18
CPC分类号： H01L22/14 , H01L29/78
摘要： A IC wafer is fabricated using a process of interest to have a plurality of FET devices with different channel lengths (Leff) form a plurality of channel length groups. The threshold voltage (VT) is measured of a statistical sample of the FET devices in each channel length group at two different drain-to-source voltage (VDS). The mean of VT is calculated for each channel length and each VDS. A slope coefficient λ relating VT to Leff is calculated at each VDS. The total variance of VT is calculated at each VDS. Two equations at each VDS, each relating the total variance of VT to the variance of VT with respect to dopant levels and the square of the slope coefficient λ times the variance of Leff, are solved simultaneously to obtain the variance of VT with respect to dopant levels and the variance of Leff.
摘要翻译：使用感兴趣的工艺制造IC晶片，以具有形成多个沟道长度组的具有不同沟道长度（Leff）的多个FET器件。在两个不同的漏极 - 源极电压（VDS）下，测量每个沟道长度组中的FET器件的统计采样的阈值电压（VT）。对每个通道长度和每个VDS计算VT的平均值。在每个VDS处计算出与Leff相关的VT的斜率系数λ。在每个VDS处计算VT的总方差。每个VDS上的两个方程，每个VDS相关于VT的总方差相对于掺杂剂水平的方差和斜率系数λ乘以Leff方差的平方式被同时求解以获得相对于掺杂剂的VT的方差水平和Leff的差异。

6. 发明申请

US20080030220A1 Characterization Array and Method for Determining Threshold Voltage Variation 失效
标题翻译：用于确定阈值电压变化的表征阵列和方法
公开(公告)号：US20080030220A1
公开(公告)日：2008-02-07
申请号：US11462186
申请日：2006-08-03
申请人： Kanak B. Agarwal , Sani R. Nassif
发明人： Kanak B. Agarwal , Sani R. Nassif
IPC分类号： G01R31/36
CPC分类号： G01R31/2884 , G01R31/2621 , G01R31/275
摘要： A characterization array and method for determining threshold voltage variation rapidly provides accurate threshold voltage distribution values for process verification and improvement. The characterization array includes a circuit for imposing a fixed drain-source voltage and a constant channel current at individual devices within the array. A circuit for sensing the source voltage of the individual device is also included within the array. The statistical distribution of the threshold voltage is determined directly from the source voltage distribution by offsetting each source voltage by a value determined by completely characterizing one or more devices within the array. The resulting methodology avoids the necessity of otherwise characterizing each device within the array, thus reducing measurement time dramatically.
摘要翻译：用于确定阈值电压变化的表征阵列和方法快速提供准确的阈值电压分布值用于过程验证和改进。表征阵列包括用于在阵列内的各个器件处施加固定的漏源电压和恒定沟道电流的电路。用于感测单个器件的源极电压的电路也包括在阵列内。阈值电压的统计分布直接由源电压分布确定，通过将每个源极电压抵消通过完全表征阵列内的一个或多个器件而确定的值。所得到的方法避免了对阵列内的每个器件进行表征的必要性，从而显着地减少了测量时间。

7. 发明申请

US20070296442A1 Method and Apparatus for Measuring Device Mismatches 有权
标题翻译：用于测量设备不匹配的方法和设备
公开(公告)号：US20070296442A1
公开(公告)日：2007-12-27
申请号：US11422913
申请日：2006-06-08
申请人： Kanak B. Agarwal , Ying Liu , Chandler T. McDowell , Sani R. Nassif , James F. Plusquellic , Jayakumaran Sivagnaname
发明人： Kanak B. Agarwal , Ying Liu , Chandler T. McDowell , Sani R. Nassif , James F. Plusquellic , Jayakumaran Sivagnaname
IPC分类号： G01R31/26
CPC分类号： G01R31/3004 , G11C11/41 , G11C29/02 , G11C29/12005 , G11C29/50 , G11C2029/1202 , G11C2029/1204 , G11C2029/5004 , G11C2029/5006
摘要： A test structure for statistical characterization of local device mismatches contains densely populated SRAM devices arranged in a row/column addressable array that enables resource sharing of many devices. The test structure includes a built-in sensing mechanism to calibrate or null out sources of error, and current steering to avoid negative effects of current leakage along spurious paths. The gate and drain lines of each column are driven from both the top and bottom to minimizes parasitic effects. The system can handle a large number of devices while still providing high spatial resolution of current measurements.
摘要翻译：用于局部器件不匹配的统计表征的测试结构包含布置在行/列可寻址阵列中的密集填充的SRAM器件，其使许多器件的资源共享。该测试结构包括一个校准或消除误差源的内置感测机构，以及电流转向，以避免杂散路径上的电流泄漏的负面影响。每列的栅极和漏极线都从顶部和底部驱动以最小化寄生效应。该系统可以处理大量设备，同时仍然提供高空间分辨率的电流测量。

8. 发明授权

US08640062B2 Rapid estimation of temperature rise in wires due to Joule heating 有权
标题翻译：快速估算由于焦耳加热引起的电线温升
公开(公告)号：US08640062B2
公开(公告)日：2014-01-28
申请号：US13157980
申请日：2011-06-10
申请人： Kanak B. Agarwal , Sani R. Nassif , Ronald D. Rose , Chenggang Xu
发明人： Kanak B. Agarwal , Sani R. Nassif , Ronald D. Rose , Chenggang Xu
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F17/5018
摘要： A mechanism is provided for rapid estimation of temperature rise in wires due to Joule heating. The mechanism provides fast and accurate estimation of temperature rise in wires due to self heating. Fast estimation is important to handle millions of nets at the full-chip level. The mechanism models lateral heat flow by considering longitudinal heat flow along the wire and lateral thermal coupling to the other wires in the same level. Lateral heat flow can have a significant effect on the temperature rise. The mechanism also models vertical heat flow to the substrate and the heat sink by considering thermal conductivities of vias and inter-layer dielectric (ILD). The mechanism efficiently solves the thermal system to enable physical design optimizations (e.g., wire sizing, etc.) for fixing electromigration violations.
摘要翻译：提供了一种用于快速估计由于焦耳加热引起的电线温升的机制。该机构可以快速，准确地估计由于自加热引起的导线温升。快速估计对于在全芯片级处理数百万网络很重要。该机制通过考虑沿着导线的纵向热流动并在同一水平的横向热耦合到另一条导线来模拟横向热流。横向热流可以对温升产生显着影响。该机制还通过考虑通孔和层间电介质（ILD）的热导率来模拟垂直热流到衬底和散热片。该机制有效地解决了热系统，以实现用于固定电迁移违规的物理设计优化（例如，线尺寸等）。

9. 发明申请

US20120317523A1 Reducing Through Process Delay Variation in Metal Wires 有权
标题翻译：通过金属线的过程延迟变化减少
公开(公告)号：US20120317523A1
公开(公告)日：2012-12-13
申请号：US13157909
申请日：2011-06-10
申请人： Kanak B. Agarwal , Shayak Banerjee , Sani R. Nassif
发明人： Kanak B. Agarwal , Shayak Banerjee , Sani R. Nassif
IPC分类号： G06F17/50
CPC分类号： G03F1/70
摘要： A mechanism is provided for reducing through process delay variation in metal wires by layout retargeting. The mechanism performs initial retargeting, decomposition, and resolution enhancement techniques. For example, the mechanism may perform optical proximity correction. The mechanism then performs lithographic simulation and optical rules checking. The mechanism provides retargeting rules developed based on coupling lithography simulation and resistance/capacitance (RC) extraction. The mechanism performs RC extraction to capture non-linear dependency of RC on design shape dimensions. If the electrical properties in the lithographic simulation are within predefined specifications, the mechanism accepts the retargeting rules; however, if the electrical properties from RC extraction are outside the predefined specifications, the mechanism modifies the retargeting rules and repeats resolution enhancement techniques.
摘要翻译：提供了一种通过布局重新定位来减少金属线中的工艺延迟变化的机制。该机制执行初始重定向，分解和分辨率增强技术。例如，该机构可以执行光学邻近校正。该机制进行光刻模拟和光学规则检查。该机制提供了基于耦合光刻模拟和电阻/电容（RC）提取开发的重定向规则。该机制执行RC提取以捕获RC对设计形状尺寸的非线性依赖性。如果光刻仿真中的电性能在预定义的规格范围内，则该机制接受重定向规则; 然而，如果来自RC提取的电性能超出预定义的规范，则该机制修改重定向规则并重复分辨率增强技术。

10. 发明授权

US07759963B2 Method for determining threshold voltage variation using a device array 失效
标题翻译：使用器件阵列确定阈值电压变化的方法
公开(公告)号：US07759963B2
公开(公告)日：2010-07-20
申请号：US12147277
申请日：2008-06-26
申请人： Kanak B. Agarwal , Sani R. Nassif
发明人： Kanak B. Agarwal , Sani R. Nassif
IPC分类号： G01R31/26
CPC分类号： G01R31/2884 , G01R31/2621 , G01R31/275
摘要： A method of measuring threshold voltage variation using a device array provides accurate threshold voltage distribution values for process verification and improvement. The characterization array imposes a fixed drain-source voltage and a constant channel current at individual devices within the array. Another circuit senses the source voltage of the individual device within the array. The statistical distribution of the threshold voltage is determined directly from the source voltage distribution by offsetting each source voltage by a value determined by completely characterizing one or more devices within the array. The resulting methodology avoids the necessity of otherwise characterizing each device within the array, thus reducing measurement time dramatically.
摘要翻译：使用器件阵列测量阈值电压变化的方法为处理验证和改进提供了准确的阈值电压分布值。表征阵列在阵列内的各个器件上施加固定的漏源电压和恒定沟道电流。另一个电路感测阵列内各个器件的源极电压。阈值电压的统计分布直接由源电压分布确定，通过将每个源极电压抵消通过完全表征阵列内的一个或多个器件而确定的值。所得到的方法避免了对阵列内的每个器件进行表征的必要性，从而显着地减少了测量时间。

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