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1. 发明申请

US20100333049A1 Model-Based Retargeting of Layout Patterns for Sub-Wavelength Photolithography 有权
标题翻译：用于亚波长光刻的布局图案的基于模型的重新定位
公开(公告)号：US20100333049A1
公开(公告)日：2010-12-30
申请号：US12492301
申请日：2009-06-26
申请人： Kanak B. Agarwal , Shayak Banerjee , Sani R. Nassif
发明人： Kanak B. Agarwal , Shayak Banerjee , Sani R. Nassif
IPC分类号： G06F17/50
CPC分类号： G03F1/36
摘要： Mechanism are provided for model-based retargeting of photolithographic layouts. An optical proximity correction is performed on a set of target patterns for a predetermined number of iterations until a counter value exceeds a maximum predetermined number of iterations in order to produce a set of optical proximity correction mask shapes. A set of lithographic contours is generated for each of the set of optical proximity correction mask shapes in response to the counter value exceeding the maximum predetermined number of iterations. A normalized image log slope (NILS) extraction is performed on the set of target shapes and use the set of lithographic contours to produce NILS values. The set of target patterns is modified based on the NILS values in response to the NILS values failing to be within a predetermined limit. The steps are repeated until the NILS values are within the predetermined limit.
摘要翻译：提供了用于光刻布局的基于模型的重新定位的机制。对预定次数的迭代的一组目标图案执行光学邻近校正，直到计数器值超过最大预定迭代次数为了产生一组光学邻近校正掩模形状。响应于计数器值超过最大预定迭代次数，针对所述一组光学邻近校正掩模形状中的每一个生成一组光刻轮廓。在目标形状集上执行归一化图像对数斜率（NILS）提取，并使用该组光刻轮廓来产生NILS值。基于NILS值响应于NILS值不能在预定限度内修改目标模式集合。重复这些步骤，直到NILS值在预定限度内。

2. 发明申请

US20120317523A1 Reducing Through Process Delay Variation in Metal Wires 有权
标题翻译：通过金属线的过程延迟变化减少
公开(公告)号：US20120317523A1
公开(公告)日：2012-12-13
申请号：US13157909
申请日：2011-06-10
申请人： Kanak B. Agarwal , Shayak Banerjee , Sani R. Nassif
发明人： Kanak B. Agarwal , Shayak Banerjee , Sani R. Nassif
IPC分类号： G06F17/50
CPC分类号： G03F1/70
摘要： A mechanism is provided for reducing through process delay variation in metal wires by layout retargeting. The mechanism performs initial retargeting, decomposition, and resolution enhancement techniques. For example, the mechanism may perform optical proximity correction. The mechanism then performs lithographic simulation and optical rules checking. The mechanism provides retargeting rules developed based on coupling lithography simulation and resistance/capacitance (RC) extraction. The mechanism performs RC extraction to capture non-linear dependency of RC on design shape dimensions. If the electrical properties in the lithographic simulation are within predefined specifications, the mechanism accepts the retargeting rules; however, if the electrical properties from RC extraction are outside the predefined specifications, the mechanism modifies the retargeting rules and repeats resolution enhancement techniques.
摘要翻译：提供了一种通过布局重新定位来减少金属线中的工艺延迟变化的机制。该机制执行初始重定向，分解和分辨率增强技术。例如，该机构可以执行光学邻近校正。该机制进行光刻模拟和光学规则检查。该机制提供了基于耦合光刻模拟和电阻/电容（RC）提取开发的重定向规则。该机制执行RC提取以捕获RC对设计形状尺寸的非线性依赖性。如果光刻仿真中的电性能在预定义的规格范围内，则该机制接受重定向规则; 然而，如果来自RC提取的电性能超出预定义的规范，则该机制修改重定向规则并重复分辨率增强技术。

3. 发明授权

US08321818B2 Model-based retargeting of layout patterns for sub-wavelength photolithography 有权
标题翻译：用于亚波长光刻的布局图案的基于模型的重新定位
公开(公告)号：US08321818B2
公开(公告)日：2012-11-27
申请号：US12492301
申请日：2009-06-26
申请人： Kanak B. Agarwal , Shayak Banerjee , Sani R. Nassif
发明人： Kanak B. Agarwal , Shayak Banerjee , Sani R. Nassif
IPC分类号： G06F17/50
CPC分类号： G03F1/36
摘要： Mechanism are provided for model-based retargeting of photolithographic layouts. An optical proximity correction is performed on a set of target patterns for a predetermined number of iterations until a counter value exceeds a maximum predetermined number of iterations in order to produce a set of optical proximity correction mask shapes. A set of lithographic contours is generated for each of the set of optical proximity correction mask shapes in response to the counter value exceeding the maximum predetermined number of iterations. A normalized image log slope (NILS) extraction is performed on the set of target shapes and use the set of lithographic contours to produce NILS values. The set of target patterns is modified based on the NILS values in response to the NILS values failing to be within a predetermined limit. The steps are repeated until the NILS values are within the predetermined limit.
摘要翻译：提供了用于光刻布局的基于模型的重新定位的机制。对预定次数的迭代的一组目标图案执行光学邻近校正，直到计数器值超过最大预定迭代次数为了产生一组光学邻近校正掩模形状。响应于计数器值超过最大预定迭代次数，针对所述一组光学邻近校正掩模形状中的每一个生成一组光刻轮廓。在目标形状集上执行归一化图像对数斜率（NILS）提取，并使用该组光刻轮廓来产生NILS值。基于NILS值响应于NILS值不能在预定限度内修改目标模式集合。重复这些步骤，直到NILS值在预定限度内。

4. 发明授权

US08402398B2 Reducing through process delay variation in metal wires 有权
标题翻译：通过金属线中的工艺延迟变化减少
公开(公告)号：US08402398B2
公开(公告)日：2013-03-19
申请号：US13157909
申请日：2011-06-10
申请人： Kanak B. Agarwal , Shayak Banerjee , Sani R. Nassif
发明人： Kanak B. Agarwal , Shayak Banerjee , Sani R. Nassif
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G03F1/70
摘要： A mechanism is provided for reducing through process delay variation in metal wires by layout retargeting. The mechanism performs initial retargeting, decomposition, and resolution enhancement techniques. For example, the mechanism may perform optical proximity correction. The mechanism then performs lithographic simulation and optical rules checking. The mechanism provides retargeting rules developed based on coupling lithography simulation and resistance/capacitance (RC) extraction. The mechanism performs RC extraction to capture non-linear dependency of RC on design shape dimensions. If the electrical properties in the lithographic simulation are within predefined specifications, the mechanism accepts the retargeting rules; however, if the electrical properties from RC extraction are outside the predefined specifications, the mechanism modifies the retargeting rules and repeats resolution enhancement techniques.
摘要翻译：提供了一种通过布局重新定位来减少金属线中的工艺延迟变化的机制。该机制执行初始重定向，分解和分辨率增强技术。例如，该机构可以执行光学邻近校正。该机制进行光刻模拟和光学规则检查。该机制提供了基于耦合光刻模拟和电阻/电容（RC）提取开发的重定向规则。该机制执行RC提取以捕获RC对设计形状尺寸的非线性依赖性。如果光刻仿真中的电性能在预定义的规格范围内，则该机制接受重定向规则; 然而，如果来自RC提取的电性能超出预定义的规范，则该机制修改重定向规则并重复分辨率增强技术。

5. 发明授权

US08782573B2 Solutions for retargeting integrated circuit layouts based on diffraction pattern analysis 失效
$Solutions for retargeting integrated circuit layouts based on diffraction pattern analysis$
标题翻译：基于衍射图案分析的重新定位集成电路布局的解决方案
公开(公告)号：US08782573B2
公开(公告)日：2014-07-15
申请号：US13600319
申请日：2012-08-31
申请人： Kanak B. Agarwal , Shayak Banerjee
发明人： Kanak B. Agarwal , Shayak Banerjee
IPC分类号： G06F17/50
CPC分类号： G03F7/70441
摘要： A computer-implemented method for retargeting an Integrated Circuit (IC) layout is disclosed. In one embodiment, the method includes generating a diffraction pattern for the IC layout including a set of diffraction-orders, the IC layout including a set of features defined by a set of target edges, analyzing the diffraction pattern with a merit function to estimate printability of the IC layout, monitoring a change in value of the merit function as a position of at least one of the set of target edges is adjusted across a range, and retargeting the set of target edges based on the monitoring of the merit function.
摘要翻译：公开了一种用于重新定位集成电路（IC）布局的计算机实现的方法。在一个实施例中，该方法包括生成包括一组衍射级的IC布局的衍射图案，该IC布局包括由一组目标边缘定义的一组特征，用优点函数分析衍射图案以估计可印刷性的IC布局，监视优值函数的值的变化作为所述一组目标边缘中的至少一个的位置在一个范围内被调整，并且基于所述优值函数的监视来重新定位所述一组目标边缘。

6. 发明授权

US08647893B1 Method for post decomposition density balancing in integrated circuit layouts, related system and program product 有权
标题翻译：集成电路布局中后分解密度平衡的方法，相关系统和程序产品
公开(公告)号：US08647893B1
公开(公告)日：2014-02-11
申请号：US13596126
申请日：2012-08-28
申请人： Kanak B. Agarwal , Shayak Banerjee , Lars W. Liebmann
发明人： Kanak B. Agarwal , Shayak Banerjee , Lars W. Liebmann
IPC分类号： H01L21/66
CPC分类号： H01L22/12 , G05B19/41835 , G06F17/5081 , H01L2924/0002 , Y02P90/265 , H01L2924/00
摘要： Embodiments of the invention provide a method of modifying a decomposed integrated circuit (IC) layout. The method includes providing a decomposed IC layout, the decomposed IC layout including a set of colors; determining a density of each color in the decomposed IC layout, wherein each color includes a plurality of features formed by a related exposure; separating the decomposed IC layout into a set of tiles; determining a first color with a minimum density in one tile of the set of tiles and a second color with a maximum density in tile, the first color including a first set of first features and the second color including a first set of second features; and replacing the first set of second features on the tile with a second set of first features, and the first set of first features on the tile with a second set of second features.
摘要翻译：本发明的实施例提供了一种修改分解的集成电路（IC）布局的方法。该方法包括提供分解的IC布局，分解的IC布局包括一组颜色; 确定分解的IC布局中的每种颜色的浓度，其中每种颜色包括通过相关曝光形成的多个特征; 将分解的IC布局分离成一组瓦片; 确定所述瓦片组中的一个瓦片中具有最小密度的第一颜色和具有瓦片中最大密度的第二颜色，所述第一颜色包括第一组第一特征，所述第二颜色包括第一组第二特征; 以及用第二组第一特征替换所述瓦片上的所述第一组第二特征，以及所述瓦片上的所述第一组第一特征具有第二组第二特征。

7. 发明申请

US20140065728A1 METHOD FOR POST DECOMPOSITION DENSITY BALANCING IN INTEGRATED CIRCUIT LAYOUTS, RELATED SYSTEM AND PROGRAM PRODUCT 有权
标题翻译：一体化电路中分解密度平衡的方法，相关系统和程序产品
公开(公告)号：US20140065728A1
公开(公告)日：2014-03-06
申请号：US13596126
申请日：2012-08-28
申请人： Kanak B. Agarwal , Shayak Banerjee , Lars W. Liebmann
发明人： Kanak B. Agarwal , Shayak Banerjee , Lars W. Liebmann
IPC分类号： H01L21/66 , G05B19/418
CPC分类号： H01L22/12 , G05B19/41835 , G06F17/5081 , H01L2924/0002 , Y02P90/265 , H01L2924/00
摘要： Embodiments of the invention provide a method of modifying a decomposed integrated circuit (IC) layout. The method includes providing a decomposed IC layout, the decomposed IC layout including a set of colors; determining a density of each color in the decomposed IC layout, wherein each color includes a plurality of features formed by a related exposure; separating the decomposed IC layout into a set of tiles; determining a first color with a minimum density in one tile of the set of tiles and a second color with a maximum density in tile, the first color including a first set of first features and the second color including a first set of second features; and replacing the first set of second features on the tile with a second set of first features, and the first set of first features on the tile with a second set of second features.
摘要翻译：本发明的实施例提供了一种修改分解的集成电路（IC）布局的方法。该方法包括提供分解的IC布局，分解的IC布局包括一组颜色; 确定分解的IC布局中的每种颜色的浓度，其中每种颜色包括通过相关曝光形成的多个特征; 将分解的IC布局分离成一组瓦片; 确定所述瓦片组中的一个瓦片中具有最小密度的第一颜色和具有瓦片中最大密度的第二颜色，所述第一颜色包括第一组第一特征，所述第二颜色包括第一组第二特征; 以及用第二组第一特征替换所述瓦片上的所述第一组第二特征，以及所述瓦片上的所述第一组第一特征具有第二组第二特征。

8. 发明申请

US20120040280A1 Simultaneous Optical Proximity Correction and Decomposition for Double Exposure Lithography 有权
标题翻译：双曝光平版印刷的同时光学接近校正和分解
公开(公告)号：US20120040280A1
公开(公告)日：2012-02-16
申请号：US12856208
申请日：2010-08-13
申请人： Kanak B. Agarwal , Shayak Banerjee
发明人： Kanak B. Agarwal , Shayak Banerjee
IPC分类号： G03F7/20 , G03B27/42
CPC分类号： G03F7/70433 , G03F1/36 , G03F7/70441 , G03F7/70466
摘要： A mechanism is provided for simultaneous optical proximity correction (OPC) and decomposition for double exposure lithography. The mechanism begins with two masks that are equal to each other and to the target. The mechanism simultaneously optimizes both masks to obtain a wafer image that both matches the target and is robust to process variations. The mechanism develops a lithographic cost function that optimizes for contour fidelity as well as robustness to variation. The mechanism minimizes the cost function using gradient descent. The gradient descent works on analytically evaluating the derivative of the cost function with respect to mask movement for both masks. It then moves the masks by a fraction of the derivative.
摘要翻译：提供了用于同时光学邻近校正（OPC）和用于双曝光光刻的分解的机制。该机制以两个彼此相等并且与目标相同的掩模开始。该机制同时优化两个掩模以获得两者匹配目标并且对于处理变化是鲁棒的晶片图像。该机制开发出光刻成本函数，优化轮廓保真度以及变化的鲁棒性。该机制使用梯度下降最小化成本函数。梯度下降用于分析评估两个掩模相对于掩模移动的成本函数的导数。然后将掩模移动一部分衍生物。

9. 发明申请

US20110150343A1 Optical Proximity Correction for Transistors Using Harmonic Mean of Gate Length 失效
标题翻译：使用栅极长度的谐波均值的晶体管的光学接近校正
公开(公告)号：US20110150343A1
公开(公告)日：2011-06-23
申请号：US12645627
申请日：2009-12-23
申请人： Kanak B. Agarwal , Shayak Banerjee
发明人： Kanak B. Agarwal , Shayak Banerjee
IPC分类号： G06K9/48
CPC分类号： G06K9/48 , G03F1/36 , G03F7/70441
摘要： A mechanism is provided for harmonic mean optical proximity correction (HMOPC). A lithographic simulator in a HMOPC mechanism generates an image of a mask shape based on a target shape on a wafer thereby forming one or more lithographic contours. A cost function evaluator module determines a geometric cost function associated with the one or more lithographic contours. An edge movement module minimizes the geometric cost function thereby forming a minimized geometric cost function. The edge movement module determines a set of edge movements for each slice in a set of slices associated with the one or more lithographic contours using the minimized geometric cost function. The edge movement module moves the edges of the mask shape using the set of edge movements for each slice in the set of slices. The HMOPC mechanism then produces a clean mask shape using the set of edge movements.
摘要翻译：提供了一种用于谐波平均光学邻近校正（HMOPC）的机制。 HMOPC机构中的光刻模拟器基于晶片上的目标形状产生掩模形状的图像，从而形成一个或多个平版轮廓。成本函数评估器模块确定与一个或多个平版轮廓相关联的几何成本函数。边缘移动模块最小化几何成本函数，从而形成最小化的几何成本函数。边缘移动模块使用最小化的几何成本函数确定与一个或多个平版印刷轮廓相关联的一组切片中的每个切片的一组边缘移动。边缘移动模块使用该组切片中的每个切片的边缘移动集来移动掩模形状的边缘。然后，HMOPC机构使用一组边缘移动产生干净的掩模形状。

10. 发明授权

US08627244B2 Frequency domain layout decomposition in double patterning lithography 失效
标题翻译：双图案光刻中的频域布局分解
公开(公告)号：US08627244B2
公开(公告)日：2014-01-07
申请号：US13171513
申请日：2011-06-29
申请人： Kanak B. Agarwal , Shayak Banerjee
发明人： Kanak B. Agarwal , Shayak Banerjee
IPC分类号： G06F17/50
CPC分类号： G03F7/70466
摘要： A mechanism is provided for frequency domain layout decomposition in double pattern lithography (DPL) based on Fourier coefficient optimization (FCO). The Fourier transform of a layout represents the spatial frequency terms present in the layout. The mechanism models decomposed patterns for two exposures as a function of the corresponding Fourier coefficients. For each exposure, the mechanism sets the corresponding Fourier coefficients to zero for spatial frequency terms greater than the cut-off frequency of the optical system. The mechanism then optimizes non-zero Fourier coefficients for the two exposures to decompose the original target. The mechanism provides frequency domain optimization instead of conventional spatial domain methods, which naturally leads to optics-aware decomposition and stitch insertion in arbitrary two dimensional patterns.
摘要翻译：基于傅里叶系数优化（FCO）的双模式光刻（DPL）中的频域布局分解提供了一种机制。布局的傅里叶变换表示布局中存在的空间频率项。机制模型将两次曝光的分解模式作为相应的傅里叶系数的函数。对于每次曝光，机构将相应的傅立叶系数设置为零，以使空间频率项大于光学系统的截止频率。然后，该机制优化用于两次曝光的非零傅立叶系数以分解原始目标。该机制提供频域优化，而不是传统的空间域方法，这自然导致光学感知分解和针脚插入任意二维模式。

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