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1. 发明授权

US06621325B2 Structures and methods for selectively applying a well bias to portions of a programmable device 有权
标题翻译：用于选择性地将井偏压施加到可编程设备的部分的结构和方法
公开(公告)号：US06621325B2
公开(公告)日：2003-09-16
申请号：US09956203
申请日：2001-09-18
申请人： Michael J. Hart , Steven P. Young , Daniel Gitlin , Hua Shen , Stephen M. Trimberger
发明人： Michael J. Hart , Steven P. Young , Daniel Gitlin , Hua Shen , Stephen M. Trimberger
IPC分类号： H03K301
CPC分类号： H03K19/17792 , G06F17/5054 , H01L27/0928 , H01L27/11807
摘要： Structures and methods for selectively applying a well bias to only those portions of a PLD where such a bias is necessary or desirable, e.g., applying a positive well bias to transistors on critical paths within a user's design. A substrate for an integrated circuit includes a plurality of wells, each of which can be independently and programmably biased with the same or a different well bias voltage. In one embodiment, FPGA implementation software automatically determines the critical paths and generates a configuration bitstream that enables positive well biasing only for the transistors participating in the critical paths, or only for programmable logic elements (e.g., CLBs or lookup tables) containing those transistors. In another embodiment, negative well biasing is selectively applied to reduce leakage current.
摘要翻译：用于选择性地将阱偏压施加到PLD的那些需要或期望的偏置的那些部分的结构和方法，例如在用户设计中的关键路径上的晶体管施加正的阱偏置。用于集成电路的衬底包括多个阱，每个阱可以以相同或不同的阱偏置电压独立地且可编程地偏置。在一个实施例中，FPGA实现软件自动地确定关键路径并且生成配置比特流，其使得能够仅对参与关键路径的晶体管施加正阱偏置，或仅对包含那些晶体管的可编程逻辑元件（例如，CLB或查找表）进行偏置。在另一个实施例中，选择性地施加负阱偏置以减少泄漏电流。

2. 发明授权

US06777978B2 Structures and methods for selectively applying a well bias to portions of a programmable device 有权
公开(公告)号：US06777978B2
公开(公告)日：2004-08-17
申请号：US10624617
申请日：2003-07-21
申请人： Michael J. Hart , Steven P. Young , Stephen M. Trimberger
发明人： Michael J. Hart , Steven P. Young , Stephen M. Trimberger
IPC分类号： H03K19173
CPC分类号： H03K19/17792 , G06F17/5054 , H01L27/0928 , H01L27/11807
摘要： Structures and methods for selectively applying a well bias to only those portions of a PLD where such a bias is necessary or desirable, e.g., applying a positive well bias to transistors on critical paths within a user's design. A substrate for an integrated circuit includes a plurality of wells, each of which can be independently and programmably biased with the same or a different well bias voltage. In one embodiment, FPGA implementation software automatically determines the critical paths and generates a configuration bitstream that enables positive well biasing only for the transistors participating in the critical paths, or only for programmable logic elements (e.g., CLBs or lookup tables) containing those transistors. In another embodiment, negative well biasing is selectively applied to reduce leakage current.

3. 发明授权

US07089527B2 Structures and methods for selectively applying a well bias to portions of a programmable device 有权
公开(公告)号：US07089527B2
公开(公告)日：2006-08-08
申请号：US10853982
申请日：2004-05-25
申请人： Michael J. Hart , Steven P. Young , Stephen M. Trimberger
发明人： Michael J. Hart , Steven P. Young , Stephen M. Trimberger
IPC分类号： G06F17/50
CPC分类号： H03K19/17792 , G06F17/5054 , H01L27/0928 , H01L27/11807
摘要： Structures and methods for selectively applying a well bias to only those portions of a PLD where such a bias is necessary or desirable, e.g., applying a positive well bias to transistors on critical paths within a user's design. A substrate for an integrated circuit includes a plurality of wells, each of which can be independently and programmably biased with the same or a different well bias voltage. In one embodiment, FPGA implementation software automatically determines the critical paths and generates a configuration bitstream that enables positive well biasing only for the transistors participating in the critical paths, or only for programmable logic elements (e.g., CLBs or lookup tables) containing those transistors. In another embodiment, negative well biasing is selectively applied to reduce leakage current.

4. 发明授权

US5844844A FPGA memory element programmably triggered on both clock edges 失效
标题翻译：可编程地在两个时钟沿触发FPGA存储单元
公开(公告)号：US5844844A
公开(公告)日：1998-12-01
申请号：US890951
申请日：1997-07-09
申请人： Trevor J. Bauer , Stephen M. Trimberger , Steven P. Young
发明人： Trevor J. Bauer , Stephen M. Trimberger , Steven P. Young
IPC分类号： G11C11/41 , G11C11/412 , G11C7/00
CPC分类号： G11C11/412 , G11C11/41
摘要： A programmable memory element clocks in new data on both rising and falling edges of the clock, thereby optionally operating at twice the frequency of the distributed clock. The circuit according to the invention comprises two latches, one rising edge triggered and one falling edge triggered. One of these latches, each time the clock changes state, latches in a new value. When configured as a dual-edge flip-flop, the output of the inactive latch is fed forward to drive the output of the memory element. In one embodiment, the outputs of the two latches are multiplexed together and the clock selects the active output. According to a first embodiment of the invention, the memory element is used in an FPGA and can be programmed to function as either a latch or a dual-edge flip-flop. A second embodiment of the invention comprises a third latch. Based on the contents of a configuration memory cell, two of the three latches are selected to form a flip-flop. One such flip-flop is dual-edge, the other is single-edge. Further embodiments incorporate programmable variations of latches and flip-flops responsive to either or both clock edges.
摘要翻译：可编程存储器元件在时钟的上升沿和下降沿的新数据中进行时钟，从而可选地以分布式时钟的两倍的频率工作。根据本发明的电路包括两个锁存器，一个上升沿触发和一个下降沿触发。这些锁存器中的一个，每当时钟改变状态时，锁存一个新的值。当配置为双边沿触发器时，非活动锁存器的输出向前馈送以驱动存储器元件的输出。在一个实施例中，两个锁存器的输出被多路复用在一起，并且时钟选择有效输出。根据本发明的第一实施例，存储器元件在FPGA中使用，并且可以被编程为用作锁存器或双边沿触发器。本发明的第二实施例包括第三锁存器。基于配置存储单元的内容，选择三个锁存器中的两个形成触发器。一个这样的触发器是双边缘的，另一个是单边缘。另外的实施例结合了一个或两个时钟沿的锁存器和触发器的可编程变化。

5. 发明授权

US08966253B1 Method and apparatus for authenticating a programmable device bitstream 有权
标题翻译：用于认证可编程设备比特流的方法和装置
公开(公告)号：US08966253B1
公开(公告)日：2015-02-24
申请号：US12791668
申请日：2010-06-01
申请人： Stephen M. Trimberger
发明人： Stephen M. Trimberger
IPC分类号： H04L29/06 , G06F9/30
CPC分类号： H04L63/123 , G06F9/30145 , G06F21/572 , G06F21/76
摘要： A method and apparatus for authenticating a bitstream used to configure programmable devices are described. In an example, the bitstream is received via a configuration port of the programmable device, the bitstream including instructions for programming configuration registers of the programmable device and at least one embedded message authentication code (MAC). At least a portion of the instructions is initially stored in a memory of the programmable device without programming the configuration registers. At least one actual MAC is computed based on the bitstream using a hash algorithm. The at least one actual MAC is compared with the at least one embedded MAC, respectively. Each instruction stored in the memory is executed to program the configuration registers until any one of the at least one actual MAC is not the same as a corresponding one of the at least one embedded MAC, after which any remaining instructions in the memory are not executed.
摘要翻译：描述用于认证用于配置可编程设备的比特流的方法和装置。在一个示例中，经由可编程设备的配置端口接收比特流，比特流包括用于编程可编程设备的配置寄存器和至少一个嵌入式消息认证码（MAC）的指令。指令的至少一部分最初被存储在可编程设备的存储器中，而不对配置寄存器进行编程。使用散列算法基于比特流计算至少一个实际的MAC。将至少一个实际的MAC分别与至少一个嵌入式MAC进行比较。执行存储在存储器中的每个指令以对配置寄存器进行编程，直到至少一个实际MAC中的任何一个与至少一个嵌入式MAC中的对应的一个不相同，之后不执行存储器中的任何剩余指令。

6. 发明授权

US08909941B1 Programmable integrated circuit and a method of enabling the detection of tampering with data provided to a programmable integrated circuit 有权
标题翻译：可编程集成电路和一种能够检测篡改提供给可编程集成电路的数据的方法
公开(公告)号：US08909941B1
公开(公告)日：2014-12-09
申请号：US13077814
申请日：2011-03-31
申请人： Stephen M. Trimberger
发明人： Stephen M. Trimberger
IPC分类号： G06F21/00
CPC分类号： H04L63/1466 , G06F21/64 , G06F21/76
摘要： A method of enabling detection of tampering with data provided to a programmable integrated circuit is described. The method comprises modifying a portion of the data to establish randomness in the data; and inserting, by a computer, a redundancy check value in the portion, wherein the redundancy check value is based upon the modified portion of the data. A programmable integrated circuit is also described.
摘要翻译：描述了能够检测到提供给可编程集成电路的数据的篡改的方法。该方法包括修改数据的一部分以在数据中建立随机性; 并且由计算机插入所述部分中的冗余校验值，其中所述冗余校验值基于所述数据的修改部分。还描述了可编程集成电路。

7. 发明授权

US08416950B1 Copy protection without non-volatile memory 有权
标题翻译：复制保护，不带非易失性存储器
公开(公告)号：US08416950B1
公开(公告)日：2013-04-09
申请号：US13082271
申请日：2011-04-07
申请人： Stephen M. Trimberger
发明人： Stephen M. Trimberger
IPC分类号： H04L29/06
CPC分类号： H04L9/0866
摘要： An integrated circuit includes a fingerprint element and a decryption circuit. The fingerprint element generates a fingerprint, where the fingerprint is reproducible and represents an inherent manufacturing process characteristic unique to the integrated circuit device. The decryption circuit decrypts, using a decryption key that is based on the fingerprint, an encrypted data in order to extract data. In one embodiment, the propagation delay of various circuit elements are used to generate the fingerprint. In another embodiment, the specific frequency of an oscillator is used to generate the fingerprint. In yet another embodiment, a ratio of measurable values is used to generate the fingerprint. In another embodiment, differences in transistor threshold voltages are used to generate the fingerprint. In yet another embodiment, variations in line widths are used to generate the fingerprint.
摘要翻译：集成电路包括指纹元件和解密电路。指纹元件产生指纹，其中指纹是可重现的，并且表示集成电路设备独有的固有制造工艺特性。解密电路使用基于指纹的解密密钥解密加密数据，以提取数据。在一个实施例中，各种电路元件的传播延迟被用于产生指纹。在另一个实施例中，使用振荡器的特定频率来生成指纹。在另一个实施例中，使用可测量值的比例来生成指纹。在另一个实施例中，晶体管阈值电压的差异用于产生指纹。在另一个实施例中，使用线宽的变化来生成指纹。

8. 发明授权

US08104012B1 System and methods for reducing clock power in integrated circuits 有权
标题翻译：集成电路中降低时钟功率的系统和方法
公开(公告)号：US08104012B1
公开(公告)日：2012-01-24
申请号：US12363721
申请日：2009-01-31
申请人： Matthew H. Klein , Edward S. McGettigan , Stephen M. Trimberger , James M. Simkins , Brian D. Philofsky , Subodh Gupta
发明人： Matthew H. Klein , Edward S. McGettigan , Stephen M. Trimberger , James M. Simkins , Brian D. Philofsky , Subodh Gupta
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5054 , G06F2217/62
摘要： Dynamic power savings and efficient use of resources are achieved in a programmable logic device (PLD) such as a field programmable gate array (FPGA) or complex programmable logic device (CPLD) by receiving a design netlist specifying a circuit including clock signals, clock buffers, clock enable signals and synchronous elements, examining the design netlist to identify synchronous elements coupled to common clock and clock enable signals, cutting the clock signals to the synchronous elements to form a modified design netlist, inserting gated clock buffers into the modified netlist to output gated clock signals to the synchronous elements, responsive to the clock enable signals, and performing placement and routing on the modified netlist. A system for performing the method on an EDA tool is provided. The methods may be provided as executable instructions stored on a computer readable medium which cause a programmable processor to perform the methods.
摘要翻译：在诸如现场可编程门阵列（FPGA）或复杂可编程逻辑器件（CPLD）的可编程逻辑器件（PLD）中实现动态功率节省和资源的有效利用，通过接收指定包括时钟信号，时钟缓冲器的电路的设计网表，时钟使能信号和同步元件，检查设计网表以识别耦合到公共时钟和时钟使能信号的同步元件，将时钟信号切割到同步元件以形成修改后的设计网表，将门控时钟缓冲器插入修改的网表以输出门控时钟信号到同步元件，响应于时钟使能信号，并在修改的网表上执行放置和布线。提供了一种用于在EDA工具上执行该方法的系统。可以将这些方法提供为存储在计算机可读介质上的可执行指令，其使可编程处理器执行该方法。

9. 发明授权

US07979826B1 Computer-readable storage media comprising data streams having mixed mode data correction capability 有权
标题翻译：包括具有混合模式数据校正能力的数据流的计算机可读存储介质
公开(公告)号：US07979826B1
公开(公告)日：2011-07-12
申请号：US11820938
申请日：2007-06-21
申请人： Stephen M. Trimberger
发明人： Stephen M. Trimberger
IPC分类号： G06F17/50 , H03M13/00
CPC分类号： G06F17/5054
摘要： Methods of providing error correction in configuration bitstreams for programmable logic devices (PLDs). While any error correction method can be used, in one embodiment a Hamming code is applied to instructions in the configuration bitstream, while a product code is applied to configuration data. Thus, the higher overhead required for a Hamming code applies to only a few words in the bitstream. The instructions are corrected on receipt of the word that includes the Hamming code, so the instructions are executed correctly even if a transmission error has occurred. However, configuration data can be stored in the configuration memory without correction. With a product code, the exact location of an erroneous bit is not known until the end of the transmission, when a parity word is received. At this time, the PLD can go back and correct erroneous bits in the configuration data prior to enabling the newly loaded design.
摘要翻译：在可编程逻辑器件（PLD）的配置比特流中提供纠错的方法。虽然可以使用任何纠错方法，但是在一个实施例中，将汉明码应用于配置比特流中的指令，同时将产品代码应用于配置数据。因此，汉明码所需的较高开销仅适用于比特流中的几个字。在接收到包含汉明码的单词时纠正指令，因此即使发生传输错误，指令也能正确执行。然而，配置数据可以存储在配置存储器中而不进行校正。使用产品代码，当接收到奇偶校验字时，直到发送结束，才知道错误位的确切位置。此时，在启用新加载的设计之前，PLD可以返回并纠正配置数据中的错误位。

10. 发明授权

US07853916B1 Methods of using one of a plurality of configuration bitstreams for an integrated circuit 有权
标题翻译：使用多个配置比特流中的一个用于集成电路的方法
公开(公告)号：US07853916B1
公开(公告)日：2010-12-14
申请号：US11974355
申请日：2007-10-11
申请人： Stephen M. Trimberger , Babak Ehteshami
发明人： Stephen M. Trimberger , Babak Ehteshami
IPC分类号： G06F17/50 , H03K19/00 , H03K17/693
CPC分类号： H03K17/693
摘要： Methods of using one of a plurality of configuration bitstreams in an integrated circuit are disclosed. An exemplary method comprises analyzing the plurality of implementations of a design to determine initial variations in timing among the implementations; modifying the implementations to reduce the variations in timing among the implementations; and outputting a plurality of configuration bitstreams for the implementations having variations in timing that are reduced relative to the initial variations in timing. Another method comprises generating a plurality of implementations for the design; generating a cost function for the design based upon costs (e.g., collision penalties) derived from at least two of the plurality of implementations; determining a cost for each implementation based upon the cost function; optimizing an implementation of the design by minimizing the cost of the implementation; generating a plurality of configuration bitstreams for the plurality of implementations; and outputting the plurality of configuration bitstreams.
摘要翻译：公开了在集成电路中使用多个配置比特流中的一个的方法。一种示例性方法包括分析设计的多个实现以确定实现中的定时的初始变化; 修改实现以减少实现中的时序变化; 以及输出多个配置比特流，用于具有相对于初始定时变化而减小的定时变化的实现。另一种方法包括为设计生成多个实现; 基于从所述多个实现中的至少两个导出的成本（例如，冲突惩罚），为所述设计生成成本函数; 根据成本函数确定每个实现的成本; 通过最小化实施成本来优化设计的实施; 为所述多个实现产生多个配置比特流; 并输出多个配置比特流。

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