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1. 发明授权

US5880620A Pass gate circuit with body bias control 失效
标题翻译：通过门电路与体偏置控制
公开(公告)号：US5880620A
公开(公告)日：1999-03-09
申请号：US840582
申请日：1997-04-22
申请人： Daniel Gitlin , Sheau-Suey Li , Martin L. Voogel , Tiemin Zhao
发明人： Daniel Gitlin , Sheau-Suey Li , Martin L. Voogel , Tiemin Zhao
IPC分类号： G11C5/14 , H03K17/06 , H03K3/01
CPC分类号： G11C5/146 , H03K17/063 , H03K2217/0018
摘要： A pass gate circuit includes a pass transistor and a body bias control circuit for biasing the body of the pass transistor to reduce body effect. The body bias control circuit includes one or more control transistors arranged to selectively connect the substrate (body) of the pass transistor to the drain or gate of the pass transistor when predetermined voltages are applied to the drain and gate of the pass transistor. As a result, the pass transistor exhibits a reduced body effect in the on-state. In one embodiment, the body bias control circuit includes a first control transistor having a drain and gate connected to the gate of the pass transistor, a gate connected to the drain of the pass transistor, and a source. The body bias control circuit also includes a second control transistor having a drain connected to the source of the first control transistor, a source connected to a body of the pass transistor, and a gate connected to the drain of the pass transistor. The bodies of the pass transistor, first control transistor and second control transistor are electrically interconnected. With this arrangement, the body of the pass transistor is biased "high" by the gate of the pass transistor only when both the gate and drain of the pass transistor are at a high voltage level.
摘要翻译：通路电路包括通过晶体管和体偏置控制电路，用于偏置通过晶体管的主体以减小体效应。体偏置控制电路包括一个或多个控制晶体管，其布置成当预定电压施加到传输晶体管的漏极和栅极时，选择性地将传输晶体管的衬底（主体）连接到传输晶体管的漏极或栅极。结果，通过晶体管在导通状态下表现出减小的体效应。在一个实施例中，体偏置控制电路包括第一控制晶体管，其具有连接到传输晶体管的栅极的漏极和栅极，连接到传输晶体管的漏极的栅极和源极。体偏置控制电路还包括第二控制晶体管，其具有连接到第一控制晶体管的源极的漏极，连接到传输晶体管的主体的源极和连接到通过晶体管的漏极的栅极。传输晶体管，第一控制晶体管和第二控制晶体管的主体电互连。通过这种布置，只有当传输晶体管的栅极和漏极都处于高电压电平时，传输晶体管的主体被传输晶体管的栅极偏置“高”。

2. 发明授权

US06549458B1 Non-volatile memory array using gate breakdown structures 有权
标题翻译：使用门击穿结构的非易失性存储器阵列
公开(公告)号：US06549458B1
公开(公告)日：2003-04-15
申请号：US10040044
申请日：2001-10-25
申请人： Kameswara K. Rao , Martin L. Voogel , James Karp , Shahin Toutounchi , Michael J. Hart , Daniel Gitlin , Kevin T. Look , Jongheon Jeong , Radko G. Bankras
发明人： Kameswara K. Rao , Martin L. Voogel , James Karp , Shahin Toutounchi , Michael J. Hart , Daniel Gitlin , Kevin T. Look , Jongheon Jeong , Radko G. Bankras
IPC分类号： G11C1400
CPC分类号： G11C16/08
摘要： Memory cell structures and related circuitry for use in non-volatile memory devices can be fabricated utilizing standard CMOS processes, for example, 0.18 micron or 0.15 micron processes. Advantageously, the cell structures can be programmed so that a conductive path is formed between like type materials, for example, between a p-type gate and a p-type source/drain region or an n-type gate and an n-type source/drain region. Programming cells in this manner advantageously provides a programmed cell having a low, linear resistance after programming.
摘要翻译：用于非易失性存储器件的存储器单元结构和相关电路可以使用标准CMOS工艺制造，例如0.18微米或0.15微米工艺。有利地，单元结构可以被编程，使得导电路径形成在类型材料之间，例如在p型栅极和p型源极/漏极区域之间或n型栅极和n型源极 /漏区。以这种方式编程单元有利地在编程之后提供具有低线性电阻的编程单元。

3. 发明授权

US06522582B1 Non-volatile memory array using gate breakdown structures 有权
标题翻译：使用门击穿结构的非易失性存储器阵列
公开(公告)号：US06522582B1
公开(公告)日：2003-02-18
申请号：US09553571
申请日：2000-04-19
申请人： Kameswara K. Rao , Martin L. Voogel , James Karp , Shahin Toutounchi , Michael J. Hart , Daniel Gitlin , Kevin T. Look , Jongheon Jeong , Radko G. Bankras
发明人： Kameswara K. Rao , Martin L. Voogel , James Karp , Shahin Toutounchi , Michael J. Hart , Daniel Gitlin , Kevin T. Look , Jongheon Jeong , Radko G. Bankras
IPC分类号： G11C1400
CPC分类号： G11C16/08
摘要： Memory cell structures and related circuitry for use in non-volatile memory devices are described. The cell structures can be fabricated utilizing standard CMOS processes, e.g. sub 0.35 micron or sub 0.25 micron processes. Preferably, the cell structures can be fabricated using 0.18 micron or 0.15 micron standard CMOS processes. Advantageously, the cell structures can be programmed so that a conductive path is formed between like type materials. For example, in certain cell structures a cell is programmed by applying a programming voltage in such a way as to form a conductive path between a p-type gate and a p-type source/drain region or an n-type gate and an n-type source/drain region. Programming cells in this manner advantageously provides a programmed cell having a low, linear resistance after programming. In addition, novel charge pump circuits are provided that, in a preferred embodiment, are located “on chip” with an array of memory cells. These charge pump circuits are preferably fabricated utilizing the same standard CMOS processing techniques that were utilized to form the memory cell structures and related circuitry.
摘要翻译：描述了用于非易失性存储器件的存储单元结构和相关电路。可以使用标准CMOS工艺制造电池结构，例如次0.35微米或次级0.25微米工艺。优选地，可以使用0.18微米或0.15微米标准CMOS工艺制造电池结构。有利地，电池结构可以被编程，使得在相似类型的材料之间形成导电路径。例如，在某些单元结构中，通过施加编程电压来编程单元，以便在p型栅极和p型源极/漏极区域或n型栅极和n型栅极之间形成导电路径型源极/漏极区域。以这种方式编程单元有利地在编程之后提供具有低线性电阻的编程单元。此外，提供了新颖的电荷泵电路，在优选实施例中，它们以“存储器”阵列位于芯片上。这些电荷泵电路优选地利用用于形成存储器单元结构和相关电路的相同的标准CMOS处理技术来制造。

4. 发明授权

US07283409B1 Data monitoring for single event upset in a programmable logic device 有权
标题翻译：可编程逻辑器件中单事件不正常的数据监控
公开(公告)号：US07283409B1
公开(公告)日：2007-10-16
申请号：US11503824
申请日：2006-08-14
申请人： Martin L. Voogel , David P. Schultz , Vasisht M. Vadi , Philip D. Costello , Venu M. Kondapalli
发明人： Martin L. Voogel , David P. Schultz , Vasisht M. Vadi , Philip D. Costello , Venu M. Kondapalli
IPC分类号： G11C29/00 , G01R31/28
CPC分类号： H03K19/17748 , H03K19/17732 , H03K19/1776
摘要： Method and apparatus for data monitoring for error detection is described. A programmable logic device includes a configurable logic block having function generators, each of which is configurable for at least two programmable mode functions. The function generators are coupled to an array of memory cells for storing configuration bits for configuring the function generators. A primary address line is coupled to each memory cell spanning two or more of the function generators. A secondary address line is coupled to groups of memory cells associated with the function generators. A mask circuit is configured to selectively communicate a signal of the primary address line to a segment of the secondary address line or to a ground responsive in part to the program mode function.
摘要翻译：描述用于错误检测的数据监视的方法和装置。可编程逻辑器件包括具有功能发生器的可配置逻辑块，其中每一个可配置用于至少两个可编程模式功能。功能发生器耦合到存储器单元阵列，用于存储用于配置功能发生器的配置位。主地址线耦合到跨越两个或更多个函数发生器的每个存储器单元。辅助地址线耦合到与功能发生器相关联的存储器单元组。掩模电路被配置为部分地响应于程序模式功能选择性地将主地址线的信号传送到辅助地址线的一个段或地址。

5. 发明授权

US07119570B1 Method of measuring performance of a semiconductor device and circuit for the same 有权
标题翻译：测量半导体器件性能的方法及其电路
公开(公告)号：US07119570B1
公开(公告)日：2006-10-10
申请号：US10836850
申请日：2004-04-30
申请人： Manoj Chirania , Venu M. Kondapalli , Martin L. Voogel , Philip Costello
发明人： Manoj Chirania , Venu M. Kondapalli , Martin L. Voogel , Philip Costello
IPC分类号： G01R31/26
CPC分类号： G01R31/31708 , G01R31/31725
摘要： A test circuit to test rise delay/fall delay performance on a semiconductor device may comprise a latch to latch data at its input responsive to a clock signal. The latch may source an output signal related to the data latched. A buffer chain may be configured to serially propagate the signal sourced by the latch from the latch output back to the clock input, as the clock signal. A reset/set input of the latch may be configured to receive a reset/set signal from an intermediate node of the buffer chain.
摘要翻译：用于测试半导体器件上升延迟/下降延迟性能的测试电路可以包括锁存器，用于响应于时钟信号在其输入端锁存数据。锁存器可以输出与被锁存的数据相关的输出信号。作为时钟信号，缓冲链可以被配置为将由锁存器产生的信号从锁存器输出串行传播回到时钟输入。锁存器的复位/置位输入可被配置为从缓冲器链的中间节点接收复位/置位信号。

6. 发明授权

US06949951B1 Integrated circuit multiplexer including transistors of more than one oxide thickness 有权
标题翻译：集成电路多路复用器包括多于一个氧化物厚度的晶体管
公开(公告)号：US06949951B1
公开(公告)日：2005-09-27
申请号：US10869777
申请日：2004-06-15
申请人： Steven P. Young , Michael J. Hart , Venu M. Kondapalli , Martin L. Voogel
发明人： Steven P. Young , Michael J. Hart , Venu M. Kondapalli , Martin L. Voogel
IPC分类号： G06F7/38 , H03K17/00 , H03K17/693 , H03K19/177
CPC分类号： H03K17/005 , H03K17/693 , H03K19/17736 , H03K19/1778
摘要： A multiplexer that can be used, for example, in a programmable logic device (PLD). The multiplexer includes a plurality of pass transistors passing a selected one of several input values to an internal node, which drives a buffer that provides the multiplexer output signal. The pass transistors can be controlled, for example, by values stored in memory cells of a PLD. The pass transistors have a first oxide thickness and are controlled by a value having a first operating voltage. The buffer includes transistors having a second and thinner oxide thickness, and is operated at a second and lower operating voltage. Where memory cells are used to control the pass transistors, the memory cells include transistors having the first oxide thickness and operate at the first operating voltage. Some embodiments also include transistors of varying gate length for each of the pass transistors, buffer transistors, and memory cell transistors.
摘要翻译：可以用于例如可编程逻辑器件（PLD）中的多路复用器。多路复用器包括将多个输入值中选择的一个输入值传送到内部节点的多个传输晶体管，驱动提供多路复用器输出信号的缓冲器。可以例如通过存储在PLD的存储器单元中的值来控制传输晶体管。传输晶体管具有第一氧化物厚度并且由具有第一工作电压的值控制。缓冲器包括具有第二和较薄氧化物厚度的晶体管，并且在第二和较低工作电压下操作。在使用存储器单元来控制传输晶体管的情况下，存储单元包括具有第一氧化物厚度并在第一工作电压下工作的晶体管。一些实施例还包括用于每个传输晶体管，缓冲晶体管和存储单元晶体管的栅极长度变化的晶体管。

7. 发明授权

US06509739B1 Method for locating defects and measuring resistance in a test structure 有权
标题翻译：在测试结构中定位缺陷和测量电阻的方法
公开(公告)号：US06509739B1
公开(公告)日：2003-01-21
申请号：US09709184
申请日：2000-11-08
申请人： Martin L. Voogel , Leon Ly Nguyen , Narasimhan Vasudevan
发明人： Martin L. Voogel , Leon Ly Nguyen , Narasimhan Vasudevan
IPC分类号： G01R3128
CPC分类号： H01L22/34 , G01R31/026 , G01R31/316 , H01L2924/0002 , H01L2924/00
摘要： A test structure provides defect information rapidly and accurately. The test structure includes a plurality of lines provided in a parallel orientation, a decoder coupled to the plurality of lines for selecting one of the plurality of lines, and a sense amplifier coupled to the selected line. To analyze an open, a line in the test structure is coupled to the sense amplifier. A high input signal is provided to the line. To determine the resistance of the open, a plurality of reference voltages are then provided to the sense amplifier. A mathematical model of the resistance of the line based on the reference voltage provided to the sense amplifier is generated. Using this mathematical model, the test structure can quickly detect and characterize defect levels down to a few parts-per-million at minimal expense.
摘要翻译：测试结构快速准确地提供缺陷信息。测试结构包括以平行取向提供的多条线，耦合到多条线的解码器，用于选择多条线中的一条线;以及读出放大器，耦合到所选择的线。为了分析开路，测试结构中的一条线耦合到读出放大器。线路上提供高输入信号。为了确定开路的电阻，然后将多个参考电压提供给读出放大器。产生基于提供给读出放大器的参考电压的线路的电阻的数学模型。使用这种数学模型，测试结构可以以最小的成本快速检测和表征缺陷水平，达到百万分之几。

8. 发明授权

US5959821A Triple-well silicon controlled rectifier with dynamic holding voltage 失效
标题翻译：具有动态保持电压的三重可控硅整流器
公开(公告)号：US5959821A
公开(公告)日：1999-09-28
申请号：US109479
申请日：1998-07-02
申请人： Martin L. Voogel
发明人： Martin L. Voogel
IPC分类号： H01L27/02 , H02H9/04 , H02H3/22
CPC分类号： H01L27/0251 , H02H9/046
摘要： An electrostatic discharge (ESD) protection circuit for an IC device including a triple-well SCR and a control circuit connected between the triple-well SCR and ground. The triple-well SCR is implemented using triple-well CMOS technology to facilitate connection of the control circuit by isolating both terminals of the triple-well SCR from ground. The control circuit includes a switch circuit, a capacitor, or a combination thereof, for controlling the holding voltage of the triple-well SCR. The switch circuit is closed during non-operation (i.e., before power is applied to the IC device protected by the SCR) so that electrostatic discharge (ESD) energy is transmitted to ground through the triple-well SCR. Similarly, the capacitor transmits ESD pulses to ground during ESD events. During normal operation of the IC device, the switch circuit is controlled by system voltage to remain open. In contrast, the capacitor is charged when a voltage pulse triggers the triple-well SCR during normal IC operation, thereby reliably switching off the triple-well SCR by decreasing the voltage across the SCR below the holding voltage.
摘要翻译：一种用于IC器件的静电放电（ESD）保护电路，包括三阱SCR和连接在三阱SCR与地之间的控制电路。使用三阱CMOS技术实现三阱SCR，以通过将三阱SCR的两个端子与地相隔离来促进控制电路的连接。控制电路包括用于控制三阱SCR的保持电压的开关电路，电容器或其组合。在非操作期间（即，在被SCR保护的IC器件被施加电力之前），开关电路闭合，使得静电放电（ESD）能量通过三阱SCR传输到地。类似地，电容器在ESD事件期间将ESD脉冲发送到地。在IC器件的正常工作期间，开关电路由系统电压控制以保持开路。相比之下，当在正常IC操作期间电压脉冲触发三阱SCR时，电容器被充电，从而通过将SCR两端的电压降低到保持电压以下，从而可靠地关闭三阱SCR。

9. 发明授权

US07859918B1 Method and apparatus for trimming die-to-die variation of an on-chip generated voltage reference 有权
标题翻译：用于修整片上产生的参考电压的芯片到芯片的变化的方法和装置
公开(公告)号：US07859918B1
公开(公告)日：2010-12-28
申请号：US12577502
申请日：2009-10-12
申请人： Leon L. Nguyen , Martin L. Voogel
发明人： Leon L. Nguyen , Martin L. Voogel
IPC分类号： G11C7/00
CPC分类号： G11C5/147 , G05F3/242
摘要： A method and apparatus is provided for the implementation of a measurement and adjustment mechanism within a semiconductor die that facilitates adjustment of the magnitude of voltage generated by one or more voltage reference generation circuits on the die. In a first embodiment, the output voltage magnitude of a bandgap reference circuit may be measured and adjusted. In a second embodiment, the output voltage magnitude of a voltage regulator circuit may be measured and adjusted. Programmable circuit elements, such as programmable resistors, may first be programmed during a configuration event of the die to determine the optimal configuration settings of the one or more voltage reference generation circuits. The optimal configuration settings are then used to program the state of one or more eFuses to maintain the optimal configuration settings for the duration of the semiconductor die's lifetime.
摘要翻译：提供了一种用于实现半导体管芯内的测量和调节机构的方法和装置，其有助于调节由管芯上的一个或多个电压基准产生电路产生的电压的大小。在第一实施例中，可以测量和调整带隙基准电路的输出电压幅度。在第二实施例中，可以测量和调整电压调节器电路的输出电压幅值。可编程电路元件（例如可编程电阻器）可以首先在芯片的配置事件期间被编程以确定一个或多个电压基准产生电路的最佳配置设置。然后，最佳配置设置用于编程一个或多个eFuse的状态，以在半导体芯片的使用寿命期间保持最佳配置设置。

10. 发明授权

US07452765B1 Single event upset in SRAM cells in FPGAs with high resistivity gate structures 有权
标题翻译：在具有高电阻率栅极结构的FPGA中的SRAM单元中的单事件不正常
公开(公告)号：US07452765B1
公开(公告)日：2008-11-18
申请号：US11242409
申请日：2005-09-30
申请人： Martin L. Voogel , Austin H. Lesea , Joseph J. Fabula , Carl H. Carmichael , Shahin Toutounchi , Michael J. Hart , Steven P. Young , Kevin T. Look , Jan L. de Jong
发明人： Martin L. Voogel , Austin H. Lesea , Joseph J. Fabula , Carl H. Carmichael , Shahin Toutounchi , Michael J. Hart , Steven P. Young , Kevin T. Look , Jan L. de Jong
IPC分类号： H01L21/8238
CPC分类号： H01L27/11803 , H01L21/76831 , H01L21/76834 , H01L27/11
摘要： SEU-hardening series resistances loads are formed within the gate structures of cross-coupled inverters of a latch. For some embodiments, the gate contact for the input of each cross-coupled inverter has a sufficiently high resistance to provide the SEU-hardening series resistance. For other embodiments, a conductive trace layer coupled to the input of each cross-coupled inverter includes a high-resistivity portion that provides the SEU-hardening series resistance.
摘要翻译： SEU硬化串联电阻负载形成在锁存器的交叉耦合反相器的栅极结构内。对于一些实施例，用于每个交叉耦合的反相器的输入的栅极接触具有足够高的电阻以提供SEU-硬化串联电阻。对于其他实施例，耦合到每个交叉耦合的反相器的输入的导电迹线层包括提供SEU硬化串联电阻的高电阻部分。

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