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1. 发明授权

US4811063A JMOS transistor utilizing polysilicon sinks 失效
标题翻译：使用多晶硅槽的JMOS晶体管
公开(公告)号：US4811063A
公开(公告)日：1989-03-07
申请号：US110453
申请日：1987-10-20
申请人： Stephen J. Valeri , Kailash C. Jain , Bernard A. MacIver
发明人： Stephen J. Valeri , Kailash C. Jain , Bernard A. MacIver
IPC分类号： H01L29/78 , H01L29/80
CPC分类号： H01L29/7827 , H01L29/7838
摘要： JMOS depletion mode transistors include back-to-back junctions in the doped polysilicon layer that serves as the gate. The polysilicon layer includes a first region of the same conductivity type as the channel in contact with the channel, and a second region, of the same conductivity type as the channel and to which the gate potential is applied, spaced apart by a region of the opposite conductivity type that serves as a sink for minority carriers in the channel. Both buried oxide layer and recessed gate JMOS transistors are included.
摘要翻译： JMOS耗尽型晶体管包括用作栅极的掺杂多晶硅层中的背对点结。多晶硅层包括与沟道接触的沟道类型相同的导电类型的第一区域，以及与沟道相同的导电类型的第二区域，栅极电位施加到该第二区域，作为通道中的少数载体的吸收器的相反导电类型。包括埋氧层和凹栅JMOS晶体管。

2. 发明授权

US4786952A High voltage depletion mode MOS power field effect transistor 失效
标题翻译：高电压耗尽型MOS功率场效应晶体管
公开(公告)号：US4786952A
公开(公告)日：1988-11-22
申请号：US888697
申请日：1986-07-24
申请人： Bernard A. MacIver , Kailash C. Jain
发明人： Bernard A. MacIver , Kailash C. Jain
IPC分类号： H01L29/78 , H01L27/10
CPC分类号： H01L29/7838 , H01L29/7827
摘要： A vertical depletion mode power field effect transistor having a greatly increased drain-to-source breakdown voltage. The drain region is formed in the substrate and separated from the channel by a first insulative layer having apertures which allow the passage of electrical currents. The channel, which is formed between the first insulative layer and a second insulative layer parallel to the substrate surface, contains both a source region, formed by implantation of impurities of the same type as are used to form the drain region, and a gate region. In this configuration, the normally high voltage which exists between the gate and drain is imposed over a greater distance than in conventional depletion mode vertical FETs, so that this new configuration produces vertical power FETs having much higher breakdown voltages than do conventional depletion mode vertical FETs. Islands having a conductivity type opposite to that used to form the source region are formed immediately below the second insulative layer and serve to prevent the creation of a charge inversion layer in the channel, where the inversion layer adversely affects the turn off characteristic of the j-MOS power transistor.
摘要翻译：具有大大增加的漏极 - 源极击穿电压的垂直耗尽型功率场效应晶体管。漏极区域形成在衬底中并且通过具有允许电流通过的孔的第一绝缘层与沟道分离。形成在第一绝缘层和平行于衬底表面的第二绝缘层之间的沟道包含通过注入与用于形成漏极区的相同类型的杂质形成的源极区域和栅极区域。在这种配置中，存在于栅极和漏极之间的正常高电压施加在比传统的耗尽型垂直FET中更大的距离上，使得这种新的配置产生具有比传统的耗尽型垂直FET更高的击穿电压的垂直功率FET 。具有与用于形成源极区域的导电类型相反的导电类型的岛形成在第二绝缘层的正下方，并且用于防止在沟道中产生电荷反转层，其中反型层不利地影响j的截止特性 -MOS功率晶体管。

3. 发明授权

US4746960A Vertical depletion-mode j-MOSFET 失效
标题翻译：垂直耗尽型j-MOSFET
公开(公告)号：US4746960A
公开(公告)日：1988-05-24
申请号：US77742
申请日：1987-07-27
申请人： Stephen J. Valeri , Bernard A. MacIver , Kailash C. Jain
发明人： Stephen J. Valeri , Bernard A. MacIver , Kailash C. Jain
IPC分类号： H01L29/78 , H01L29/786 , H01L29/80
CPC分类号： H01L29/78612 , H01L29/7827 , H01L29/7838 , H01L29/78642
摘要： A vertical j-MOSFET useful as a power transistor includes a two-dimensional array of square cells in which a small fraction of the cells are replaced by a double-junction sink useful for collecting the minority carriers in the channel regions that normally will accumulate at each interface of the gate electrode and channel region.
摘要翻译：可用作功率晶体管的垂直j-MOSFET包括方形单元的二维阵列，其中一小部分单元被用于收集通常将在栅极电极和沟道区域的每个界面。

4. 发明授权

US4800170A Process for forming in a silicon oxide layer a portion with vertical side walls 失效
标题翻译：在氧化硅层中形成具有垂直侧壁的部分的工艺
公开(公告)号：US4800170A
公开(公告)日：1989-01-24
申请号：US104091
申请日：1987-10-02
申请人： Kailash C. Jain , Bernard A. MacIver
发明人： Kailash C. Jain , Bernard A. MacIver
IPC分类号： H01L21/033 , H01L21/265 , H01L21/266 , H01L21/311 , H01L21/425 , H01L21/467
CPC分类号： H01L21/033 , H01L21/26533 , H01L21/26586 , H01L21/266 , H01L21/31111
摘要： A process for forming a buried patterned silicon oxide layer in a silicon chip in which the layer is formed by implanting oxygen into the chip through a mask of silicon oxide on the surface of the silicon chip. The silicon oxide mask is formed to have essentially vertical side walls by interposing an irradiation step between a pair of isotropic wet etching steps in its formation.
摘要翻译：一种用于在硅芯片中形成掩埋图案化氧化硅层的工艺，其中通过在硅芯片的表面上通过氧化硅掩模将氧注入到芯片中形成该层。氧化硅掩模通过在其形成中的一对各向同性湿蚀刻步骤之间插入照射步骤而形成为具有基本上垂直的侧壁。

5. 发明授权

US4652334A Method for patterning silicon dioxide with high resolution in three dimensions 失效
标题翻译：三维图案二氧化硅分辨率高的方法
公开(公告)号：US4652334A
公开(公告)日：1987-03-24
申请号：US836900
申请日：1986-03-06
申请人： Kailash C. Jain , Bernard A. MacIver
发明人： Kailash C. Jain , Bernard A. MacIver
IPC分类号： C03C15/00 , C03C23/00 , H01L21/311 , H01L21/3115 , B44C1/22 , C03C25/06
CPC分类号： C03C23/0055 , C03C15/00 , H01L21/31111 , H01L21/31155
摘要： A method is provided for selectively etching ion-implanted silicon dioxide. A masked silicon dioxide layer is exposed to an ion beam of controlled dose and energy. The mask is removed and the silicon dioxide layer is brought in contact with an aqueous ammoniacal hydrogen peroxide solution which preferentially removes the ion-bombarded region with minimal etching of the unimplanted silicon dioxide.
摘要翻译：提供了一种选择性蚀刻离子注入二氧化硅的方法。掩蔽的二氧化硅层暴露于受控剂量和能量的离子束。除去掩模，并且使二氧化硅层与氨过氧化氢水溶液接触，该氨水过氧化氢溶液优先除去未被注入的二氧化硅的蚀刻，从而优先除去离子轰击区域。

6. 发明授权

US4321317A High resolution lithography system for microelectronic fabrication 失效
标题翻译：用于微电子制造的高分辨率光刻系统
公开(公告)号：US4321317A
公开(公告)日：1982-03-23
申请号：US144578
申请日：1980-04-28
申请人： Bernard A. MacIver
发明人： Bernard A. MacIver
IPC分类号： G03F1/56 , G03F1/78 , G03F7/039 , G03F7/20 , B05D3/06 , G03C5/00
CPC分类号： G03F1/78 , G03F1/56 , G03F7/039 , G03F7/2063 , Y10S430/143
摘要： Master and working photomasks are made using a photoresist darkened on and bonded to respective quartz substrates. The working photomask is formed by deep ultraviolet light exposure through an electron beam patterned master mask. Deep ultraviolet light is also used to pattern a resist on a silicon slice through the working mask. The same resist is preferably used on the slice and both masks.
摘要翻译：主和工作光掩模使用在相应的石英基板上变暗并粘合到其上的光致抗蚀剂制成。工作光掩模由深紫外光照射通过电子束图案化主掩模形成。深紫外光也用于通过工作面罩对硅片上的抗蚀剂进行图案化。优选在切片和两个掩模上使用相同的抗蚀剂。

7. 发明授权

US4554208A Metal bearing surface having an adherent score-resistant coating 失效
标题翻译：金属轴承表面具有粘附的耐分层涂层
公开(公告)号：US4554208A
公开(公告)日：1985-11-19
申请号：US674239
申请日：1984-11-23
申请人： Bernard A. MacIver , James C. Erskine, Jr. , John C. Bierlein
发明人： Bernard A. MacIver , James C. Erskine, Jr. , John C. Bierlein
IPC分类号： B29C35/08 , B29C37/00 , B29C59/16 , C23C26/00 , B32B9/00 , B05D3/06
CPC分类号： B29C59/16 , B29C37/0078 , C23C26/00 , B29C2035/0872 , Y10T428/12458 , Y10T428/26 , Y10T428/30 , Y10T428/31699
摘要： A bearing element having an adherent score-resistant coating on its surface comprising a carbonized layer of an organic resin in which the layer is carbonized by ion implantation. The ion implantation is controlled to not only provide graphite-like and diamond-like structures in the carbonized coating but to also produce chemical bonding between carbon atoms of the resultant coating and atoms of the bearing surface.
摘要翻译：在其表面上具有贴附耐光泽涂层的承载元件包括有机树脂的碳化层，其中该层通过离子注入碳化。控制离子注入不仅在碳化涂层中提供石墨状和类金刚石结构，而且在所得涂层的碳原子和支承表面的原子之间产生化学键合。

8. 发明授权

US4144100A Method of low dose phoshorus implantation for oxide passivated diodes in <10> P-type silicon 失效
标题翻译：在{21 100 {22 {0 P型硅）中的氧化物钝化二极管的低剂量磷光体注入方法
公开(公告)号：US4144100A
公开(公告)日：1979-03-13
申请号：US856643
申请日：1977-12-02
申请人： Bernard A. MacIver , Eugene Greenstein
发明人： Bernard A. MacIver , Eugene Greenstein
IPC分类号： H01L21/265 , H01L21/316 , H01L7/54
CPC分类号： H01L21/02238 , H01L21/02255 , H01L21/26506 , H01L21/26513 , H01L21/31662
摘要： Low dosage phosphorus implantation regions in P-type silicon are subjected to a severe damage implant with halogen or silicon ions, preferably fluorine and chlorine. This permits anneal in a strongly oxidizing atmosphere for PN junction passivation, without concurrently inducing PN junction leakage. Oxide passivated PN junctions are formed having leakages as low as when the low dose phosphorus implants are annealed in other atmospheres, or are formed in silicon.
摘要翻译： <100> P型硅中的低剂量磷注入区域用卤素或硅离子（优选氟和氯）进行严重损伤植入。这允许在强氧化气氛中退火以进行PN结钝化，而不会同时诱发PN结泄漏。形成氧化物钝化的PN结，其泄漏低于当低剂量磷植入物在其它气氛中退火或者在<111>硅中形成时的泄漏。

9. 发明授权

US4133701A Selective enhancement of phosphorus diffusion by implanting halogen ions 失效
标题翻译：通过植入卤素离子来选择性增强磷的扩散
公开(公告)号：US4133701A
公开(公告)日：1979-01-09
申请号：US810929
申请日：1977-06-29
申请人： Eugene Greenstein , Bernard A. MacIver
发明人： Eugene Greenstein , Bernard A. MacIver
IPC分类号： H01L21/225 , H01L21/265 , H01L29/167 , H01L21/263 , H01L27/02
CPC分类号： H01L21/26506 , H01L21/2252 , H01L29/167 , Y10S148/128
摘要： An improved method of making bipolar monolithic integrated circuits by successive diffusions of boron and phosphorus. Selective halogen ion implantation is used to locally specifically enhance phosphorus diffusion. The halogen implant is performed prior to the boron diffusion. Enhanced local phosphorus diffusion provides selected transistors in the circuit with a narrower base width than others, and a corresponding higher current gain than others. Analogously, higher value pinch resistors can be selectively produced in the circuit.
摘要翻译：通过硼和磷的连续扩散制造双极单片集成电路的改进方法。选择性卤素离子注入用于局部特异性增强磷扩散。在硼扩散之前进行卤素注入。增强的局部磷扩散在电路中提供选择的晶体管，其基极宽度比其他晶体窄，并且相应的电流增益比其它晶体管高。类似地，可以在电路中选择性地产生更高价值的钳式电阻器。

10. 发明授权

US4769685A Recessed-gate junction-MOS field effect transistor 失效
标题翻译：嵌入栅结MOS场效应晶体管
公开(公告)号：US4769685A
公开(公告)日：1988-09-06
申请号：US923583
申请日：1986-10-27
申请人： Bernard A. MacIver , James C. Erskine
发明人： Bernard A. MacIver , James C. Erskine
IPC分类号： H01L29/78 , H01L27/02 , H01L29/06 , H01L29/50
CPC分类号： H01L29/7827
摘要： An insulated gate field effect transistor of the depletion mode type has a recessed gate structure with opposed gate sections on opposite sides of adjacent bar-like structures defined in a channel region. An opposite conductivity-type island in the channel region is electrically connected to the transistor gate electrode. A voltage applied to the gate electrode generates an electric field effect which extends from the opposed gate sections into said bar-like structures creating opposed depletion regions which modulate channel current. The gate voltage simultaneously biases the island to enhance the gate electric field effect by removing minority charge carriers which would otherwise accumulate in the bar-like structures.
摘要翻译：耗尽型绝缘栅场效应晶体管具有凹陷栅极结构，在沟道区域中定义的相邻条状结构的相对侧上具有相对的栅极部分。沟道区中的相反导电型岛与晶体管栅极电连接。施加到栅电极的电压产生从相对的栅极部分延伸到所述棒状结构中的电场效应，产生调制通道电流的相反的耗尽区域。栅极电压同时偏置岛，以通过去除否则将积聚在棒状结构中的少数电荷载流子来增强栅极电场效应。

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