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    • 3. 发明授权
    • High voltage depletion mode MOS power field effect transistor
    • 高电压耗尽型MOS功率场效应晶体管
    • US4786952A
    • 1988-11-22
    • US888697
    • 1986-07-24
    • Bernard A. MacIverKailash C. Jain
    • Bernard A. MacIverKailash C. Jain
    • H01L29/78H01L27/10
    • H01L29/7838H01L29/7827
    • A vertical depletion mode power field effect transistor having a greatly increased drain-to-source breakdown voltage. The drain region is formed in the substrate and separated from the channel by a first insulative layer having apertures which allow the passage of electrical currents. The channel, which is formed between the first insulative layer and a second insulative layer parallel to the substrate surface, contains both a source region, formed by implantation of impurities of the same type as are used to form the drain region, and a gate region. In this configuration, the normally high voltage which exists between the gate and drain is imposed over a greater distance than in conventional depletion mode vertical FETs, so that this new configuration produces vertical power FETs having much higher breakdown voltages than do conventional depletion mode vertical FETs. Islands having a conductivity type opposite to that used to form the source region are formed immediately below the second insulative layer and serve to prevent the creation of a charge inversion layer in the channel, where the inversion layer adversely affects the turn off characteristic of the j-MOS power transistor.
    • 具有大大增加的漏极 - 源极击穿电压的垂直耗尽型功率场效应晶体管。 漏极区域形成在衬底中并且通过具有允许电流通过的孔的第一绝缘层与沟道分离。 形成在第一绝缘层和平行于衬底表面的第二绝缘层之间的沟道包含通过注入与用于形成漏极区的相同类型的杂质形成的源极区域和栅极区域 。 在这种配置中,存在于栅极和漏极之间的正常高电压施加在比传统的耗尽型垂直FET中更大的距离上,使得这种新的配置产生具有比传统的耗尽型垂直FET更高的击穿电压的垂直功率FET 。 具有与用于形成源极区域的导电类型相反的导电类型的岛形成在第二绝缘层的正下方,并且用于防止在沟道中产生电荷反转层,其中反型层不利地影响j的截止特性 -MOS功率晶体管。