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1. 发明申请

WO2008038236A2 A MULTI-TRANSISTOR BASED NON-VOLATILE MEMORY CELL WITH DUAL THRESHOLD VOLTAGE 审中-公开
标题翻译：具有双阈值电压的基于多晶体管的非易失性存储器单元
公开(公告)号：WO2008038236A2
公开(公告)日：2008-04-03
申请号：PCT/IB2007/053911
申请日：2007-09-26
申请人： NXP B.V. , SLOTBOOM, Michiel , VAN DUUREN, Michiel, J. , AKIL, Nader , VAN SCHAIJK, Robertus, T., F. , HUERTA, Almudena
发明人： SLOTBOOM, Michiel , VAN DUUREN, Michiel, J. , AKIL, Nader , VAN SCHAIJK, Robertus, T., F. , HUERTA, Almudena
IPC分类号： H01L21/336 , H01L29/792 , G11C16/04 , H01L21/8247 , H01L27/115 , H01L21/28 , H01L29/788
CPC分类号： H01L27/11568 , G11C16/0466 , H01L21/28273 , H01L21/28282 , H01L27/115 , H01L27/11524 , H01L29/66825 , H01L29/66833 , H01L29/7881 , H01L29/792
摘要： A multi-transistor based non- volatile memory cell Ml arranged on a semiconductor substrate 1 includes at least one access transistor ATI; AT2; AT2'; AT2" and at least one memory transistor TM2a; TM2b; TM2c; TM2d. The at least one access transistor is a "normally-off ' transistor and includes first and second diffusion regions Sl, S2, an access channel region Rl, and an access gate AG. The access channel region is intermediate the first and second diffusion regions. The at least one memory transistor includes third and fourth diffusion regions S2, S3, a channel region R2, a charge trapping element O1-N-O2 and a control gate CG. The channel region is intermediate the third and fourth diffusion regions, and the charge trapping element is above the channel region with the control gate being arranged above the charge trapping element. The semiconductor substrate is of a first conductivity type. The at least one memory transistor is provided with a memory threshold voltage window with an upper limit above and a lower limit below zero Volt.
摘要翻译：布置在半导体衬底1上的基于多晶体管的非易失性存储器单元M1包括至少一个存取晶体管ATI; AT2; AT2' ; AT2＆QUOT; 和至少一个存储晶体管TM2a; TM2b; TM2C; TM2d。该至少一个存取晶体管是“常关”晶体管并且包括第一和第二扩散区域S1，S2，存取沟道区域R1和存取门AG。进入通道区域位于第一和第二扩散区域的中间。该至少一个存储晶体管包括第三和第四扩散区域S2，S3，沟道区域R2，电荷俘获元件O1-N-O2和控制栅极CG。沟道区位于第三和第四扩散区的中间，并且电荷俘获元件位于沟道区之上，控制栅极布置在电荷俘获元件之上。半导体衬底是第一导电类型。所述至少一个存储器晶体管设置有存储器阈值电压窗口，其具有高于上限的上限和低于零的低于下限的电压。

2. 发明申请

WO2007135632A2 SONOS MEMORY DEVICE AND METHOD OF OPERATING A SONOS MEMORY DEVICE 审中-公开
标题翻译： SONOS存储器件和操作SONOS存储器件的方法
公开(公告)号：WO2007135632A2
公开(公告)日：2007-11-29
申请号：PCT/IB2007/051873
申请日：2007-05-16
申请人： NXP B.V. , VAN DUUREN, Michiel, J. , VAN SCHAIJK, Robertus, T., F. , AKIL, Nader
发明人： VAN DUUREN, Michiel, J. , VAN SCHAIJK, Robertus, T., F. , AKIL, Nader
IPC分类号： G11C16/04 , G11C16/10
CPC分类号： G11C16/0466 , G11C16/10
摘要： The present invention relates to a memory device, hereinafter SONOS memory device, comprising SONOS memory cells having a control gate terminal connected to a SONOS layer stack with a nitride layer, a source terminal and a drain terminal; and a programming unit, which is connected to the drain terminal and to the control gate terminal and which is configured to apply a predetermined positive drain voltage to the drain terminal of the selected SONOS memory cell and a predetermined negative gate voltage to the control gate terminal of the selected SONOS memory cell each upon receiving a programming request addressed to a selected SONOS memory cell, the drain voltage and the gate voltage being suitable for creating hot holes at a drain side of the selected SONOS memory cell in a gate-assisted band-to-band-tunneling process and for injecting the hot holes into the nitride layer of the selected SONOS memory cell, thus switching the selected SONOS memory cell from a high-V T state to a low-V T state.
摘要翻译：本发明涉及一种存储器件，以下称为SONOS存储器件，它包括具有连接到具有氮化物层的SONOS层堆叠的控制栅极端子的SONOS存储器单元，源极端子和漏极端子; 以及编程单元，其连接到所述漏极端子和所述控制栅极端子，并且被配置为向所述控制栅极端子的所选择的SONOS存储单元的漏极端子施加预定的正极漏极电压和预定的负极栅极电压所选择的SONOS存储单元在接收到寻址到所选择的SONOS存储单元的编程请求时，所述漏极电压和栅极电压适于在门辅助带通滤波器中在所选择的SONOS存储器单元的漏极侧产生热孔，并且用于将热孔注入到所选择的SONOS存储单元的氮化物层中，从而将所选择的SONOS存储单元从高V T T S状态切换到低V' SUB> T 状态。

3. 发明申请

WO2007138517A1 ARRAY CONFIGURATION FOR DRAM MEMORY WITH DOUBLE-GATE FLOATING-BODY FINFET CELLS 审中-公开
标题翻译：具有双栅浮动体FINFET电池的DRAM存储器的阵列配置
公开(公告)号：WO2007138517A1
公开(公告)日：2007-12-06
申请号：PCT/IB2007/051874
申请日：2007-05-16
申请人： NXP B.V. , VAN SCHAIJK, Robertus, T., F. , VAN DUUREN, Michiel, J.
发明人： VAN SCHAIJK, Robertus, T., F. , VAN DUUREN, Michiel, J.
IPC分类号： G11C11/404 , H01L29/78
CPC分类号： G11C11/404 , G11C8/14 , G11C2211/4016 , H01L27/108 , H01L27/10802 , H01L27/10823 , H01L27/10826 , H01L29/7841 , H01L29/785
摘要： The present invention relates to a DRAM memory that includes a memory-cell array with FinFETs of the double-gate floating-body type. The FinFETs comprise a fin- shaped region that includes a channel region controlled via a front gate and a floating-body region controlled via a back gate. In the DRAM memory device of the invention, FinFET pairs formed by FinFETs neighboring each other in a first array direction are electrically connected back-gate to back-gate via a respective shared back-gate word line that is routed in a second array direction between the FinFETs of a respective FinFET pair to a respective shared back-gate contact, which is arranged outside the FinFET array. Since FinFET pairs neighboring each other in a first array direction are electrically connected back-gate to back- gate through a respective shared back-gate word line, only one back-gate word line is needed per FinFET pair in the first array direction.
摘要翻译：本发明涉及一种DRAM存储器，其包括具有双栅极浮体型FinFET的存储单元阵列。 FinFET包括鳍形区域，其包括通过前栅极控制的沟道区域和经由背栅极控制的浮动体区域。在本发明的DRAM存储器件中，由FinFET在第一阵列方向上彼此相邻的FinFET对，经由相应的共享背栅极字线电连接到栅极，该栅极在第二阵列方向上被布线在设置在FinFET阵列外部的各自的FinFET对的FinFET到相应的共享背栅极触点。由于在第一阵列方向上彼此相邻的FinFET对通过相应的共用背栅极字线电连接到背栅极，所以在第一阵列方向上每个FinFET对仅需要一个后栅极字线。

4. 发明申请

WO2007069180A1 NON-VOLATILE MEMORY DEVICE HAVING A GAP IN THE TUNNUEL INSULATING LAYER AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：在破坏层中具有差异的非易失性存储器件及其制造方法
公开(公告)号：WO2007069180A1
公开(公告)日：2007-06-21
申请号：PCT/IB2006/054741
申请日：2006-12-11
申请人： NXP B.V. , VAN SCHAIJK, Robertus, T., F. , VAN DUUREN, Michiel, J, .
发明人： VAN SCHAIJK, Robertus, T., F. , VAN DUUREN, Michiel, J, .
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8247 , H01L21/84 , H01L27/115 , H01L27/12 , H01L29/788 , H01L29/792 , H01L29/423 , H01L29/51
CPC分类号： H01L21/28273 , H01L21/28282 , H01L21/84 , H01L27/115 , H01L27/11521 , H01L27/11568 , H01L27/1203 , H01L29/66795 , H01L29/66825 , H01L29/66833 , H01L29/785 , H01L29/7883 , H01L29/792
摘要： A non- volatile memory device (1, 101, 201, 301) having a gap within a tunnel dielectric layer (14, 114, 214, 314) and a method of manufacturing the same is provided. The devices have a stack of layers on top of a substrate (10, 110, 210, 310) including, a charge tunneling layer with a gap (14, 114, 214, 314), a charge storage layer (16, 116, 216, 316), a control gate layer (20, 120, 220, 320) and an insulating layer (18, 118, 218 220) in between the charge storage layer and the control gate. Manufacturing proceeds through deposition of a sacrificial layer (28, 128,228,328) on parts of a substrate, whereupon a stack of layers (24, 124,224,324) including a charge-storage layer, an insulating layer and a control gate layer are formed. Subsequently, selected parts of the sacrificial layer are removed, thereby forming a gap in between the charge storage region and the substrate. The gap is protected from future processing by deposition of a sealing layer (34, 134, 234, 334). Such a device has a reduced operating voltage and its manufacture can be easily implemented in existing semiconductor processes.
摘要翻译：提供了在隧道介电层（14,114,214,314）内具有间隙的非易失性存储器件（1,101,201,301）及其制造方法。这些器件在衬底（10,110,210,310）的顶部上具有一叠层，包括具有间隙（14,114,214,314）的电荷隧道层，电荷存储层（16,116,216），316），控制栅极层（20,120,220,320）和在电荷存储层和控制栅极之间的绝缘层（18,118,218220）。通过在衬底的部分上沉积牺牲层（28,128,228,328）来进行制造，由此形成包括电荷存储层，绝缘层和控制栅极层的层叠层（24,124,224,324）。随后，去除牺牲层的选定部分，从而在电荷存储区域和基板之间形成间隙。通过沉积密封层（34,134,234,334）来保护间隙免于将来的加工。这种器件具有降低的工作电压，并且其制造可以容易地在现有的半导体工艺中实现。

5. 发明申请

WO2008004179A2 NON-VOLATILE MEMORY AND-ARRAY 审中-公开
标题翻译：非易失记忆与阵列
公开(公告)号：WO2008004179A2
公开(公告)日：2008-01-10
申请号：PCT/IB2007/052575
申请日：2007-07-03
申请人： NXP B.V. , VAN DUUREN, Michiel, J. , VAN SCHAIJK, Robertus, T., F.
发明人： VAN DUUREN, Michiel, J. , VAN SCHAIJK, Robertus, T., F.
CPC分类号： G11C16/0475 , H01L27/0207 , H01L27/11568
摘要： A non- volatile memory cell on a semiconductor substrate includes a first and a second transistor. Each transistor is arranged as a memory element that includes two diffusion regions capable of acting as either source or drain, a charge storage element and a control gate element. A channel region is located intermediate the two diffusion regions. The charge storage element is located over the channel region, the control gate element is arranged on top of the charge storage element. One diffusion region of the first transistor and one diffusion region of the second transistor form a common diffusion region. The other diffusion region of the first transistor is connected as first diffusion region to a first bit line, the other diffusion region of the second transistor is connected as second diffusion region to a second bit line and the common diffusion region is connected to a sensing line.
摘要翻译：半导体衬底上的非易失性存储单元包括第一和第二晶体管。每个晶体管被布置为包括能够用作源极或漏极的两个扩散区域，电荷存储元件和控制栅极元件的存储元件。沟道区域位于两个扩散区域的中间。电荷存储元件位于沟道区域之上，控制栅极元件设置在电荷存储元件的顶部。第一晶体管的一个扩散区域和第二晶体管的一个扩散区域形成公共扩散区域。第一晶体管的另一扩散区域作为第一扩散区域连接到第一位线，第二晶体管的另一个扩散区域作为第二扩散区域连接到第二位线，并且公共扩散区域连接到感测线。

6. 发明申请

WO2005124874A1 NON-VOLATILE MEMORY WITH ERASE GATE ON ISOLATION ZONES 审中-公开
标题翻译：具有隔离栅的非易失性存储器在隔离区上
公开(公告)号：WO2005124874A1
公开(公告)日：2005-12-29
申请号：PCT/IB2005/051819
申请日：2005-06-03
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , VAN SCHAIJK, Robertus, T., F. , VAN DUUREN, Michiel, J.
发明人： VAN SCHAIJK, Robertus, T., F. , VAN DUUREN, Michiel, J.
IPC分类号： H01L29/788
CPC分类号： H01L29/7883 , H01L29/42328
摘要： The present invention provides a non-volatile memory device and a method for manufacturing such a device. The device comprises a floating gate (16), a control gate (19) and a separate erase gate (10). The erase gate (10) is provided in or on isolation zones (2) provided in the substrate (1). Because of that, the erase gates (10) do not add to the cell size. The capacitance between the erase gate (10) and the floating gate (16) is small compared with the capacitance between the control gate (19) and the floating gate (16), and the charged floating gate (16) is erased by Fowler-Nordheim tunneling through the oxide layer between the erase gate (10) and the floating gate (16).
摘要翻译：本发明提供一种非易失性存储器件及其制造方法。该装置包括浮动栅极（16），控制栅极（19）和单独的擦除栅极（10）。擦除栅极（10）设置在设置在基板（1）中的隔离区（2）中或隔离区（2）中。因此，擦除门（10）不增加单元大小。擦除栅极（10）和浮动栅极（16）之间的电容与控制栅极（19）和浮动栅极（16）之间的电容相比较小，并且充电的浮置栅极（16）被Fowler- Nordheim穿过擦除栅极（10）和浮动栅极（16）之间的氧化物层。

7. 发明申请

WO2003096431A1 FLOATING GATE MEMORY CELLS WITH INCREASED COUPLING RATIO 审中-公开
标题翻译：具有增加的耦合比的浮栅存储器电池
公开(公告)号：WO2003096431A1
公开(公告)日：2003-11-20
申请号：PCT/IB2003/001485
申请日：2003-04-11
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , VAN DUUREN, Michiel, J. , VAN SCHAIJK, Robertus, T., F.
发明人： VAN DUUREN, Michiel, J. , VAN SCHAIJK, Robertus, T., F.
IPC分类号： H01L29/788
CPC分类号： H01L29/7881 , H01L29/42324
摘要： A method to improve the coupling ratio between a control gate (18) and a floating gate (14) of a floating gate non-volatile semiconductor device is described. In a stacked gate floating gate transistor according to the invention, a conductive spacer (24) is used at both sides of the stack. The conductive spacer (24) is galvanically connected to the control gate (18), preferably by means of a conductive layer (34), whereas it is separated from the floating gate (14) by means of an insulating layer (22). The capacitance (C1, C2) between both conductive spacers (24) and the side walls of the floating gate (14) adds up to the normal capacitance between control gate (18) and floating gate (14).
摘要翻译：描述了一种改善浮动栅极非易失性半导体器件的控制栅极（18）和浮动栅极（14）之间的耦合比的方法。在根据本发明的堆叠栅极浮栅晶体管中，在堆叠的两侧使用导电间隔物（24）。导电间隔物（24）优选通过导电层（34）电连接到控制栅极（18），而通过绝缘层（22）与导电间隔物（24）分离。两个导电间隔物（24）和浮动栅极（14）的侧壁之间的电容（C1，C2）与控制栅极（18）和浮动栅极（14）之间的正常电容相加。

8. 发明申请

WO2006003620A1 METHOD FOR MANUFACTURING AN ELECTRIC DEVICE WITH A LAYER OF CONDUCTIVE MATERIAL CONTACTED BY NANOWIRE 审中-公开
标题翻译：用NANOWIRE接触的导电材料层制造电气装置的方法
公开(公告)号：WO2006003620A1
公开(公告)日：2006-01-12
申请号：PCT/IB2005/052145
申请日：2005-06-28
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , VAN SCHAIJK, Robertus, T., F. , AGARWAL, Prabhat , BAKKERS, Erik, P., A., M. , LANKHORST, Martijn, H., R. , VAN DUUREN, Michiel, J. , BALKENENDE, Abraham, R. , FEINER, Louis, F. , WOERLEE, Pierre, H.
发明人： VAN SCHAIJK, Robertus, T., F. , AGARWAL, Prabhat , BAKKERS, Erik, P., A., M. , LANKHORST, Martijn, H., R. , VAN DUUREN, Michiel, J. , BALKENENDE, Abraham, R. , FEINER, Louis, F. , WOERLEE, Pierre, H.
IPC分类号： H01L21/768
CPC分类号： H01L45/1273 , B82Y10/00 , G11C13/0004 , G11C13/025 , G11C2213/81 , H01L21/28525 , H01L21/76879 , H01L27/2409 , H01L27/2436 , H01L27/2472 , H01L27/2481 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/148 , H01L45/16
摘要： The electric device (100) according to the invention comprises a layer (107) of a memory material which has an electrical resistivity switchable between a first value and a second value. The memory material may be a phase change material. The electric device (100) further comprises a set of nanowires (NW) electrically connecting a first terminal (172) of the electric device and the layer (107) of memory material thereby enabling conduction of an electric current from the first terminal via the nanowires (NW) and the layer (107) of memory material to a second terminal (272) of the electric device. Each nanowire (NW) electrically contacts the layer (107) of memory material in a respective contact area. All contact areas are substantially identical. The method according to the invention is suited to manufacture the electric device (100) according to the invention.
摘要翻译：根据本发明的电子设备（100）包括存储材料的层（107），其具有可在第一值和第二值之间切换的电阻率。记忆材料可以是相变材料。电气设备（100）还包括一组电气连接电气设备的第一端子（172）和存储器材料层（107）的纳米线（NW），从而使得能够经由纳米线从第一端子传导电流（NW）和存储器材料层（107）连接到电气设备的第二端子（272）。每个纳米线（NW）在相应的接触区域中电接触存储器材料的层（107）。所有接触区域基本相同。根据本发明的方法适用于制造根据本发明的电子设备（100）。

9. 发明申请

WO2004077498A2 METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：WO2004077498A2
公开(公告)日：2004-09-10
申请号：PCT/IB2004/050113
申请日：2004-02-13
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , VAN DUUREN, Michiel, J. , VAN SCHAIJK, Robertus, T., F. , PONOMAREV, Youri , HOOKER, Jacob, C.
发明人： VAN DUUREN, Michiel, J. , VAN SCHAIJK, Robertus, T., F. , PONOMAREV, Youri , HOOKER, Jacob, C.
IPC分类号： H01L
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/115 , H01L29/42328 , H01L29/66825
摘要： In the method for manufacturing a semiconductor device (100), which comprises a semiconducting body (1) having a surface (2) with a source region (3) and a drain region (4) defining a channel direction (102) and a channel region (101), a first stack (6) of layers on top of the channel region (101), the first stack (6) comprising, in this order, a tunnel dielectric layer (11), a charge storage layer (10) for storing an electric charge and a control gate layer (9), and a second stack (7) of layers on top of the channel region (101) directly adjacent to the first stack (6) in the channel direction (102), the second stack (7) comprising an access gate layer (14) electrically insulated from the semiconducting body (1) and from the first stack (6), initially a first sacrificial layer (90) is used, which is later replaced by the control gate layer (9). A second sacrificial layer (20) is used to protect the part (82) off the surface (2) adjacent to the second sidewall (81) and opposite to the position (83) of the second stack (7) when providing the access gate layer (14).
摘要翻译：在制造半导体器件（100）的方法中，其包括具有源极区（3）的表面（2）和限定沟道方向（102）的漏极区（4）的半导体（1）和通道区域（101），在沟道区域（101）的顶部上的第一层叠层（6），第一堆叠（6）依次包括隧道介电层（11），电荷存储层（10）用于在通道方向（102）上直接与第一堆叠（6）相邻的通道区域（101）的顶部上存储电荷和控制栅极层（9）以及第二堆叠（7），第二堆叠（7）包括与半导电体（1）和第一堆叠（6）电绝缘的存取栅极层（14），最初使用第一牺牲层（90），其随后由控制栅极层（9）。当提供接入门（20）时，第二牺牲层（20）用于保护邻近第二侧壁（81）的表面（2）并且与第二堆叠（7）的位置（83）相对的部分（82）层（14）。

10. 发明申请

WO2004053992A2 SELF ALIGNED SHALLOW TRENCH ISOLATION WITH IMPROVED COUPLING COEFFICIENT IN FLOATING GATE DEVICES 审中-公开
标题翻译：自动对准在浮动门设备中改进耦合系数的浅层分离
公开(公告)号：WO2004053992A2
公开(公告)日：2004-06-24
申请号：PCT/IB2003/004949
申请日：2003-10-31
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , VAN SCHAIJK, Robertus, T., F. , VAN DUUREN, Michiel, J.
发明人： VAN SCHAIJK, Robertus, T., F. , VAN DUUREN, Michiel, J.
IPC分类号： H01L27/115
CPC分类号： H01L27/11521 , H01L27/115
摘要： The present invention provides a method for manufacturing a floating gate type semiconductor device on a substrate having a surface (2), and a device thus manufactured.The method comprises: - forming, on the substrate surface, a stack comprising an insulating film (4), a first layer of floating gate material (6) and a layer of sacrificial material (8), - forming at least one isolation zone (18) through the stack and into the substrate (2), the first layer of floating gate material (6) thereby having a top surface and side walls (26), - removing the sacrificial material (8), thus leaving a cavity (20) defined by the isolation zones (18) and the top surface of the first layer of floating gate material (6), and filling the cavity (20) with a second layer of floating gate material (22), the first layer of floating gate material (6) and the second layer of floating gate material (22) thus forming together a floating-gate (24).
摘要翻译：本发明提供一种在具有表面（2）的基板上制造浮栅型半导体器件的方法以及如此制造的器件。该方法包括：在衬底表面上形成包括绝缘膜（4）的叠层），第一层浮栅材料（6）和牺牲材料层（8）， - 通过堆叠形成至少一个隔离区（18）并进入衬底（2），第一层浮栅材料（6），从而具有顶表面和侧壁（26）， - 去除所述牺牲材料（8），从而留下由所述隔离区（18）限定的空腔（20）和所述第一浮动栅极的顶表面材料（6），并且用第二层浮栅材料（22）填充空腔（20），第一层浮栅材料（6）和第二层浮栅材料（22）由此形成浮动 -gate（24）。

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