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1. 发明授权

US08530877B2 Non-volatile semiconductor device 有权
标题翻译：非易失性半导体器件
公开(公告)号：US08530877B2
公开(公告)日：2013-09-10
申请号：US13182696
申请日：2011-07-14
申请人： Junya Onishi , Shinobu Yamazaki , Kazuya Ishihara , Yushi Inoue , Yukio Tamai , Nobuyoshi Awaya
发明人： Junya Onishi , Shinobu Yamazaki , Kazuya Ishihara , Yushi Inoue , Yukio Tamai , Nobuyoshi Awaya
IPC分类号： H01L47/00
CPC分类号： H01L45/04 , H01L27/2436 , H01L45/1233 , H01L45/146
摘要： A variable resistance element that can stably perform a switching operation with a property variation being reduced by suppressing a sharp current that accompanies completion of forming process, and a non-volatile semiconductor memory device including the variable resistance element are realized. The non-volatile semiconductor memory device uses the variable resistance element for storing information in which a resistance changing layer is interposed between a first electrode and a second electrode, and a buffer layer is inserted between the first electrode and the resistance changing layer where a switching interface is formed. The buffer layer and the resistance changing layer include n-type metal oxides, and materials of the buffer layer and the resistance changing layer are selected such that energy at a bottom of a conduction band of the n-type metal oxide configuring the buffer layer is lower than that of the n-type metal oxide configuring the resistance changing layer.
摘要翻译：通过抑制伴随着成形处理的完成的尖锐电流，可以稳定地进行具有特性变化的开关动作的可变电阻元件，以及包括该可变电阻元件的非易失性半导体存储器件。非易失性半导体存储器件使用可变电阻元件来存储在第一电极和第二电极之间插入电阻变化层的信息，并且缓冲层插入在第一电极和电阻变化层之间，其中开关界面形成。缓冲层和电阻变化层包括n型金属氧化物，并且选择缓冲层和电阻变化层的材料，使得构成缓冲层的n型金属氧化物的导带的底部的能量为低于构成电阻变化层的n型金属氧化物。

2. 发明申请

US20120025163A1 NON-VOLATILE SEMICONDUCTOR DEVICE 有权
标题翻译：非挥发性半导体器件
公开(公告)号：US20120025163A1
公开(公告)日：2012-02-02
申请号：US13182696
申请日：2011-07-14
申请人： Junya ONISHI , Shinobu Yamazaki , Kazuya Ishihara , Yushi Inoue , Yukio Tamai , Nobuyoshi Awaya
发明人： Junya ONISHI , Shinobu Yamazaki , Kazuya Ishihara , Yushi Inoue , Yukio Tamai , Nobuyoshi Awaya
IPC分类号： H01L45/00
CPC分类号： H01L45/04 , H01L27/2436 , H01L45/1233 , H01L45/146
摘要： A variable resistance element that can stably perform a switching operation with a property variation being reduced by suppressing a sharp current that accompanies completion of forming process, and a non-volatile semiconductor memory device including the variable resistance element are realized. The non-volatile semiconductor memory device uses the variable resistance element for storing information in which a resistance changing layer is interposed between a first electrode and a second electrode, and a buffer layer is inserted between the first electrode and the resistance changing layer where a switching interface is formed. The buffer layer and the resistance changing layer include n-type metal oxides, and materials of the buffer layer and the resistance changing layer are selected such that energy at a bottom of a conduction band of the n-type metal oxide configuring the buffer layer is lower than that of the n-type metal oxide configuring the resistance changing layer.
摘要翻译：通过抑制伴随着成形处理的完成的尖锐电流，可以稳定地进行具有特性变化的开关动作的可变电阻元件，以及包括该可变电阻元件的非易失性半导体存储器件。非易失性半导体存储器件使用可变电阻元件来存储在第一电极和第二电极之间插入电阻变化层的信息，并且缓冲层插入在第一电极和电阻变化层之间，其中开关界面形成。缓冲层和电阻变化层包括n型金属氧化物，并且选择缓冲层和电阻变化层的材料，使得构成缓冲层的n型金属氧化物的导带的底部的能量为低于构成电阻变化层的n型金属氧化物。

3. 发明授权

US07615459B1 Manufacturing method for variable resistive element 有权
标题翻译：可变电阻元件的制造方法
公开(公告)号：US07615459B1
公开(公告)日：2009-11-10
申请号：US12190398
申请日：2008-08-12
申请人： Yushi Inoue , Tetsuya Ohnishi , Kazuya Ishihara , Takahiro Shibiuya , Yasunari Hosoi , Shinobu Yamazaki , Takashi Nakano
发明人： Yushi Inoue , Tetsuya Ohnishi , Kazuya Ishihara , Takahiro Shibiuya , Yasunari Hosoi , Shinobu Yamazaki , Takashi Nakano
IPC分类号： H01L21/20
CPC分类号： H01L45/04 , H01L45/1226 , H01L45/124 , H01L45/146 , H01L45/1633
摘要： A manufacturing method for a variable resistive element according to which a stable switching operation can be achieved with excellent reproducibility is provided. A conductive thin film is deposited on a semiconductor substrate and patterned to a predetermined form, and after that, a first interlayer insulating film is deposited. An opening is then created in a predetermined location on the first interlayer insulating film in such a manner that the upper surface of the conductive thin film is exposed and the thickness of the conductive thin film formed at the bottom of this opening is reduced through processing, and after that, an oxidation process is carried out on the periphery of the exposed conductive thin film. As a result, a variable resistor film is formed in the peripheral region of the opening, and this variable resistor film divides the conductive thin film into a first electrode and a second electrode.
摘要翻译：提供了一种可变电阻元件的制造方法，其中可以以优异的再现性实现稳定的开关操作。将导电薄膜沉积在半导体衬底上并图案化为预定形式，之后沉积第一层间绝缘膜。然后在第一层间绝缘膜上的预定位置处以导电薄膜的上表面露出并且形成在该开口底部的导电薄膜的厚度通过加工而减小的方式形成开口，之后，在露出的导电性薄膜的周围进行氧化处理。结果，在开口的周边区域中形成可变电阻膜，该可变电阻膜将导电薄膜分成第一电极和第二电极。

4. 发明授权

US06251805B1 Method of fabricating semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US06251805B1
公开(公告)日：2001-06-26
申请号：US08993681
申请日：1997-12-18
申请人： Takahisa Yamaha , Yushi Inoue
发明人： Takahisa Yamaha , Yushi Inoue
IPC分类号： H01L2131
CPC分类号： H01L21/02164 , H01L21/02134 , H01L21/02282 , H01L21/02337 , H01L21/31051 , H01L21/3124 , H01L21/316
摘要： A hydrogen silsesquloxane resin film is formed flat by spin-coating or another such method on the surface of a semiconductor substrate or another such treatment wafer 38, after which the above-mentioned resin film is subjected to a heat treatment in an inert gas atmosphere to form a silicon oxide film of preceramic phase. In a hot plate type of heating apparatus, the wafer 38 is placed on a conveyor belt 34 and moved above a heat-generating block 30, which heats the wafer in the open air and converts the preceramic-phase silicon oxide film into a ceramic-phase silicon oxide film. The silane generated during heating does not adhere to the wafer surface as SiO2 particles, so no microscopic protrusions are produced. N2 or another such inert gas may be blown at the wafer 38 during heating.
摘要翻译：在半导体基板或另一个这样的处理晶片38的表面上，通过旋涂或其他这种方法将氢硅倍半酚树脂膜平坦地形成，之后将上述树脂膜在惰性气体气氛中进行热处理形成前陶瓷相的氧化硅膜。在热板式加热装置中，将晶片38放置在输送带34上并移动到发热块30上方，该发热块30在露天加热晶片，并将陶瓷前氧化硅膜转换为陶瓷 - 相氧化硅膜。在加热过程中产生的硅烷作为SiO 2颗粒不粘附到晶片表面，因此不产生微观突起。在加热期间，可以在晶片38上吹入N 2或另一种这样的惰性气体。

5. 发明授权

US5885857A Semiconductor chip capable of suppressing cracks in the insulating layer 失效
标题翻译：能够抑制绝缘层的裂纹的半导体芯片
公开(公告)号：US5885857A
公开(公告)日：1999-03-23
申请号：US7619
申请日：1998-01-15
申请人： Takahisa Yamaha , Yushi Inoue , Masaru Naito
发明人： Takahisa Yamaha , Yushi Inoue , Masaru Naito
IPC分类号： H01L23/52 , H01L21/316 , H01L21/3205 , H01L21/768 , H01L23/31 , H01L23/522 , H01L21/283 , H01L21/306 , H01L21/311
CPC分类号： H01L23/3171 , H01L2924/0002
摘要： A resin molded semiconductor device having wiring layers and interlayer insulating layers inclusive of an SOG film, capable of suppressing generation of cracks in an SOG film to be caused by thermal stress. In the outer peripheral area of a semiconductor chip, via holes are formed in an interlayer insulating layer inclusive of an SOG film to substantially reduce residual SOG film. As an underlying layer of the interlayer insulating layer inclusive of the SOG film, dummy wiring patterns are formed to thin the SOG film on the dummy wiring patterns. Dummy wiring patterns may also be formed by using a higher level wiring layer, burying the via holes and contacting the lower level dummy wiring patterns.
摘要翻译：一种树脂模制半导体器件，其具有布线层和包括SOG膜的层间绝缘层，能够抑制由于热应力引起的SOG膜中的裂纹的产生。在半导体芯片的外周区域中，在包括SOG膜的层间绝缘层中形成通孔，以显着减少残留的SOG膜。作为包含SOG膜的层间绝缘层的下层，形成虚拟布线图案，以使虚拟布线图案上的SOG膜变薄。也可以通过使用较高级布线层，埋入通孔并接触下层虚拟布线图案来形成虚拟布线图案。

6. 发明申请

US20060105541A1 Trench isolation method for semiconductor devices 审中-公开
标题翻译：半导体器件的沟槽隔离方法
公开(公告)号：US20060105541A1
公开(公告)日：2006-05-18
申请号：US11272668
申请日：2005-11-15
申请人： Yushi Inoue
发明人： Yushi Inoue
IPC分类号： H01L21/76
CPC分类号： H01L21/76235
摘要： A trench isolation method for semiconductor devices, the method includes the steps of: successively depositing a pad oxide film and a nitride film on a semiconductor substrate and then selectively removing the pad oxide film and the nitride film to form a mask pattern; forming trench regions in the semiconductor substrate using the formed mask pattern; depositing a thermal oxide film on side walls and bottoms of the formed trench regions by thermal oxidation; depositing on the semiconductor substrate having the trench regions a first buried oxide film having such a thickness that the trench regions are not completely filled by thermal CVD using SiH4/N2O gas; depositing a plasma oxide film as a second buried oxide film, by HDP plasma CVD, such that the trench regions are filled with the film; and removing upper portions of the first and second buried oxide films by CMP (chemical mechanical polishing) using the nitride film as a stopper and then etching away the nitride film and the pad oxide film, wherein the gas flow-rate ratio of SiH4/N2O is set to such a ratio that formation of fine foreign substances in the first buried oxide film can be suppressed in the step of depositing the first buried oxide film.
摘要翻译：一种半导体器件的沟槽隔离方法，该方法包括以下步骤：在半导体衬底上依次沉积衬垫氧化物膜和氮化物膜，然后选择性地去除衬底氧化物膜和氮化物膜以形成掩模图案; 使用所形成的掩模图案在半导体衬底中形成沟槽区域; 通过热氧化在形成的沟槽区域的侧壁和底部上沉积热氧化膜; 在具有沟槽区域的半导体衬底上沉积第一掩埋氧化物膜，该第一掩埋氧化物膜具有这样的厚度，即使用SiH 4 / N 2 O 2，通过热CVD不完全填充沟槽区域加油站; 通过HDP等离子体CVD沉积作为第二掩埋氧化物膜的等离子体氧化物膜，使得沟槽区域被膜填充; 并通过CMP（化学机械抛光），使用氮化物膜作为阻挡层去除第一和第二掩埋氧化物膜的上部，然后蚀刻掉氮化物膜和衬垫氧化膜，其中SiH 4 2 O设定为在沉积第一掩埋氧化膜的步骤中能够抑制在第一掩埋氧化膜中形成细小异物的比例。

7. 发明授权

US06503849B1 Method for forming insulating film 失效
标题翻译：绝缘膜的形成方法
公开(公告)号：US06503849B1
公开(公告)日：2003-01-07
申请号：US09680951
申请日：2000-10-10
申请人： Yoshihiro Ooishi , Yushi Inoue
发明人： Yoshihiro Ooishi , Yushi Inoue
IPC分类号： H01L2102
CPC分类号： H01L21/76802 , C23C18/1208 , C23C18/1279 , H01L21/316 , H01L21/76801
摘要： A method for forming an insulating film, wherein a precursor film of a coating type insulating film having Si—H bonding is coated, the precursor film is calcined in an atmosphere containing at least one of an inert gas and oxygen gas for converting it into a ceramic film as the insulating film, and then the ceramic film is cooled under reduced pressure lower than that for the calcination.
摘要翻译：一种形成绝缘膜的方法，其中涂覆具有Si-H键的涂层型绝缘膜的前体膜，所述前体膜在包含惰性气体和氧气中的至少一种的气氛中煅烧，以将其转化为陶瓷膜作为绝缘膜，然后将陶瓷膜在低于煅烧时的减压下冷却。

8. 发明授权

US5976966A Converting a hydrogen silsesquioxane film to an oxide using a first heat treatment and a second heat treatment with the second heat treatment using rapid thermal processing 失效
标题翻译：使用第一热处理和第二热处理将氢倍半硅氧烷膜转化为氧化物，使用快速热处理
公开(公告)号：US5976966A
公开(公告)日：1999-11-02
申请号：US964580
申请日：1997-11-05
申请人： Yushi Inoue
发明人： Yushi Inoue
IPC分类号： H01L21/312 , H01L21/314 , H01L21/316 , H01L21/768 , H01L23/522 , H01L21/4763
CPC分类号： H01L21/02164 , H01L21/02134 , H01L21/02282 , H01L21/02337 , H01L21/3124 , H01L21/316 , H01L21/76801 , H01L21/76828 , H01L21/76814
摘要： An insulating film is formed by CVD on the surface of a semiconductor substrate formed with circuit elements such as transistors, and thereafter a hydrogen silsesquioxane resin film is formed on the insulating film by spin-coating or the like. This resin film is sequentially subjected to low temperature annealing at 400.degree. C. or lower and then to high temperature annealing at 700.degree. C. or higher. The low temperature annealing changes the resin film into a silicon oxide film, and the high temperature annealing is performed in order to make dense the film quality of the silicon oxide film. The high temperature annealing is performed by rapid thermal annealing in an oxidizing atmosphere of water vapor or the like. A CVD insulating film is formed on the densified silicon oxide film and planarized by CMP or the like, according to necessity. A contact hole is formed through the CVD insulating film, densified silicon oxide film and the insulating film, and a wiring layer is thereafter deposited.
摘要翻译：在由诸如晶体管的电路元件形成的半导体衬底的表面上通过CVD形成绝缘膜，然后通过旋涂等在绝缘膜上形成氢倍半硅氧烷树脂膜。该树脂膜依次在400℃以下进行低温退火，然后在700℃以上进行高温退火。低温退火将树脂膜变更为氧化硅膜，进行高温退火以使氧化硅膜的膜质量密集。高温退火通过在水蒸气等的氧化气氛中快速热退火进行。根据需要，在致密化的氧化硅膜上形成CVD绝缘膜，并通过CMP等进行平坦化。通过CVD绝缘膜，致密氧化硅膜和绝缘膜形成接触孔，然后沉积布线层。

9. 发明授权

US09159664B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US09159664B2
公开(公告)日：2015-10-13
申请号：US13178093
申请日：2011-07-07
申请人： Yushi Inoue , Yukitoshi Hirose
发明人： Yushi Inoue , Yukitoshi Hirose
IPC分类号： H01L23/48 , H01L23/498 , H01L23/64 , H01L23/00 , H01L25/065 , H01L23/31
CPC分类号： H01L23/49838 , H01L23/3128 , H01L23/64 , H01L24/48 , H01L24/49 , H01L24/73 , H01L25/0657 , H01L2224/05554 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48145 , H01L2224/48227 , H01L2224/49171 , H01L2224/49175 , H01L2224/73265 , H01L2225/06506 , H01L2225/0651 , H01L2225/06527 , H01L2225/06562 , H01L2225/06575 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/0102 , H01L2924/01033 , H01L2924/014 , H01L2924/15311 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/05599
摘要： A semiconductor device may include, but is not limited to: a wiring hoard; and first and second chips stacked over the wiring board. The wiring board includes a plurality of first data terminals and a plurality of second data terminals. One of the first and second chips is sandwiched between the wiring board and the other of the first and second chips. The first chip includes a plurality of first data pads. The second chip includes a plurality of second data pads and a plurality of third data pads. The first data terminals of the wiring board are electrically connected respectively to the first data pads of the first chip and further respectively to the second data pads of the second chip. The second data terminals are electrically connected respectively to the third data pads of the second chip and electrically disconnected from the first chip.
摘要翻译：半导体器件可以包括但不限于：布线板; 以及堆叠在布线板上的第一和第二芯片。布线板包括多个第一数据终端和多个第二数据终端。第一和第二芯片中的一个夹在布线板和第一和第二芯片中的另一个之间。第一芯片包括多个第一数据焊盘。第二芯片包括多个第二数据焊盘和多个第三数据焊盘。布线板的第一数据端子分别电连接到第一芯片的第一数据焊盘，并且进一步分别连接到第二芯片的第二数据焊盘。第二数据端子分别电连接到第二芯片的第三数据焊盘，并与第一芯片电断开。

10. 发明授权

US07402513B2 Method for forming interlayer insulation film 有权
标题翻译：形成层间绝缘膜的方法
公开(公告)号：US07402513B2
公开(公告)日：2008-07-22
申请号：US11034616
申请日：2005-01-12
申请人： Takanori Sonoda , Kazumasa Mitsumune , Kenichiroh Abe , Yushi Inoue , Tsukasa Doi
发明人： Takanori Sonoda , Kazumasa Mitsumune , Kenichiroh Abe , Yushi Inoue , Tsukasa Doi
IPC分类号： H01L21/461 , H01L21/4763 , H01L21/469
CPC分类号： H01L21/0217 , H01L21/02164 , H01L21/02271 , H01L21/02274 , H01L21/02318 , H01L21/3143 , H01L21/31625 , H01L21/3185 , H01L21/76825 , H01L21/76826 , H01L21/76828 , H01L21/76829 , H01L21/76837
摘要： It is an object of the present invention to provide a method for forming an interlayer insulation film suppressing the occurrence of voids in the interlayer insulation film.A method for forming an interlayer insulation film of the present invention, comprising the steps of: (1) forming an etching stopper film of a silicon nitride film on an entire surface including a step part on a semiconductor substrate having the step part with an aspect ratio of ≧3; (2) forming an interlayer insulation film of an impurity-doped silicate film on the silicon nitride film; and (3) performing reflow of the interlayer insulation film by a heat treatment, wherein the formation of the silicon nitride film is controlled such that the N—H bond density of the silicon nitride film is 1.0×1022 pieces/cm3 or less.According to the method for forming the interlayer insulation film of the present invention, the occurrence of the voids can be suppressed in the interlayer insulation film even if the aspect ratio of the step part formed on the semiconductor substrate is 3 or more. Also, the damage applied to the semiconductor device by reflow can be reduced.
摘要翻译：本发明的目的是提供一种形成层间绝缘膜的方法，该层间绝缘膜抑制层间绝缘膜中空隙的发生。一种形成本发明的层间绝缘膜的方法，包括以下步骤：（1）在具有该步骤部分的半导体衬底上的包括台阶部分的整个表面上形成氮化硅膜的蚀刻阻挡膜，该半导体衬底具有一个方面比值> = 3; （2）在氮化硅膜上形成杂质掺杂硅酸盐膜的层间绝缘膜; 和（3）通过热处理进行层间绝缘膜的回流，其中控制氮化硅膜的形成，使得氮化硅膜的NH键密度为1.0×10 22个/ cm 3以下。根据本发明的层间绝缘膜的形成方法，即使形成在半导体基板上的台阶部的纵横比为3以上，也能够抑制层间绝缘膜的空隙的发生。此外，可以减少通过回流施加到半导体器件的损坏。

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