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1. 发明申请

US20120241908A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20120241908A1
公开(公告)日：2012-09-27
申请号：US13488958
申请日：2012-06-05
申请人： Jung-Chih TSAO , Yu-Sheng WANG , Kei-Wei CHEN , Ying-Lang WANG
发明人： Jung-Chih TSAO , Yu-Sheng WANG , Kei-Wei CHEN , Ying-Lang WANG
IPC分类号： H01L29/92
CPC分类号： H01L27/0805 , H01L28/60 , H01L28/75
摘要： A semiconductor device is disclosed. The device includes a substrate; a first metal layer overlying the substrate; a dielectric layer overlying the first metal layer; and a second metal layer overlying the dielectric layer, wherein the first metal layer comprises: a first body-centered cubic lattice metal layer; a first underlayer, underlying the first body-centered cubic lattice metal layer, wherein the first underlayer is metal of body-centered cubic lattice and includes titanium (Ti), tungsten (W), molybdenum (Mo) or niobium (Nb); and a first interface of body-centered cubic lattice between the first body-centered cubic lattice metal layer and the first underlayer.
摘要翻译：公开了一种半导体器件。该装置包括基板; 覆盖衬底的第一金属层; 覆盖在第一金属层上的电介质层; 以及覆盖所述电介质层的第二金属层，其中所述第一金属层包括：第一体心立方晶格金属层; 第一底层，位于第一体心立方晶格金属层下面，其中第一底层是体心立方晶格的金属，包括钛（Ti），钨（W），钼（Mo）或铌（Nb）; 以及在第一体心立方晶格金属层和第一底层之间的体心立方晶格的第一界面。

2. 发明申请

US20130102152A1 SEMICONDUCTOR MANUFACTURING APPARATUS AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体制造装置及制造半导体器件的方法
公开(公告)号：US20130102152A1
公开(公告)日：2013-04-25
申请号：US13277609
申请日：2011-10-20
申请人： Yen-Chang CHAO , Kei-Wei CHEN , Ying-Lang WANG
发明人： Yen-Chang CHAO , Kei-Wei CHEN , Ying-Lang WANG
IPC分类号： H01L21/306 , B24B55/00 , H01L21/304 , B24B41/06
CPC分类号： B24B37/32
摘要： A semiconductor manufacturing apparatus includes at least one inner retaining ring, and an outer retaining ring. The at least one inner retaining ring applies a first pressure to the polishing pad, and retains a substrate on the polishing pad. The outer retaining ring applies a second pressure to the polishing pad, and retains the at least one inner retaining ring on the polishing pad. Control of the first pressure is independent with respect to control of the second pressure.
摘要翻译：半导体制造装置包括至少一个内保持环和外保持环。至少一个内部保持环向抛光垫施加第一压力，并将衬底保持在抛光垫上。外保持环向抛光垫施加第二压力，并且将至少一个内保持环保持在抛光垫上。关于第二压力的控制，第一压力的控制是独立的。

3. 发明申请

US20130210172A1 WAFER THINNING APPARATUS HAVING FEEDBACK CONTROL AND METHOD OF USING 审中-公开
标题翻译：具有反馈控制功能的减速装置和使用方法
公开(公告)号：US20130210172A1
公开(公告)日：2013-08-15
申请号：US13371046
申请日：2012-02-10
申请人： Yuan-Hsuan Chen , Kei-Wei CHEN , Ying-Lang WANG , Kuo-Hsiu WEI
发明人： Yuan-Hsuan Chen , Kei-Wei CHEN , Ying-Lang WANG , Kuo-Hsiu WEI
IPC分类号： H01L21/66 , B24B49/00 , H01L21/306
CPC分类号： H01L21/30625 , B24B37/005 , B24B37/04 , B24B49/00 , B24B49/04 , B24B49/05 , H01L21/304 , H01L22/12 , H01L22/20
摘要： A wafer thinning apparatus includes a first metrology tool configured to measure an initial thickness of the wafer. The wafer thinning apparatus further includes a controller connected to the first metrology tool, and configured to determine a polishing time based on the initial thickness, a predetermined thickness and a material removal rate. The wafer thinning apparatus further includes a polishing tool connected to the controller configured to polish the wafer for a period of time equal to the polishing time. The wafer thinning apparatus includes a second metrology tool connected to the controller and the polishing tool, and configured to measure a polished thickness. The controller is configured to update the material removal rate based on the polished thickness, the predetermined thickness and the polishing time.
摘要翻译：晶片减薄装置包括被配置为测量晶片的初始厚度的第一计量工具。晶片减薄装置还包括连接到第一计量工具的控制器，并且被配置为基于初始厚度，预定厚度和材料移除速率来确定抛光时间。晶片减薄装置还包括连接到控制器的抛光工具，该抛光工具被配置成在等于抛光时间的时间内抛光晶片。晶片减薄装置包括连接到控制器和抛光工具的第二计量工具，并且被配置为测量抛光厚度。控制器被配置为基于抛光厚度，预定厚度和抛光时间更新材料去除速率。

4. 发明申请

US20130288582A1 METHOD OF FORMING DIAMOND CONDITIONERS FOR CMP PROCESS 有权
标题翻译：形成CMP工艺的金刚石调节器的方法
公开(公告)号：US20130288582A1
公开(公告)日：2013-10-31
申请号：US13455448
申请日：2012-04-25
申请人： Yen-Chang CHAO , Kei-Wei CHEN , Ying-Lang WANG
发明人： Yen-Chang CHAO , Kei-Wei CHEN , Ying-Lang WANG
IPC分类号： B24B53/017 , B24D3/06 , B24D3/28 , B24D18/00
CPC分类号： B24B53/12 , B24B53/017 , B24D3/06 , B24D3/28 , B24D18/00
摘要： A method for making a conditioner disk used in a chemical mechanical polishing (CMP) process comprises applying a first layer of at least one binder over a substrate; disposing a plurality of diamond particles on the first layer of the at least one first binder at the plurality of locations; and fixing the plurality of diamond particles to the substrate by heating the substrate to a raised temperature and then cooling the substrate. The plurality of diamond particles disposed over the substrate are configured to provide a working diamond ratio higher than 50% when the conditioner disk is used in a CMP process.
摘要翻译：用于制造在化学机械抛光（CMP）工艺中使用的调节盘的方法包括在衬底上施加至少一种粘合剂的第一层; 在所述多个位置处在所述至少一个第一粘合剂的所述第一层上设置多个金刚石颗粒; 以及通过将衬底加热到升高的温度然后冷却衬底，将多个金刚石颗粒固定到衬底上。设置在基板上的多个金刚石颗粒被配置为当在CMP工艺中使用调节盘时，提供高于50％的工作金刚石比例。

5. 发明申请

US20130210321A1 MODULAR GRINDING APPARATUSES AND METHODS FOR WAFER THINNING 有权
标题翻译：模块化研磨设备及其减薄方法
公开(公告)号：US20130210321A1
公开(公告)日：2013-08-15
申请号：US13370946
申请日：2012-02-10
申请人： Chun-Ting KUO , Kei-Wei CHEN , Ying-Lang WANG , Kuo-Hsiu WEI
发明人： Chun-Ting KUO , Kei-Wei CHEN , Ying-Lang WANG , Kuo-Hsiu WEI
IPC分类号： H01L21/02 , B24B7/00
CPC分类号： H01L21/304 , B24B37/00 , B24B37/042
摘要： Methods of thinning a plurality of semiconductor wafers and apparatuses for carrying out the same are disclosed. A grinding module within a set of grinding modules receives and grinds a semiconductor wafer. A polishing module receives the semiconductor wafer from the grinding module and polishes the wafer. The polishing module is configured to polish the semiconductor wafer in less time than the grinding module is configured to grind the corresponding wafer.
摘要翻译：公开了使多个半导体晶片变薄的方法及其实施方法。一组研磨模块内的研磨模块接收并研磨半导体晶片。抛光模块从研磨模块接收半导体晶片并抛光晶片。抛光模块被配置为在比研磨模块构造成磨碎相应晶片的时间少的时间内抛光半导体晶片。

6. 发明申请

US20120264303A1 CHEMICAL MECHANICAL POLISHING SLURRY, SYSTEM AND METHOD 审中-公开
标题翻译：化学机械抛光浆，系统和方法
公开(公告)号：US20120264303A1
公开(公告)日：2012-10-18
申请号：US13087565
申请日：2011-04-15
申请人： Kei-Wei CHEN , Kuo-Hsiu WEI , Shih-Chieh CHANG , Ying-Lang WANG
发明人： Kei-Wei CHEN , Kuo-Hsiu WEI , Shih-Chieh CHANG , Ying-Lang WANG
IPC分类号： H01L21/306 , B24D11/00 , C09K13/00
CPC分类号： H01L21/3212 , C09G1/02 , C09K3/1463
摘要： A metal polishing slurry includes a chemical solution and abrasives characterized by a bimodal or other multimodal distribution of particle sizes or a prevalence of two or more particle sizes or ranges of particle sizes. A method and system for using the slurry in a CMP polishing operation, are also provided.
摘要翻译：金属抛光浆料包括化学溶液和研磨剂，其特征在于具有双峰或其它多峰分布的颗粒尺寸或具有两种或更多种粒径或颗粒尺寸范围的流行性。还提供了在CMP抛光操作中使用该浆料的方法和系统。

7. 发明申请

US20120235299A1 SEMICONDUCTOR DEVICE CONTACT STRUCTURES AND METHODS FOR MAKING THE SAME 有权
标题翻译：半导体器件接触结构及其制造方法
公开(公告)号：US20120235299A1
公开(公告)日：2012-09-20
申请号：US13049049
申请日：2011-03-16
申请人： Shih Chieh CHANG , Chih-Chung CHANG , Kei-Wei CHEN , Ying-Lang WANG
发明人： Shih Chieh CHANG , Chih-Chung CHANG , Kei-Wei CHEN , Ying-Lang WANG
IPC分类号： H01L23/52 , H01L21/768
CPC分类号： H01L23/53266 , H01L21/2855 , H01L21/76805 , H01L21/76814 , H01L21/76846 , H01L23/485 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor contact structure and method provide contact structures that extend through a dielectric material and provide contact to multiple different subjacent materials including a silicide material and a non-silicide material such as doped silicon. The contact structures includes a lower composite layer formed using a multi-step ionized metal plasma (IMP) deposition operation. A lower IMP film is formed at a high AC bias power followed by the formation of an upper IMP film at a lower AC bias power. The composite layer may be formed of titanium. A further layer is formed as a liner over the composite layer and the liner layer may advantageously be formed using CVD and may be TiN. A conductive plug material such as tungsten or copper fills the contact openings.
摘要翻译：半导体接触结构和方法提供延伸穿过电介质材料并提供与包括硅化物材料和非硅化物材料例如掺杂硅的多个不同下层材料的接触的接触结构。接触结构包括使用多步电离金属等离子体（IMP）沉积操作形成的下复合层。下部IMP膜以高AC偏压功率形成，随后以较低的AC偏压功率形成上部IMP膜。复合层可以由钛形成。在复合层上形成另一层作为衬垫，并且衬垫层可以有利地使用CVD形成，并且可以是TiN。诸如钨或铜的导电插塞材料填充接触开口。

8. 发明申请

US20130220090A1 WAFER EDGE TRIM BLADE WITH SLOTS 有权
标题翻译： WAFER EDGE TRIM刀片与SLOTS
公开(公告)号：US20130220090A1
公开(公告)日：2013-08-29
申请号：US13408327
申请日：2012-02-29
申请人： Chun-Ting KUO , Kei-Wei CHEN , Ying-Lang WANG , Kuo-Hsiu WEI
发明人： Chun-Ting KUO , Kei-Wei CHEN , Ying-Lang WANG , Kuo-Hsiu WEI
IPC分类号： B26D1/14 , B26D7/18 , B24D3/00
CPC分类号： B26D7/18 , B23D61/02 , B23D61/021 , B24D5/02 , B24D5/12 , B26D1/143 , B28D1/04 , B28D1/121 , B28D5/022 , Y10T83/0448 , Y10T83/9372
摘要： A wafer edge trim blade includes a round blade body and at least one slot formed inward from an outside edge of the round blade body. The at least one slot is configured to remove debris generated during wafer edge trimming using the wafer edge trim blade.
摘要翻译：晶片边缘修剪刀片包括圆形刀片本体和从圆刀片本体的外边缘向内形成的至少一个槽。所述至少一个槽被配置成使用晶片边缘修剪刀片去除在晶片边缘修整期间产生的碎屑。

9. 发明申请

US20130181258A1 IMAGE SENSOR AND METHOD OF MANUFACTURING 有权
标题翻译：图像传感器及其制造方法
公开(公告)号：US20130181258A1
公开(公告)日：2013-07-18
申请号：US13349221
申请日：2012-01-12
申请人： Shiu-Ko JangJian , Kei-Wei CHEN , Szu-An WU , Ying-Lang WANG
发明人： Shiu-Ko JangJian , Kei-Wei CHEN , Szu-An WU , Ying-Lang WANG
IPC分类号： H01L27/148 , H01L27/146
CPC分类号： H01L27/14621 , H01L27/14623 , H01L27/1464
摘要： An image sensor includes a substrate having opposite first and second sides, a multilayer structure on the first side of the substrate, and a photo-sensitive element on the second side of the substrate. The photo-sensitive element is configured to receive light that is incident upon the first side and transmitted through the multilayer structure and the substrate. The multilayer structure includes first and second light transmitting layers. The first light transmitting layer is sandwiched between the substrate and the second light transmitting layer. The first light transmitting layer has a refractive index that is from 60% to 90% of a refractive index of the substrate. The second light transmitting layer has a refractive index that is lower than the refractive index of the first light transmitting layer and is from 40% to 70% of the refractive index of the substrate.
摘要翻译：图像传感器包括具有相对的第一和第二侧的基板，在基板的第一侧上的多层结构和在基板的第二侧上的感光元件。光敏元件被配置为接收入射在第一侧并透过多层结构和基板的光。该多层结构包括第一和第二透光层。第一透光层夹在基板和第二透光层之间。第一透光层的折射率为基板折射率的60％至90％。第二透光层的折射率低于第一透光层的折射率，为基板的折射率的40％〜70％。

10. 发明申请

US20130049101A1 SEMICONDUCTOR DEVICES UTILIZING PARTIALLY DOPED STRESSOR FILM PORTIONS AND METHODS FOR FORMING THE SAME 有权
标题翻译：利用局部压电薄膜薄膜部分的半导体器件及其形成方法
公开(公告)号：US20130049101A1
公开(公告)日：2013-02-28
申请号：US13221160
申请日：2011-08-30
申请人： Wen Chu HSIAO , Ju Wen HSIAO , Ying Min CHOU , Hsiang Hsiang KO , Ying-Lang WANG
发明人： Wen Chu HSIAO , Ju Wen HSIAO , Ying Min CHOU , Hsiang Hsiang KO , Ying-Lang WANG
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66636 , H01L21/02529 , H01L21/02532 , H01L21/02535 , H01L21/0262 , H01L21/30604 , H01L29/165 , H01L29/167 , H01L29/7834 , H01L29/7848
摘要： A semiconductor structure and method for forming the same provide a high mobility stressor material suitable for use as source/drain regions or other active devices. The structure is formed in a substrate opening and is doped with an impurity such as boron in upper portions but is void of the impurity in regions that contact the surfaces of the opening. The structure is therefore resistant to out-diffusion of the dopant impurity during high temperature operations and may be formed through selective deposition using reduced pressure chemical vapor deposition or reduced pressure epitaxial deposition.
摘要翻译：半导体结构及其形成方法提供适合用作源极/漏极区域或其它有源器件的高迁移率应力源材料。该结构形成在衬底开口中，并且在上部掺杂有诸如硼的杂质，但是在与开口的表面接触的区域中不含杂质。因此，该结构在高温操作期间抵抗掺杂剂杂质的扩散，并且可以通过使用减压化学气相沉积或减压外延沉积的选择性沉积来形成。

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